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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <string.h>
  25
  26 #include "arm7_9_common.h"
  27 #include "etb.h"
  28 #include "etm.h"
  29
  30 #include "log.h"
  31 #include "types.h"
  32 #include "binarybuffer.h"
  33 #include "target.h"
  34 #include "register.h"
  35 #include "jtag.h"
  36
  37 #include <stdlib.h>
  38
  39 static char* etb_reg_list[] =
  40 {
  41         "ETB_identification",
  42         "ETB_ram_depth",
  43         "ETB_ram_width",
  44         "ETB_status",
  45         "ETB_ram_data",
  46         "ETB_ram_read_pointer",
  47         "ETB_ram_write_pointer",
  48         "ETB_trigger_counter",
  49         "ETB_control",
  50 };
  51
  52 static int etb_reg_arch_type = -1;
  53
  54 static int etb_get_reg(reg_t *reg);
  55
  56 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  57
  58 static int etb_set_instr(etb_t *etb, u32 new_instr)
  59 {
  60         jtag_tap_t *tap;
  61         tap = etb->tap;
  62         if (tap==NULL)
  63                 return ERROR_FAIL;
  64
  65         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
  66         {
  67                 scan_field_t field;
  68
  69                 field.tap = tap;
  70                 field.num_bits = tap->ir_length;
  71                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  72                 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
  73
  74                 field.in_value = NULL;
  75
  76
  77                 field.in_handler = NULL;
  78
  79
  80                 jtag_add_ir_scan(1, &field, TAP_INVALID);
  81
  82                 free(field.out_value);
  83         }
  84
  85         return ERROR_OK;
  86 }
  87
  88 static int etb_scann(etb_t *etb, u32 new_scan_chain)
  89 {
  90         if(etb->cur_scan_chain != new_scan_chain)
  91         {
  92                 scan_field_t field;
  93
  94                 field.tap = etb->tap;
  95                 field.num_bits = 5;
  96                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  97                 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
  98
  99                 field.in_value = NULL;
 100
 101
 102                 field.in_handler = NULL;
 103
 104
 105                 /* select INTEST instruction */
 106                 etb_set_instr(etb, 0x2);
 107                 jtag_add_dr_scan(1, &field, TAP_INVALID);
 108
 109                 etb->cur_scan_chain = new_scan_chain;
 110
 111                 free(field.out_value);
 112         }
 113
 114         return ERROR_OK;
 115 }
 116
 117 reg_cache_t* etb_build_reg_cache(etb_t *etb)
 118 {
 119         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 120         reg_t *reg_list = NULL;
 121         etb_reg_t *arch_info = NULL;
 122         int num_regs = 9;
 123         int i;
 124
 125         /* register a register arch-type for etm registers only once */
 126         if (etb_reg_arch_type == -1)
 127                 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
 128
 129         /* the actual registers are kept in two arrays */
 130         reg_list = calloc(num_regs, sizeof(reg_t));
 131         arch_info = calloc(num_regs, sizeof(etb_reg_t));
 132
 133         /* fill in values for the reg cache */
 134         reg_cache->name = "etb registers";
 135         reg_cache->next = NULL;
 136         reg_cache->reg_list = reg_list;
 137         reg_cache->num_regs = num_regs;
 138
 139         /* set up registers */
 140         for (i = 0; i < num_regs; i++)
 141         {
 142                 reg_list[i].name = etb_reg_list[i];
 143                 reg_list[i].size = 32;
 144                 reg_list[i].dirty = 0;
 145                 reg_list[i].valid = 0;
 146                 reg_list[i].bitfield_desc = NULL;
 147                 reg_list[i].num_bitfields = 0;
 148                 reg_list[i].value = calloc(1, 4);
 149                 reg_list[i].arch_info = &arch_info[i];
 150                 reg_list[i].arch_type = etb_reg_arch_type;
 151                 reg_list[i].size = 32;
 152                 arch_info[i].addr = i;
 153                 arch_info[i].etb = etb;
 154         }
 155
 156         return reg_cache;
 157 }
 158
 159 static int etb_get_reg(reg_t *reg)
 160 {
 161         int retval;
 162         if ((retval = etb_read_reg(reg)) != ERROR_OK)
 163         {
 164                 LOG_ERROR("BUG: error scheduling etm register read");
 165                 return retval;
 166         }
 167
 168         if ((retval = jtag_execute_queue()) != ERROR_OK)
 169         {
 170                 LOG_ERROR("register read failed");
 171                 return retval;
 172         }
 173
 174         return ERROR_OK;
 175 }
 176
 177 static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
 178 {
 179         scan_field_t fields[3];
 180         int i;
 181
 182         jtag_add_end_state(TAP_IDLE);
 183         etb_scann(etb, 0x0);
 184         etb_set_instr(etb, 0xc);
 185
 186         fields[0].tap = etb->tap;
 187         fields[0].num_bits = 32;
 188         fields[0].out_value = NULL;
 189         u8 tmp[4];
 190         fields[0].in_value = tmp;
 191         fields[0].in_handler = NULL;
 192
 193         fields[1].tap = etb->tap;
 194         fields[1].num_bits = 7;
 195         fields[1].out_value = malloc(1);
 196         buf_set_u32(fields[1].out_value, 0, 7, 4);
 197         fields[1].in_value = NULL;
 198         fields[1].in_handler = NULL;
 199
 200         fields[2].tap = etb->tap;
 201         fields[2].num_bits = 1;
 202         fields[2].out_value = malloc(1);
 203         buf_set_u32(fields[2].out_value, 0, 1, 0);
 204         fields[2].in_value = NULL;
 205         fields[2].in_handler = NULL;
 206
 207         jtag_add_dr_scan(3, fields, TAP_INVALID);
 208
 209
 210         for (i = 0; i < num_frames; i++)
 211         {
 212                 /* ensure nR/W reamins set to read */
 213                 buf_set_u32(fields[2].out_value, 0, 1, 0);
 214
 215                 /* address remains set to 0x4 (RAM data) until we read the last frame */
 216                 if (i < num_frames - 1)
 217                         buf_set_u32(fields[1].out_value, 0, 7, 4);
 218                 else
 219                         buf_set_u32(fields[1].out_value, 0, 7, 0);
 220
 221                 jtag_add_dr_scan_now(3, fields, TAP_INVALID);
 222
 223                 data[i]=buf_get_u32(tmp, 0, 32);
 224         }
 225
 226         jtag_execute_queue();
 227
 228         free(fields[1].out_value);
 229         free(fields[2].out_value);
 230
 231         return ERROR_OK;
 232 }
 233
 234 int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 235 {
 236         etb_reg_t *etb_reg = reg->arch_info;
 237         u8 reg_addr = etb_reg->addr & 0x7f;
 238         scan_field_t fields[3];
 239
 240         LOG_DEBUG("%i", etb_reg->addr);
 241
 242         jtag_add_end_state(TAP_IDLE);
 243         etb_scann(etb_reg->etb, 0x0);
 244         etb_set_instr(etb_reg->etb, 0xc);
 245
 246         fields[0].tap = etb_reg->etb->tap;
 247         fields[0].num_bits = 32;
 248         fields[0].out_value = reg->value;
 249
 250         fields[0].in_value = NULL;
 251
 252
 253         fields[0].in_handler = NULL;
 254
 255
 256         fields[1].tap = etb_reg->etb->tap;
 257         fields[1].num_bits = 7;
 258         fields[1].out_value = malloc(1);
 259         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 260
 261         fields[1].in_value = NULL;
 262
 263
 264         fields[1].in_handler = NULL;
 265
 266
 267         fields[2].tap = etb_reg->etb->tap;
 268         fields[2].num_bits = 1;
 269         fields[2].out_value = malloc(1);
 270         buf_set_u32(fields[2].out_value, 0, 1, 0);
 271
 272         fields[2].in_value = NULL;
 273
 274
 275         fields[2].in_handler = NULL;
 276
 277
 278         jtag_add_dr_scan(3, fields, TAP_INVALID);
 279
 280         /* read the identification register in the second run, to make sure we
 281          * don't read the ETB data register twice, skipping every second entry
 282          */
 283         buf_set_u32(fields[1].out_value, 0, 7, 0x0);
 284         fields[0].in_value = reg->value;
 285
 286         jtag_add_dr_scan(3, fields, TAP_INVALID);
 287
 288         jtag_check_value_mask(fields+0, check_value, check_mask);
 289
 290         free(fields[1].out_value);
 291         free(fields[2].out_value);
 292
 293         return ERROR_OK;
 294 }
 295
 296 int etb_read_reg(reg_t *reg)
 297 {
 298         return etb_read_reg_w_check(reg, NULL, NULL);
 299 }
 300
 301 int etb_set_reg(reg_t *reg, u32 value)
 302 {
 303         int retval;
 304         if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
 305         {
 306                 LOG_ERROR("BUG: error scheduling etm register write");
 307                 return retval;
 308         }
 309
 310         buf_set_u32(reg->value, 0, reg->size, value);
 311         reg->valid = 1;
 312         reg->dirty = 0;
 313
 314         return ERROR_OK;
 315 }
 316
 317 int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
 318 {
 319         int retval;
 320         etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 321
 322         if ((retval = jtag_execute_queue()) != ERROR_OK)
 323         {
 324                 LOG_ERROR("register write failed");
 325                 return retval;
 326         }
 327         return ERROR_OK;
 328 }
 329
 330 int etb_write_reg(reg_t *reg, u32 value)
 331 {
 332         etb_reg_t *etb_reg = reg->arch_info;
 333         u8 reg_addr = etb_reg->addr & 0x7f;
 334         scan_field_t fields[3];
 335
 336         LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
 337
 338         jtag_add_end_state(TAP_IDLE);
 339         etb_scann(etb_reg->etb, 0x0);
 340         etb_set_instr(etb_reg->etb, 0xc);
 341
 342         fields[0].tap = etb_reg->etb->tap;
 343         fields[0].num_bits = 32;
 344         fields[0].out_value = malloc(4);
 345         buf_set_u32(fields[0].out_value, 0, 32, value);
 346
 347         fields[0].in_value = NULL;
 348
 349
 350         fields[0].in_handler = NULL;
 351
 352
 353         fields[1].tap = etb_reg->etb->tap;
 354         fields[1].num_bits = 7;
 355         fields[1].out_value = malloc(1);
 356         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 357
 358         fields[1].in_value = NULL;
 359
 360
 361         fields[1].in_handler = NULL;
 362
 363
 364         fields[2].tap = etb_reg->etb->tap;
 365         fields[2].num_bits = 1;
 366         fields[2].out_value = malloc(1);
 367         buf_set_u32(fields[2].out_value, 0, 1, 1);
 368
 369         fields[2].in_value = NULL;
 370
 371
 372         fields[2].in_handler = NULL;
 373
 374
 375         jtag_add_dr_scan(3, fields, TAP_INVALID);
 376
 377         free(fields[0].out_value);
 378         free(fields[1].out_value);
 379         free(fields[2].out_value);
 380
 381         return ERROR_OK;
 382 }
 383
 384 int etb_store_reg(reg_t *reg)
 385 {
 386         return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 387 }
 388
 389 static int etb_register_commands(struct command_context_s *cmd_ctx)
 390 {
 391         command_t *etb_cmd;
 392
 393         etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
 394
 395         register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
 396
 397         return ERROR_OK;
 398 }
 399
 400 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 401 {
 402         target_t *target;
 403         jtag_tap_t *tap;
 404         armv4_5_common_t *armv4_5;
 405         arm7_9_common_t *arm7_9;
 406
 407         if (argc != 2)
 408         {
 409                 return ERROR_COMMAND_SYNTAX_ERROR;
 410         }
 411
 412         target = get_target_by_num(strtoul(args[0], NULL, 0));
 413
 414         if (!target)
 415         {
 416                 LOG_ERROR("target number '%s' not defined", args[0]);
 417                 return ERROR_FAIL;
 418         }
 419
 420         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 421         {
 422                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 423                 return ERROR_FAIL;
 424         }
 425
 426         tap = jtag_TapByString( args[1] );
 427         if( tap == NULL ){
 428                 command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
 429                 return ERROR_FAIL;
 430         }
 431
 432
 433         if (arm7_9->etm_ctx)
 434         {
 435                 etb_t *etb = malloc(sizeof(etb_t));
 436
 437                 arm7_9->etm_ctx->capture_driver_priv = etb;
 438
 439                 etb->tap  = tap;
 440                 etb->cur_scan_chain = 0xffffffff;
 441                 etb->reg_cache = NULL;
 442                 etb->ram_width = 0;
 443                 etb->ram_depth = 0;
 444         }
 445         else
 446         {
 447                 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
 448                 return ERROR_FAIL;
 449         }
 450
 451         return ERROR_OK;
 452 }
 453
 454 static int etb_init(etm_context_t *etm_ctx)
 455 {
 456         etb_t *etb = etm_ctx->capture_driver_priv;
 457
 458         etb->etm_ctx = etm_ctx;
 459
 460         /* identify ETB RAM depth and width */
 461         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
 462         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
 463         jtag_execute_queue();
 464
 465         etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
 466         etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
 467
 468         return ERROR_OK;
 469 }
 470
 471 static trace_status_t etb_status(etm_context_t *etm_ctx)
 472 {
 473         etb_t *etb = etm_ctx->capture_driver_priv;
 474
 475         etb->etm_ctx = etm_ctx;
 476
 477         /* if tracing is currently idle, return this information */
 478         if (etm_ctx->capture_status == TRACE_IDLE)
 479         {
 480                 return etm_ctx->capture_status;
 481         }
 482         else if (etm_ctx->capture_status & TRACE_RUNNING)
 483         {
 484                 reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
 485                 int etb_timeout = 100;
 486
 487                 /* trace is running, check the ETB status flags */
 488                 etb_get_reg(etb_status_reg);
 489
 490                 /* check Full bit to identify an overflow */
 491                 if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
 492                         etm_ctx->capture_status |= TRACE_OVERFLOWED;
 493
 494                 /* check Triggered bit to identify trigger condition */
 495                 if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
 496                         etm_ctx->capture_status |= TRACE_TRIGGERED;
 497
 498                 /* check AcqComp to identify trace completion */
 499                 if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
 500                 {
 501                         while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
 502                         {
 503                                 /* wait for data formatter idle */
 504                                 etb_get_reg(etb_status_reg);
 505                         }
 506
 507                         if (etb_timeout == 0)
 508                         {
 509                                 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
 510                                         buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
 511                         }
 512
 513                         if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
 514                         {
 515                                 LOG_ERROR("trace completed, but no trigger condition detected");
 516                         }
 517
 518                         etm_ctx->capture_status &= ~TRACE_RUNNING;
 519                         etm_ctx->capture_status |= TRACE_COMPLETED;
 520                 }
 521         }
 522
 523         return etm_ctx->capture_status;
 524 }
 525
 526 static int etb_read_trace(etm_context_t *etm_ctx)
 527 {
 528         etb_t *etb = etm_ctx->capture_driver_priv;
 529         int first_frame = 0;
 530         int num_frames = etb->ram_depth;
 531         u32 *trace_data = NULL;
 532         int i, j;
 533
 534         etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
 535         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
 536         jtag_execute_queue();
 537
 538         /* check if we overflowed, and adjust first frame of the trace accordingly
 539          * if we didn't overflow, read only up to the frame that would be written next,
 540          * i.e. don't read invalid entries
 541          */
 542         if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
 543         {
 544                 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 545         }
 546         else
 547         {
 548                 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 549         }
 550
 551         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
 552
 553         /* read data into temporary array for unpacking */
 554         trace_data = malloc(sizeof(u32) * num_frames);
 555         etb_read_ram(etb, trace_data, num_frames);
 556
 557         if (etm_ctx->trace_depth > 0)
 558         {
 559                 free(etm_ctx->trace_data);
 560         }
 561
 562         if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 563                 etm_ctx->trace_depth = num_frames * 3;
 564         else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 565                 etm_ctx->trace_depth = num_frames * 2;
 566         else
 567                 etm_ctx->trace_depth = num_frames;
 568
 569         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
 570
 571         for (i = 0, j = 0; i < num_frames; i++)
 572         {
 573                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 574                 {
 575                         /* trace word j */
 576                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 577                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
 578                         etm_ctx->trace_data[j].flags = 0;
 579                         if ((trace_data[i] & 0x80) >> 7)
 580                         {
 581                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 582                         }
 583                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 584                         {
 585                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 586                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 587                         }
 588
 589                         /* trace word j+1 */
 590                         etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
 591                         etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
 592                         etm_ctx->trace_data[j+1].flags = 0;
 593                         if ((trace_data[i] & 0x8000) >> 15)
 594                         {
 595                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
 596                         }
 597                         if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
 598                         {
 599                                 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
 600                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
 601                         }
 602
 603                         /* trace word j+2 */
 604                         etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
 605                         etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
 606                         etm_ctx->trace_data[j+2].flags = 0;
 607                         if ((trace_data[i] & 0x800000) >> 23)
 608                         {
 609                                 etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
 610                         }
 611                         if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
 612                         {
 613                                 etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
 614                                 etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
 615                         }
 616
 617                         j += 3;
 618                 }
 619                 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 620                 {
 621                         /* trace word j */
 622                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 623                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
 624                         etm_ctx->trace_data[j].flags = 0;
 625                         if ((trace_data[i] & 0x800) >> 11)
 626                         {
 627                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 628                         }
 629                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 630                         {
 631                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 632                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 633                         }
 634
 635                         /* trace word j+1 */
 636                         etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
 637                         etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
 638                         etm_ctx->trace_data[j+1].flags = 0;
 639                         if ((trace_data[i] & 0x800000) >> 23)
 640                         {
 641                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
 642                         }
 643                         if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
 644                         {
 645                                 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
 646                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
 647                         }
 648
 649                         j += 2;
 650                 }
 651                 else
 652                 {
 653                         /* trace word j */
 654                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 655                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
 656                         etm_ctx->trace_data[j].flags = 0;
 657                         if ((trace_data[i] & 0x80000) >> 19)
 658                         {
 659                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 660                         }
 661                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 662                         {
 663                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 664                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 665                         }
 666
 667                         j += 1;
 668                 }
 669         }
 670
 671         free(trace_data);
 672
 673         return ERROR_OK;
 674 }
 675
 676 static int etb_start_capture(etm_context_t *etm_ctx)
 677 {
 678         etb_t *etb = etm_ctx->capture_driver_priv;
 679         u32 etb_ctrl_value = 0x1;
 680         u32 trigger_count;
 681
 682         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
 683         {
 684                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
 685                 {
 686                         LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
 687                         return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 688                 }
 689                 etb_ctrl_value |= 0x2;
 690         }
 691
 692         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
 693                 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 694
 695         trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
 696
 697         etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
 698         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
 699         etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
 700         jtag_execute_queue();
 701
 702         /* we're starting a new trace, initialize capture status */
 703         etm_ctx->capture_status = TRACE_RUNNING;
 704
 705         return ERROR_OK;
 706 }
 707
 708 static int etb_stop_capture(etm_context_t *etm_ctx)
 709 {
 710         etb_t *etb = etm_ctx->capture_driver_priv;
 711         reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
 712
 713         etb_write_reg(etb_ctrl_reg, 0x0);
 714         jtag_execute_queue();
 715
 716         /* trace stopped, just clear running flag, but preserve others */
 717         etm_ctx->capture_status &= ~TRACE_RUNNING;
 718
 719         return ERROR_OK;
 720 }
 721
 722 etm_capture_driver_t etb_capture_driver =
 723 {
 724         .name = "etb",
 725         .register_commands = etb_register_commands,
 726         .init = etb_init,
 727         .status = etb_status,
 728         .start_capture = etb_start_capture,
 729         .stop_capture = etb_stop_capture,
 730         .read_trace = etb_read_trace,
 731 };