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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "armv4_5.h"
  25 #include "etb.h"
  26
  27
  28 static char* etb_reg_list[] =
  29 {
  30         "ETB_identification",
  31         "ETB_ram_depth",
  32         "ETB_ram_width",
  33         "ETB_status",
  34         "ETB_ram_data",
  35         "ETB_ram_read_pointer",
  36         "ETB_ram_write_pointer",
  37         "ETB_trigger_counter",
  38         "ETB_control",
  39 };
  40
  41 static int etb_reg_arch_type = -1;
  42
  43 static int etb_get_reg(struct reg *reg);
  44
  45 static int etb_set_instr(struct etb *etb, uint32_t new_instr)
  46 {
  47         struct jtag_tap *tap;
  48
  49         tap = etb->tap;
  50         if (tap == NULL)
  51                 return ERROR_FAIL;
  52
  53         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
  54         {
  55                 struct scan_field field;
  56
  57                 field.tap = tap;
  58                 field.num_bits = tap->ir_length;
  59                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  60                 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
  61
  62                 field.in_value = NULL;
  63
  64                 jtag_add_ir_scan(1, &field, jtag_get_end_state());
  65
  66                 free(field.out_value);
  67         }
  68
  69         return ERROR_OK;
  70 }
  71
  72 static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
  73 {
  74         if (etb->cur_scan_chain != new_scan_chain)
  75         {
  76                 struct scan_field field;
  77
  78                 field.tap = etb->tap;
  79                 field.num_bits = 5;
  80                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  81                 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
  82
  83                 field.in_value = NULL;
  84
  85                 /* select INTEST instruction */
  86                 etb_set_instr(etb, 0x2);
  87                 jtag_add_dr_scan(1, &field, jtag_get_end_state());
  88
  89                 etb->cur_scan_chain = new_scan_chain;
  90
  91                 free(field.out_value);
  92         }
  93
  94         return ERROR_OK;
  95 }
  96
  97 static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *);
  98 static int etb_set_reg_w_exec(struct reg *, uint8_t *);
  99
 100 static int etb_read_reg(struct reg *reg)
 101 {
 102         return etb_read_reg_w_check(reg, NULL, NULL);
 103 }
 104
 105 static int etb_get_reg(struct reg *reg)
 106 {
 107         int retval;
 108
 109         if ((retval = etb_read_reg(reg)) != ERROR_OK)
 110         {
 111                 LOG_ERROR("BUG: error scheduling ETB register read");
 112                 return retval;
 113         }
 114
 115         if ((retval = jtag_execute_queue()) != ERROR_OK)
 116         {
 117                 LOG_ERROR("ETB register read failed");
 118                 return retval;
 119         }
 120
 121         return ERROR_OK;
 122 }
 123
 124 struct reg_cache* etb_build_reg_cache(struct etb *etb)
 125 {
 126         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 127         struct reg *reg_list = NULL;
 128         struct etb_reg *arch_info = NULL;
 129         int num_regs = 9;
 130         int i;
 131
 132         /* register a register arch-type for etm registers only once */
 133         if (etb_reg_arch_type == -1)
 134                 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
 135
 136         /* the actual registers are kept in two arrays */
 137         reg_list = calloc(num_regs, sizeof(struct reg));
 138         arch_info = calloc(num_regs, sizeof(struct etb_reg));
 139
 140         /* fill in values for the reg cache */
 141         reg_cache->name = "etb registers";
 142         reg_cache->next = NULL;
 143         reg_cache->reg_list = reg_list;
 144         reg_cache->num_regs = num_regs;
 145
 146         /* set up registers */
 147         for (i = 0; i < num_regs; i++)
 148         {
 149                 reg_list[i].name = etb_reg_list[i];
 150                 reg_list[i].size = 32;
 151                 reg_list[i].dirty = 0;
 152                 reg_list[i].valid = 0;
 153                 reg_list[i].value = calloc(1, 4);
 154                 reg_list[i].arch_info = &arch_info[i];
 155                 reg_list[i].arch_type = etb_reg_arch_type;
 156                 reg_list[i].size = 32;
 157                 arch_info[i].addr = i;
 158                 arch_info[i].etb = etb;
 159         }
 160
 161         return reg_cache;
 162 }
 163
 164 static void etb_getbuf(jtag_callback_data_t arg)
 165 {
 166         uint8_t *in = (uint8_t *)arg;
 167
 168         *((uint32_t *)in) = buf_get_u32(in, 0, 32);
 169 }
 170
 171
 172 static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
 173 {
 174         struct scan_field fields[3];
 175         int i;
 176
 177         jtag_set_end_state(TAP_IDLE);
 178         etb_scann(etb, 0x0);
 179         etb_set_instr(etb, 0xc);
 180
 181         fields[0].tap = etb->tap;
 182         fields[0].num_bits = 32;
 183         fields[0].out_value = NULL;
 184         fields[0].in_value = NULL;
 185
 186         fields[1].tap = etb->tap;
 187         fields[1].num_bits = 7;
 188         fields[1].out_value = malloc(1);
 189         buf_set_u32(fields[1].out_value, 0, 7, 4);
 190         fields[1].in_value = NULL;
 191
 192         fields[2].tap = etb->tap;
 193         fields[2].num_bits = 1;
 194         fields[2].out_value = malloc(1);
 195         buf_set_u32(fields[2].out_value, 0, 1, 0);
 196         fields[2].in_value = NULL;
 197
 198         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 199
 200         for (i = 0; i < num_frames; i++)
 201         {
 202                 /* ensure nR/W reamins set to read */
 203                 buf_set_u32(fields[2].out_value, 0, 1, 0);
 204
 205                 /* address remains set to 0x4 (RAM data) until we read the last frame */
 206                 if (i < num_frames - 1)
 207                         buf_set_u32(fields[1].out_value, 0, 7, 4);
 208                 else
 209                         buf_set_u32(fields[1].out_value, 0, 7, 0);
 210
 211                 fields[0].in_value = (uint8_t *)(data + i);
 212                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 213
 214                 jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
 215         }
 216
 217         jtag_execute_queue();
 218
 219         free(fields[1].out_value);
 220         free(fields[2].out_value);
 221
 222         return ERROR_OK;
 223 }
 224
 225 static int etb_read_reg_w_check(struct reg *reg,
 226                 uint8_t* check_value, uint8_t* check_mask)
 227 {
 228         struct etb_reg *etb_reg = reg->arch_info;
 229         uint8_t reg_addr = etb_reg->addr & 0x7f;
 230         struct scan_field fields[3];
 231
 232         LOG_DEBUG("%i", (int)(etb_reg->addr));
 233
 234         jtag_set_end_state(TAP_IDLE);
 235         etb_scann(etb_reg->etb, 0x0);
 236         etb_set_instr(etb_reg->etb, 0xc);
 237
 238         fields[0].tap = etb_reg->etb->tap;
 239         fields[0].num_bits = 32;
 240         fields[0].out_value = reg->value;
 241         fields[0].in_value = NULL;
 242         fields[0].check_value = NULL;
 243         fields[0].check_mask = NULL;
 244
 245         fields[1].tap = etb_reg->etb->tap;
 246         fields[1].num_bits = 7;
 247         fields[1].out_value = malloc(1);
 248         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 249         fields[1].in_value = NULL;
 250         fields[1].check_value = NULL;
 251         fields[1].check_mask = NULL;
 252
 253         fields[2].tap = etb_reg->etb->tap;
 254         fields[2].num_bits = 1;
 255         fields[2].out_value = malloc(1);
 256         buf_set_u32(fields[2].out_value, 0, 1, 0);
 257         fields[2].in_value = NULL;
 258         fields[2].check_value = NULL;
 259         fields[2].check_mask = NULL;
 260
 261         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 262
 263         /* read the identification register in the second run, to make sure we
 264          * don't read the ETB data register twice, skipping every second entry
 265          */
 266         buf_set_u32(fields[1].out_value, 0, 7, 0x0);
 267         fields[0].in_value = reg->value;
 268         fields[0].check_value = check_value;
 269         fields[0].check_mask = check_mask;
 270
 271         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 272
 273         free(fields[1].out_value);
 274         free(fields[2].out_value);
 275
 276         return ERROR_OK;
 277 }
 278
 279 static int etb_write_reg(struct reg *, uint32_t);
 280
 281 static int etb_set_reg(struct reg *reg, uint32_t value)
 282 {
 283         int retval;
 284
 285         if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
 286         {
 287                 LOG_ERROR("BUG: error scheduling ETB register write");
 288                 return retval;
 289         }
 290
 291         buf_set_u32(reg->value, 0, reg->size, value);
 292         reg->valid = 1;
 293         reg->dirty = 0;
 294
 295         return ERROR_OK;
 296 }
 297
 298 static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 299 {
 300         int retval;
 301
 302         etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 303
 304         if ((retval = jtag_execute_queue()) != ERROR_OK)
 305         {
 306                 LOG_ERROR("ETB: register write failed");
 307                 return retval;
 308         }
 309         return ERROR_OK;
 310 }
 311
 312 static int etb_write_reg(struct reg *reg, uint32_t value)
 313 {
 314         struct etb_reg *etb_reg = reg->arch_info;
 315         uint8_t reg_addr = etb_reg->addr & 0x7f;
 316         struct scan_field fields[3];
 317
 318         LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
 319
 320         jtag_set_end_state(TAP_IDLE);
 321         etb_scann(etb_reg->etb, 0x0);
 322         etb_set_instr(etb_reg->etb, 0xc);
 323
 324         fields[0].tap = etb_reg->etb->tap;
 325         fields[0].num_bits = 32;
 326         fields[0].out_value = malloc(4);
 327         buf_set_u32(fields[0].out_value, 0, 32, value);
 328         fields[0].in_value = NULL;
 329
 330         fields[1].tap = etb_reg->etb->tap;
 331         fields[1].num_bits = 7;
 332         fields[1].out_value = malloc(1);
 333         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 334         fields[1].in_value = NULL;
 335
 336         fields[2].tap = etb_reg->etb->tap;
 337         fields[2].num_bits = 1;
 338         fields[2].out_value = malloc(1);
 339         buf_set_u32(fields[2].out_value, 0, 1, 1);
 340
 341         fields[2].in_value = NULL;
 342
 343         free(fields[0].out_value);
 344         free(fields[1].out_value);
 345         free(fields[2].out_value);
 346
 347         return ERROR_OK;
 348 }
 349
 350 COMMAND_HANDLER(handle_etb_config_command)
 351 {
 352         struct target *target;
 353         struct jtag_tap *tap;
 354         struct arm *arm;
 355
 356         if (argc != 2)
 357         {
 358                 return ERROR_COMMAND_SYNTAX_ERROR;
 359         }
 360
 361         target = get_target(args[0]);
 362
 363         if (!target)
 364         {
 365                 LOG_ERROR("ETB: target '%s' not defined", args[0]);
 366                 return ERROR_FAIL;
 367         }
 368
 369         arm = target_to_arm(target);
 370         if (!is_arm(arm))
 371         {
 372                 command_print(cmd_ctx, "ETB: '%s' isn't an ARM", args[0]);
 373                 return ERROR_FAIL;
 374         }
 375
 376         tap = jtag_tap_by_string(args[1]);
 377         if (tap == NULL)
 378         {
 379                 command_print(cmd_ctx, "ETB: TAP %s does not exist", args[1]);
 380                 return ERROR_FAIL;
 381         }
 382
 383         if (arm->etm)
 384         {
 385                 struct etb *etb = malloc(sizeof(struct etb));
 386
 387                 arm->etm->capture_driver_priv = etb;
 388
 389                 etb->tap  = tap;
 390                 etb->cur_scan_chain = 0xffffffff;
 391                 etb->reg_cache = NULL;
 392                 etb->ram_width = 0;
 393                 etb->ram_depth = 0;
 394         }
 395         else
 396         {
 397                 LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
 398                 return ERROR_FAIL;
 399         }
 400
 401         return ERROR_OK;
 402 }
 403
 404 static int etb_register_commands(struct command_context *cmd_ctx)
 405 {
 406         struct command *etb_cmd = register_command(cmd_ctx, NULL, "etb",
 407                         NULL, COMMAND_ANY, "Embedded Trace Buffer");
 408
 409         register_command(cmd_ctx, etb_cmd, "config",
 410                         handle_etb_config_command, COMMAND_CONFIG,
 411                         NULL);
 412
 413         return ERROR_OK;
 414 }
 415
 416 static int etb_init(struct etm_context *etm_ctx)
 417 {
 418         struct etb *etb = etm_ctx->capture_driver_priv;
 419
 420         etb->etm_ctx = etm_ctx;
 421
 422         /* identify ETB RAM depth and width */
 423         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
 424         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
 425         jtag_execute_queue();
 426
 427         etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
 428         etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
 429
 430         return ERROR_OK;
 431 }
 432
 433 static trace_status_t etb_status(struct etm_context *etm_ctx)
 434 {
 435         struct etb *etb = etm_ctx->capture_driver_priv;
 436         struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
 437         struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
 438         trace_status_t retval = 0;
 439         int etb_timeout = 100;
 440
 441         etb->etm_ctx = etm_ctx;
 442
 443         /* read control and status registers */
 444         etb_read_reg(control);
 445         etb_read_reg(status);
 446         jtag_execute_queue();
 447
 448         /* See if it's (still) active */
 449         retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE;
 450
 451         /* check Full bit to identify wraparound/overflow */
 452         if (buf_get_u32(status->value, 0, 1) == 1)
 453                 retval |= TRACE_OVERFLOWED;
 454
 455         /* check Triggered bit to identify trigger condition */
 456         if (buf_get_u32(status->value, 1, 1) == 1)
 457                 retval |= TRACE_TRIGGERED;
 458
 459         /* check AcqComp to see if trigger counter dropped to zero */
 460         if (buf_get_u32(status->value, 2, 1) == 1) {
 461                 /* wait for DFEmpty */
 462                 while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0)
 463                         etb_get_reg(status);
 464
 465                 if (etb_timeout == 0)
 466                         LOG_ERROR("ETB:  DFEmpty won't go high, status 0x%02x",
 467                                 (unsigned) buf_get_u32(status->value, 0, 4));
 468
 469                 if (!(etm_ctx->capture_status & TRACE_TRIGGERED))
 470                         LOG_WARNING("ETB: trace complete without triggering?");
 471
 472                 retval |= TRACE_COMPLETED;
 473         }
 474
 475         /* NOTE: using a trigger is optional; and at least ETB11 has a mode
 476          * where it can ignore the trigger counter.
 477          */
 478
 479         /* update recorded state */
 480         etm_ctx->capture_status = retval;
 481
 482         return retval;
 483 }
 484
 485 static int etb_read_trace(struct etm_context *etm_ctx)
 486 {
 487         struct etb *etb = etm_ctx->capture_driver_priv;
 488         int first_frame = 0;
 489         int num_frames = etb->ram_depth;
 490         uint32_t *trace_data = NULL;
 491         int i, j;
 492
 493         etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
 494         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
 495         jtag_execute_queue();
 496
 497         /* check if we overflowed, and adjust first frame of the trace accordingly
 498          * if we didn't overflow, read only up to the frame that would be written next,
 499          * i.e. don't read invalid entries
 500          */
 501         if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
 502         {
 503                 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 504         }
 505         else
 506         {
 507                 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 508         }
 509
 510         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
 511
 512         /* read data into temporary array for unpacking */
 513         trace_data = malloc(sizeof(uint32_t) * num_frames);
 514         etb_read_ram(etb, trace_data, num_frames);
 515
 516         if (etm_ctx->trace_depth > 0)
 517         {
 518                 free(etm_ctx->trace_data);
 519         }
 520
 521         if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 522                 etm_ctx->trace_depth = num_frames * 3;
 523         else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 524                 etm_ctx->trace_depth = num_frames * 2;
 525         else
 526                 etm_ctx->trace_depth = num_frames;
 527
 528         etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
 529
 530         for (i = 0, j = 0; i < num_frames; i++)
 531         {
 532                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 533                 {
 534                         /* trace word j */
 535                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 536                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
 537                         etm_ctx->trace_data[j].flags = 0;
 538                         if ((trace_data[i] & 0x80) >> 7)
 539                         {
 540                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 541                         }
 542                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 543                         {
 544                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 545                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 546                         }
 547
 548                         /* trace word j + 1 */
 549                         etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
 550                         etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
 551                         etm_ctx->trace_data[j + 1].flags = 0;
 552                         if ((trace_data[i] & 0x8000) >> 15)
 553                         {
 554                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 555                         }
 556                         if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 557                         {
 558                                 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
 559                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 560                         }
 561
 562                         /* trace word j + 2 */
 563                         etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
 564                         etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
 565                         etm_ctx->trace_data[j + 2].flags = 0;
 566                         if ((trace_data[i] & 0x800000) >> 23)
 567                         {
 568                                 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
 569                         }
 570                         if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
 571                         {
 572                                 etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
 573                                 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
 574                         }
 575
 576                         j += 3;
 577                 }
 578                 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 579                 {
 580                         /* trace word j */
 581                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 582                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
 583                         etm_ctx->trace_data[j].flags = 0;
 584                         if ((trace_data[i] & 0x800) >> 11)
 585                         {
 586                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 587                         }
 588                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 589                         {
 590                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 591                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 592                         }
 593
 594                         /* trace word j + 1 */
 595                         etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
 596                         etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
 597                         etm_ctx->trace_data[j + 1].flags = 0;
 598                         if ((trace_data[i] & 0x800000) >> 23)
 599                         {
 600                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 601                         }
 602                         if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 603                         {
 604                                 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
 605                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 606                         }
 607
 608                         j += 2;
 609                 }
 610                 else
 611                 {
 612                         /* trace word j */
 613                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 614                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
 615                         etm_ctx->trace_data[j].flags = 0;
 616                         if ((trace_data[i] & 0x80000) >> 19)
 617                         {
 618                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 619                         }
 620                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 621                         {
 622                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 623                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 624                         }
 625
 626                         j += 1;
 627                 }
 628         }
 629
 630         free(trace_data);
 631
 632         return ERROR_OK;
 633 }
 634
 635 static int etb_start_capture(struct etm_context *etm_ctx)
 636 {
 637         struct etb *etb = etm_ctx->capture_driver_priv;
 638         uint32_t etb_ctrl_value = 0x1;
 639         uint32_t trigger_count;
 640
 641         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
 642         {
 643                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
 644                 {
 645                         LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
 646                         return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 647                 }
 648                 etb_ctrl_value |= 0x2;
 649         }
 650
 651         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
 652                 LOG_ERROR("ETB: can't run in multiplexed mode");
 653                 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 654         }
 655
 656         trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
 657
 658         etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
 659         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
 660         etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
 661         jtag_execute_queue();
 662
 663         /* we're starting a new trace, initialize capture status */
 664         etm_ctx->capture_status = TRACE_RUNNING;
 665
 666         return ERROR_OK;
 667 }
 668
 669 static int etb_stop_capture(struct etm_context *etm_ctx)
 670 {
 671         struct etb *etb = etm_ctx->capture_driver_priv;
 672         struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
 673
 674         etb_write_reg(etb_ctrl_reg, 0x0);
 675         jtag_execute_queue();
 676
 677         /* trace stopped, just clear running flag, but preserve others */
 678         etm_ctx->capture_status &= ~TRACE_RUNNING;
 679
 680         return ERROR_OK;
 681 }
 682
 683 struct etm_capture_driver etb_capture_driver =
 684 {
 685         .name = "etb",
 686         .register_commands = etb_register_commands,
 687         .init = etb_init,
 688         .status = etb_status,
 689         .start_capture = etb_start_capture,
 690         .stop_capture = etb_stop_capture,
 691         .read_trace = etb_read_trace,
 692 };