git.gag.com Git - fw/openocd/blob - src/target/etb.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm7_9_common.h"
  25 #include "etb.h"
  26
  27
  28 static char* etb_reg_list[] =
  29 {
  30         "ETB_identification",
  31         "ETB_ram_depth",
  32         "ETB_ram_width",
  33         "ETB_status",
  34         "ETB_ram_data",
  35         "ETB_ram_read_pointer",
  36         "ETB_ram_write_pointer",
  37         "ETB_trigger_counter",
  38         "ETB_control",
  39 };
  40
  41 static int etb_reg_arch_type = -1;
  42
  43 static int etb_get_reg(reg_t *reg);
  44
  45 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46
  47 static int etb_set_instr(etb_t *etb, uint32_t new_instr)
  48 {
  49         jtag_tap_t *tap;
  50
  51         tap = etb->tap;
  52         if (tap == NULL)
  53                 return ERROR_FAIL;
  54
  55         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
  56         {
  57                 scan_field_t field;
  58
  59                 field.tap = tap;
  60                 field.num_bits = tap->ir_length;
  61                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  62                 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
  63
  64                 field.in_value = NULL;
  65
  66                 jtag_add_ir_scan(1, &field, jtag_get_end_state());
  67
  68                 free(field.out_value);
  69         }
  70
  71         return ERROR_OK;
  72 }
  73
  74 static int etb_scann(etb_t *etb, uint32_t new_scan_chain)
  75 {
  76         if (etb->cur_scan_chain != new_scan_chain)
  77         {
  78                 scan_field_t field;
  79
  80                 field.tap = etb->tap;
  81                 field.num_bits = 5;
  82                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  83                 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
  84
  85                 field.in_value = NULL;
  86
  87                 /* select INTEST instruction */
  88                 etb_set_instr(etb, 0x2);
  89                 jtag_add_dr_scan(1, &field, jtag_get_end_state());
  90
  91                 etb->cur_scan_chain = new_scan_chain;
  92
  93                 free(field.out_value);
  94         }
  95
  96         return ERROR_OK;
  97 }
  98
  99 reg_cache_t* etb_build_reg_cache(etb_t *etb)
 100 {
 101         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 102         reg_t *reg_list = NULL;
 103         etb_reg_t *arch_info = NULL;
 104         int num_regs = 9;
 105         int i;
 106
 107         /* register a register arch-type for etm registers only once */
 108         if (etb_reg_arch_type == -1)
 109                 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
 110
 111         /* the actual registers are kept in two arrays */
 112         reg_list = calloc(num_regs, sizeof(reg_t));
 113         arch_info = calloc(num_regs, sizeof(etb_reg_t));
 114
 115         /* fill in values for the reg cache */
 116         reg_cache->name = "etb registers";
 117         reg_cache->next = NULL;
 118         reg_cache->reg_list = reg_list;
 119         reg_cache->num_regs = num_regs;
 120
 121         /* set up registers */
 122         for (i = 0; i < num_regs; i++)
 123         {
 124                 reg_list[i].name = etb_reg_list[i];
 125                 reg_list[i].size = 32;
 126                 reg_list[i].dirty = 0;
 127                 reg_list[i].valid = 0;
 128                 reg_list[i].bitfield_desc = NULL;
 129                 reg_list[i].num_bitfields = 0;
 130                 reg_list[i].value = calloc(1, 4);
 131                 reg_list[i].arch_info = &arch_info[i];
 132                 reg_list[i].arch_type = etb_reg_arch_type;
 133                 reg_list[i].size = 32;
 134                 arch_info[i].addr = i;
 135                 arch_info[i].etb = etb;
 136         }
 137
 138         return reg_cache;
 139 }
 140
 141 static int etb_get_reg(reg_t *reg)
 142 {
 143         int retval;
 144
 145         if ((retval = etb_read_reg(reg)) != ERROR_OK)
 146         {
 147                 LOG_ERROR("BUG: error scheduling etm register read");
 148                 return retval;
 149         }
 150
 151         if ((retval = jtag_execute_queue()) != ERROR_OK)
 152         {
 153                 LOG_ERROR("register read failed");
 154                 return retval;
 155         }
 156
 157         return ERROR_OK;
 158 }
 159
 160
 161 static void etb_getbuf(jtag_callback_data_t arg)
 162 {
 163   uint8_t *in = (uint8_t *)arg;
 164         *((uint32_t *)in) = buf_get_u32(in, 0, 32);
 165 }
 166
 167
 168 static int etb_read_ram(etb_t *etb, uint32_t *data, int num_frames)
 169 {
 170         scan_field_t fields[3];
 171         int i;
 172
 173         jtag_set_end_state(TAP_IDLE);
 174         etb_scann(etb, 0x0);
 175         etb_set_instr(etb, 0xc);
 176
 177         fields[0].tap = etb->tap;
 178         fields[0].num_bits = 32;
 179         fields[0].out_value = NULL;
 180         fields[0].in_value = NULL;
 181
 182         fields[1].tap = etb->tap;
 183         fields[1].num_bits = 7;
 184         fields[1].out_value = malloc(1);
 185         buf_set_u32(fields[1].out_value, 0, 7, 4);
 186         fields[1].in_value = NULL;
 187
 188         fields[2].tap = etb->tap;
 189         fields[2].num_bits = 1;
 190         fields[2].out_value = malloc(1);
 191         buf_set_u32(fields[2].out_value, 0, 1, 0);
 192         fields[2].in_value = NULL;
 193
 194         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 195
 196         for (i = 0; i < num_frames; i++)
 197         {
 198                 /* ensure nR/W reamins set to read */
 199                 buf_set_u32(fields[2].out_value, 0, 1, 0);
 200
 201                 /* address remains set to 0x4 (RAM data) until we read the last frame */
 202                 if (i < num_frames - 1)
 203                         buf_set_u32(fields[1].out_value, 0, 7, 4);
 204                 else
 205                         buf_set_u32(fields[1].out_value, 0, 7, 0);
 206
 207                 fields[0].in_value = (uint8_t *)(data + i);
 208                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 209
 210                 jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
 211         }
 212
 213         jtag_execute_queue();
 214
 215         free(fields[1].out_value);
 216         free(fields[2].out_value);
 217
 218         return ERROR_OK;
 219 }
 220
 221 int etb_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask)
 222 {
 223         etb_reg_t *etb_reg = reg->arch_info;
 224         uint8_t reg_addr = etb_reg->addr & 0x7f;
 225         scan_field_t fields[3];
 226
 227         LOG_DEBUG("%i", (int)(etb_reg->addr));
 228
 229         jtag_set_end_state(TAP_IDLE);
 230         etb_scann(etb_reg->etb, 0x0);
 231         etb_set_instr(etb_reg->etb, 0xc);
 232
 233         fields[0].tap = etb_reg->etb->tap;
 234         fields[0].num_bits = 32;
 235         fields[0].out_value = reg->value;
 236         fields[0].in_value = NULL;
 237         fields[0].check_value = NULL;
 238         fields[0].check_mask = NULL;
 239
 240         fields[1].tap = etb_reg->etb->tap;
 241         fields[1].num_bits = 7;
 242         fields[1].out_value = malloc(1);
 243         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 244         fields[1].in_value = NULL;
 245         fields[1].check_value = NULL;
 246         fields[1].check_mask = NULL;
 247
 248         fields[2].tap = etb_reg->etb->tap;
 249         fields[2].num_bits = 1;
 250         fields[2].out_value = malloc(1);
 251         buf_set_u32(fields[2].out_value, 0, 1, 0);
 252         fields[2].in_value = NULL;
 253         fields[2].check_value = NULL;
 254         fields[2].check_mask = NULL;
 255
 256         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 257
 258         /* read the identification register in the second run, to make sure we
 259          * don't read the ETB data register twice, skipping every second entry
 260          */
 261         buf_set_u32(fields[1].out_value, 0, 7, 0x0);
 262         fields[0].in_value = reg->value;
 263         fields[0].check_value = check_value;
 264         fields[0].check_mask = check_mask;
 265
 266         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 267
 268         free(fields[1].out_value);
 269         free(fields[2].out_value);
 270
 271         return ERROR_OK;
 272 }
 273
 274 int etb_read_reg(reg_t *reg)
 275 {
 276         return etb_read_reg_w_check(reg, NULL, NULL);
 277 }
 278
 279 int etb_set_reg(reg_t *reg, uint32_t value)
 280 {
 281         int retval;
 282
 283         if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
 284         {
 285                 LOG_ERROR("BUG: error scheduling etm register write");
 286                 return retval;
 287         }
 288
 289         buf_set_u32(reg->value, 0, reg->size, value);
 290         reg->valid = 1;
 291         reg->dirty = 0;
 292
 293         return ERROR_OK;
 294 }
 295
 296 int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf)
 297 {
 298         int retval;
 299
 300         etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 301
 302         if ((retval = jtag_execute_queue()) != ERROR_OK)
 303         {
 304                 LOG_ERROR("register write failed");
 305                 return retval;
 306         }
 307         return ERROR_OK;
 308 }
 309
 310 int etb_write_reg(reg_t *reg, uint32_t value)
 311 {
 312         etb_reg_t *etb_reg = reg->arch_info;
 313         uint8_t reg_addr = etb_reg->addr & 0x7f;
 314         scan_field_t fields[3];
 315
 316         LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
 317
 318         jtag_set_end_state(TAP_IDLE);
 319         etb_scann(etb_reg->etb, 0x0);
 320         etb_set_instr(etb_reg->etb, 0xc);
 321
 322         fields[0].tap = etb_reg->etb->tap;
 323         fields[0].num_bits = 32;
 324         fields[0].out_value = malloc(4);
 325         buf_set_u32(fields[0].out_value, 0, 32, value);
 326         fields[0].in_value = NULL;
 327
 328         fields[1].tap = etb_reg->etb->tap;
 329         fields[1].num_bits = 7;
 330         fields[1].out_value = malloc(1);
 331         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 332         fields[1].in_value = NULL;
 333
 334         fields[2].tap = etb_reg->etb->tap;
 335         fields[2].num_bits = 1;
 336         fields[2].out_value = malloc(1);
 337         buf_set_u32(fields[2].out_value, 0, 1, 1);
 338
 339         fields[2].in_value = NULL;
 340
 341         free(fields[0].out_value);
 342         free(fields[1].out_value);
 343         free(fields[2].out_value);
 344
 345         return ERROR_OK;
 346 }
 347
 348 int etb_store_reg(reg_t *reg)
 349 {
 350         return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 351 }
 352
 353 static int etb_register_commands(struct command_context_s *cmd_ctx)
 354 {
 355         command_t *etb_cmd;
 356
 357         etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
 358
 359         register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
 360
 361         return ERROR_OK;
 362 }
 363
 364 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 365 {
 366         target_t *target;
 367         jtag_tap_t *tap;
 368         armv4_5_common_t *armv4_5;
 369         arm7_9_common_t *arm7_9;
 370
 371         if (argc != 2)
 372         {
 373                 return ERROR_COMMAND_SYNTAX_ERROR;
 374         }
 375
 376         target = get_target(args[0]);
 377
 378         if (!target)
 379         {
 380                 LOG_ERROR("target '%s' not defined", args[0]);
 381                 return ERROR_FAIL;
 382         }
 383
 384         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 385         {
 386                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 387                 return ERROR_FAIL;
 388         }
 389
 390         tap = jtag_tap_by_string( args[1] );
 391         if (tap == NULL)
 392         {
 393                 command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
 394                 return ERROR_FAIL;
 395         }
 396
 397         if (arm7_9->etm_ctx)
 398         {
 399                 etb_t *etb = malloc(sizeof(etb_t));
 400
 401                 arm7_9->etm_ctx->capture_driver_priv = etb;
 402
 403                 etb->tap  = tap;
 404                 etb->cur_scan_chain = 0xffffffff;
 405                 etb->reg_cache = NULL;
 406                 etb->ram_width = 0;
 407                 etb->ram_depth = 0;
 408         }
 409         else
 410         {
 411                 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
 412                 return ERROR_FAIL;
 413         }
 414
 415         return ERROR_OK;
 416 }
 417
 418 static int etb_init(etm_context_t *etm_ctx)
 419 {
 420         etb_t *etb = etm_ctx->capture_driver_priv;
 421
 422         etb->etm_ctx = etm_ctx;
 423
 424         /* identify ETB RAM depth and width */
 425         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
 426         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
 427         jtag_execute_queue();
 428
 429         etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
 430         etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
 431
 432         return ERROR_OK;
 433 }
 434
 435 static trace_status_t etb_status(etm_context_t *etm_ctx)
 436 {
 437         etb_t *etb = etm_ctx->capture_driver_priv;
 438
 439         etb->etm_ctx = etm_ctx;
 440
 441         /* if tracing is currently idle, return this information */
 442         if (etm_ctx->capture_status == TRACE_IDLE)
 443         {
 444                 return etm_ctx->capture_status;
 445         }
 446         else if (etm_ctx->capture_status & TRACE_RUNNING)
 447         {
 448                 reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
 449                 int etb_timeout = 100;
 450
 451                 /* trace is running, check the ETB status flags */
 452                 etb_get_reg(etb_status_reg);
 453
 454                 /* check Full bit to identify an overflow */
 455                 if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
 456                         etm_ctx->capture_status |= TRACE_OVERFLOWED;
 457
 458                 /* check Triggered bit to identify trigger condition */
 459                 if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
 460                         etm_ctx->capture_status |= TRACE_TRIGGERED;
 461
 462                 /* check AcqComp to identify trace completion */
 463                 if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
 464                 {
 465                         while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
 466                         {
 467                                 /* wait for data formatter idle */
 468                                 etb_get_reg(etb_status_reg);
 469                         }
 470
 471                         if (etb_timeout == 0)
 472                         {
 473                                 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%" PRIx32 "",
 474                                         buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
 475                         }
 476
 477                         if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
 478                         {
 479                                 LOG_ERROR("trace completed, but no trigger condition detected");
 480                         }
 481
 482                         etm_ctx->capture_status &= ~TRACE_RUNNING;
 483                         etm_ctx->capture_status |= TRACE_COMPLETED;
 484                 }
 485         }
 486
 487         return etm_ctx->capture_status;
 488 }
 489
 490 static int etb_read_trace(etm_context_t *etm_ctx)
 491 {
 492         etb_t *etb = etm_ctx->capture_driver_priv;
 493         int first_frame = 0;
 494         int num_frames = etb->ram_depth;
 495         uint32_t *trace_data = NULL;
 496         int i, j;
 497
 498         etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
 499         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
 500         jtag_execute_queue();
 501
 502         /* check if we overflowed, and adjust first frame of the trace accordingly
 503          * if we didn't overflow, read only up to the frame that would be written next,
 504          * i.e. don't read invalid entries
 505          */
 506         if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
 507         {
 508                 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 509         }
 510         else
 511         {
 512                 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 513         }
 514
 515         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
 516
 517         /* read data into temporary array for unpacking */
 518         trace_data = malloc(sizeof(uint32_t) * num_frames);
 519         etb_read_ram(etb, trace_data, num_frames);
 520
 521         if (etm_ctx->trace_depth > 0)
 522         {
 523                 free(etm_ctx->trace_data);
 524         }
 525
 526         if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 527                 etm_ctx->trace_depth = num_frames * 3;
 528         else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 529                 etm_ctx->trace_depth = num_frames * 2;
 530         else
 531                 etm_ctx->trace_depth = num_frames;
 532
 533         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
 534
 535         for (i = 0, j = 0; i < num_frames; i++)
 536         {
 537                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 538                 {
 539                         /* trace word j */
 540                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 541                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
 542                         etm_ctx->trace_data[j].flags = 0;
 543                         if ((trace_data[i] & 0x80) >> 7)
 544                         {
 545                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 546                         }
 547                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 548                         {
 549                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 550                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 551                         }
 552
 553                         /* trace word j + 1 */
 554                         etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
 555                         etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
 556                         etm_ctx->trace_data[j + 1].flags = 0;
 557                         if ((trace_data[i] & 0x8000) >> 15)
 558                         {
 559                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 560                         }
 561                         if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 562                         {
 563                                 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
 564                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 565                         }
 566
 567                         /* trace word j + 2 */
 568                         etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
 569                         etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
 570                         etm_ctx->trace_data[j + 2].flags = 0;
 571                         if ((trace_data[i] & 0x800000) >> 23)
 572                         {
 573                                 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
 574                         }
 575                         if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
 576                         {
 577                                 etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
 578                                 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
 579                         }
 580
 581                         j += 3;
 582                 }
 583                 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 584                 {
 585                         /* trace word j */
 586                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 587                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
 588                         etm_ctx->trace_data[j].flags = 0;
 589                         if ((trace_data[i] & 0x800) >> 11)
 590                         {
 591                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 592                         }
 593                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 594                         {
 595                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 596                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 597                         }
 598
 599                         /* trace word j + 1 */
 600                         etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
 601                         etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
 602                         etm_ctx->trace_data[j + 1].flags = 0;
 603                         if ((trace_data[i] & 0x800000) >> 23)
 604                         {
 605                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 606                         }
 607                         if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 608                         {
 609                                 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
 610                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 611                         }
 612
 613                         j += 2;
 614                 }
 615                 else
 616                 {
 617                         /* trace word j */
 618                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 619                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
 620                         etm_ctx->trace_data[j].flags = 0;
 621                         if ((trace_data[i] & 0x80000) >> 19)
 622                         {
 623                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 624                         }
 625                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 626                         {
 627                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 628                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 629                         }
 630
 631                         j += 1;
 632                 }
 633         }
 634
 635         free(trace_data);
 636
 637         return ERROR_OK;
 638 }
 639
 640 static int etb_start_capture(etm_context_t *etm_ctx)
 641 {
 642         etb_t *etb = etm_ctx->capture_driver_priv;
 643         uint32_t etb_ctrl_value = 0x1;
 644         uint32_t trigger_count;
 645
 646         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
 647         {
 648                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
 649                 {
 650                         LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
 651                         return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 652                 }
 653                 etb_ctrl_value |= 0x2;
 654         }
 655
 656         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
 657                 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 658
 659         trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
 660
 661         etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
 662         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
 663         etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
 664         jtag_execute_queue();
 665
 666         /* we're starting a new trace, initialize capture status */
 667         etm_ctx->capture_status = TRACE_RUNNING;
 668
 669         return ERROR_OK;
 670 }
 671
 672 static int etb_stop_capture(etm_context_t *etm_ctx)
 673 {
 674         etb_t *etb = etm_ctx->capture_driver_priv;
 675         reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
 676
 677         etb_write_reg(etb_ctrl_reg, 0x0);
 678         jtag_execute_queue();
 679
 680         /* trace stopped, just clear running flag, but preserve others */
 681         etm_ctx->capture_status &= ~TRACE_RUNNING;
 682
 683         return ERROR_OK;
 684 }
 685
 686 etm_capture_driver_t etb_capture_driver =
 687 {
 688         .name = "etb",
 689         .register_commands = etb_register_commands,
 690         .init = etb_init,
 691         .status = etb_status,
 692         .start_capture = etb_start_capture,
 693         .stop_capture = etb_stop_capture,
 694         .read_trace = etb_read_trace,
 695 };