git.gag.com Git - fw/openocd/blob - src/target/etb.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "armv4_5.h"
  25 #include "etb.h"
  26 #include "register.h"
  27
  28
  29 static char* etb_reg_list[] =
  30 {
  31         "ETB_identification",
  32         "ETB_ram_depth",
  33         "ETB_ram_width",
  34         "ETB_status",
  35         "ETB_ram_data",
  36         "ETB_ram_read_pointer",
  37         "ETB_ram_write_pointer",
  38         "ETB_trigger_counter",
  39         "ETB_control",
  40 };
  41
  42 static int etb_reg_arch_type = -1;
  43
  44 static int etb_get_reg(struct reg *reg);
  45
  46 static int etb_set_instr(struct etb *etb, uint32_t new_instr)
  47 {
  48         struct jtag_tap *tap;
  49
  50         tap = etb->tap;
  51         if (tap == NULL)
  52                 return ERROR_FAIL;
  53
  54         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
  55         {
  56                 struct scan_field field;
  57
  58                 field.tap = tap;
  59                 field.num_bits = tap->ir_length;
  60                 field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
  61                 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
  62
  63                 field.in_value = NULL;
  64
  65                 jtag_add_ir_scan(1, &field, jtag_get_end_state());
  66
  67                 free(field.out_value);
  68         }
  69
  70         return ERROR_OK;
  71 }
  72
  73 static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
  74 {
  75         if (etb->cur_scan_chain != new_scan_chain)
  76         {
  77                 struct scan_field field;
  78
  79                 field.tap = etb->tap;
  80                 field.num_bits = 5;
  81                 field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
  82                 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
  83
  84                 field.in_value = NULL;
  85
  86                 /* select INTEST instruction */
  87                 etb_set_instr(etb, 0x2);
  88                 jtag_add_dr_scan(1, &field, jtag_get_end_state());
  89
  90                 etb->cur_scan_chain = new_scan_chain;
  91
  92                 free(field.out_value);
  93         }
  94
  95         return ERROR_OK;
  96 }
  97
  98 static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *);
  99 static int etb_set_reg_w_exec(struct reg *, uint8_t *);
 100
 101 static int etb_read_reg(struct reg *reg)
 102 {
 103         return etb_read_reg_w_check(reg, NULL, NULL);
 104 }
 105
 106 static int etb_get_reg(struct reg *reg)
 107 {
 108         int retval;
 109
 110         if ((retval = etb_read_reg(reg)) != ERROR_OK)
 111         {
 112                 LOG_ERROR("BUG: error scheduling ETB register read");
 113                 return retval;
 114         }
 115
 116         if ((retval = jtag_execute_queue()) != ERROR_OK)
 117         {
 118                 LOG_ERROR("ETB register read failed");
 119                 return retval;
 120         }
 121
 122         return ERROR_OK;
 123 }
 124
 125 struct reg_cache* etb_build_reg_cache(struct etb *etb)
 126 {
 127         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 128         struct reg *reg_list = NULL;
 129         struct etb_reg *arch_info = NULL;
 130         int num_regs = 9;
 131         int i;
 132
 133         /* register a register arch-type for etm registers only once */
 134         if (etb_reg_arch_type == -1)
 135                 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
 136
 137         /* the actual registers are kept in two arrays */
 138         reg_list = calloc(num_regs, sizeof(struct reg));
 139         arch_info = calloc(num_regs, sizeof(struct etb_reg));
 140
 141         /* fill in values for the reg cache */
 142         reg_cache->name = "etb registers";
 143         reg_cache->next = NULL;
 144         reg_cache->reg_list = reg_list;
 145         reg_cache->num_regs = num_regs;
 146
 147         /* set up registers */
 148         for (i = 0; i < num_regs; i++)
 149         {
 150                 reg_list[i].name = etb_reg_list[i];
 151                 reg_list[i].size = 32;
 152                 reg_list[i].dirty = 0;
 153                 reg_list[i].valid = 0;
 154                 reg_list[i].value = calloc(1, 4);
 155                 reg_list[i].arch_info = &arch_info[i];
 156                 reg_list[i].arch_type = etb_reg_arch_type;
 157                 reg_list[i].size = 32;
 158                 arch_info[i].addr = i;
 159                 arch_info[i].etb = etb;
 160         }
 161
 162         return reg_cache;
 163 }
 164
 165 static void etb_getbuf(jtag_callback_data_t arg)
 166 {
 167         uint8_t *in = (uint8_t *)arg;
 168
 169         *((uint32_t *)in) = buf_get_u32(in, 0, 32);
 170 }
 171
 172
 173 static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
 174 {
 175         struct scan_field fields[3];
 176         int i;
 177
 178         jtag_set_end_state(TAP_IDLE);
 179         etb_scann(etb, 0x0);
 180         etb_set_instr(etb, 0xc);
 181
 182         fields[0].tap = etb->tap;
 183         fields[0].num_bits = 32;
 184         fields[0].out_value = NULL;
 185         fields[0].in_value = NULL;
 186
 187         fields[1].tap = etb->tap;
 188         fields[1].num_bits = 7;
 189         fields[1].out_value = malloc(1);
 190         buf_set_u32(fields[1].out_value, 0, 7, 4);
 191         fields[1].in_value = NULL;
 192
 193         fields[2].tap = etb->tap;
 194         fields[2].num_bits = 1;
 195         fields[2].out_value = malloc(1);
 196         buf_set_u32(fields[2].out_value, 0, 1, 0);
 197         fields[2].in_value = NULL;
 198
 199         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 200
 201         for (i = 0; i < num_frames; i++)
 202         {
 203                 /* ensure nR/W reamins set to read */
 204                 buf_set_u32(fields[2].out_value, 0, 1, 0);
 205
 206                 /* address remains set to 0x4 (RAM data) until we read the last frame */
 207                 if (i < num_frames - 1)
 208                         buf_set_u32(fields[1].out_value, 0, 7, 4);
 209                 else
 210                         buf_set_u32(fields[1].out_value, 0, 7, 0);
 211
 212                 fields[0].in_value = (uint8_t *)(data + i);
 213                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 214
 215                 jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
 216         }
 217
 218         jtag_execute_queue();
 219
 220         free(fields[1].out_value);
 221         free(fields[2].out_value);
 222
 223         return ERROR_OK;
 224 }
 225
 226 static int etb_read_reg_w_check(struct reg *reg,
 227                 uint8_t* check_value, uint8_t* check_mask)
 228 {
 229         struct etb_reg *etb_reg = reg->arch_info;
 230         uint8_t reg_addr = etb_reg->addr & 0x7f;
 231         struct scan_field fields[3];
 232
 233         LOG_DEBUG("%i", (int)(etb_reg->addr));
 234
 235         jtag_set_end_state(TAP_IDLE);
 236         etb_scann(etb_reg->etb, 0x0);
 237         etb_set_instr(etb_reg->etb, 0xc);
 238
 239         fields[0].tap = etb_reg->etb->tap;
 240         fields[0].num_bits = 32;
 241         fields[0].out_value = reg->value;
 242         fields[0].in_value = NULL;
 243         fields[0].check_value = NULL;
 244         fields[0].check_mask = NULL;
 245
 246         fields[1].tap = etb_reg->etb->tap;
 247         fields[1].num_bits = 7;
 248         fields[1].out_value = malloc(1);
 249         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 250         fields[1].in_value = NULL;
 251         fields[1].check_value = NULL;
 252         fields[1].check_mask = NULL;
 253
 254         fields[2].tap = etb_reg->etb->tap;
 255         fields[2].num_bits = 1;
 256         fields[2].out_value = malloc(1);
 257         buf_set_u32(fields[2].out_value, 0, 1, 0);
 258         fields[2].in_value = NULL;
 259         fields[2].check_value = NULL;
 260         fields[2].check_mask = NULL;
 261
 262         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 263
 264         /* read the identification register in the second run, to make sure we
 265          * don't read the ETB data register twice, skipping every second entry
 266          */
 267         buf_set_u32(fields[1].out_value, 0, 7, 0x0);
 268         fields[0].in_value = reg->value;
 269         fields[0].check_value = check_value;
 270         fields[0].check_mask = check_mask;
 271
 272         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 273
 274         free(fields[1].out_value);
 275         free(fields[2].out_value);
 276
 277         return ERROR_OK;
 278 }
 279
 280 static int etb_write_reg(struct reg *, uint32_t);
 281
 282 static int etb_set_reg(struct reg *reg, uint32_t value)
 283 {
 284         int retval;
 285
 286         if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
 287         {
 288                 LOG_ERROR("BUG: error scheduling ETB register write");
 289                 return retval;
 290         }
 291
 292         buf_set_u32(reg->value, 0, reg->size, value);
 293         reg->valid = 1;
 294         reg->dirty = 0;
 295
 296         return ERROR_OK;
 297 }
 298
 299 static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 300 {
 301         int retval;
 302
 303         etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 304
 305         if ((retval = jtag_execute_queue()) != ERROR_OK)
 306         {
 307                 LOG_ERROR("ETB: register write failed");
 308                 return retval;
 309         }
 310         return ERROR_OK;
 311 }
 312
 313 static int etb_write_reg(struct reg *reg, uint32_t value)
 314 {
 315         struct etb_reg *etb_reg = reg->arch_info;
 316         uint8_t reg_addr = etb_reg->addr & 0x7f;
 317         struct scan_field fields[3];
 318
 319         LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
 320
 321         jtag_set_end_state(TAP_IDLE);
 322         etb_scann(etb_reg->etb, 0x0);
 323         etb_set_instr(etb_reg->etb, 0xc);
 324
 325         fields[0].tap = etb_reg->etb->tap;
 326         fields[0].num_bits = 32;
 327         fields[0].out_value = malloc(4);
 328         buf_set_u32(fields[0].out_value, 0, 32, value);
 329         fields[0].in_value = NULL;
 330
 331         fields[1].tap = etb_reg->etb->tap;
 332         fields[1].num_bits = 7;
 333         fields[1].out_value = malloc(1);
 334         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 335         fields[1].in_value = NULL;
 336
 337         fields[2].tap = etb_reg->etb->tap;
 338         fields[2].num_bits = 1;
 339         fields[2].out_value = malloc(1);
 340         buf_set_u32(fields[2].out_value, 0, 1, 1);
 341
 342         fields[2].in_value = NULL;
 343
 344         free(fields[0].out_value);
 345         free(fields[1].out_value);
 346         free(fields[2].out_value);
 347
 348         return ERROR_OK;
 349 }
 350
 351 COMMAND_HANDLER(handle_etb_config_command)
 352 {
 353         struct target *target;
 354         struct jtag_tap *tap;
 355         struct arm *arm;
 356
 357         if (argc != 2)
 358         {
 359                 return ERROR_COMMAND_SYNTAX_ERROR;
 360         }
 361
 362         target = get_target(args[0]);
 363
 364         if (!target)
 365         {
 366                 LOG_ERROR("ETB: target '%s' not defined", args[0]);
 367                 return ERROR_FAIL;
 368         }
 369
 370         arm = target_to_arm(target);
 371         if (!is_arm(arm))
 372         {
 373                 command_print(cmd_ctx, "ETB: '%s' isn't an ARM", args[0]);
 374                 return ERROR_FAIL;
 375         }
 376
 377         tap = jtag_tap_by_string(args[1]);
 378         if (tap == NULL)
 379         {
 380                 command_print(cmd_ctx, "ETB: TAP %s does not exist", args[1]);
 381                 return ERROR_FAIL;
 382         }
 383
 384         if (arm->etm)
 385         {
 386                 struct etb *etb = malloc(sizeof(struct etb));
 387
 388                 arm->etm->capture_driver_priv = etb;
 389
 390                 etb->tap  = tap;
 391                 etb->cur_scan_chain = 0xffffffff;
 392                 etb->reg_cache = NULL;
 393                 etb->ram_width = 0;
 394                 etb->ram_depth = 0;
 395         }
 396         else
 397         {
 398                 LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
 399                 return ERROR_FAIL;
 400         }
 401
 402         return ERROR_OK;
 403 }
 404
 405 static int etb_register_commands(struct command_context *cmd_ctx)
 406 {
 407         struct command *etb_cmd = register_command(cmd_ctx, NULL, "etb",
 408                         NULL, COMMAND_ANY, "Embedded Trace Buffer");
 409
 410         register_command(cmd_ctx, etb_cmd, "config",
 411                         handle_etb_config_command, COMMAND_CONFIG,
 412                         NULL);
 413
 414         return ERROR_OK;
 415 }
 416
 417 static int etb_init(struct etm_context *etm_ctx)
 418 {
 419         struct etb *etb = etm_ctx->capture_driver_priv;
 420
 421         etb->etm_ctx = etm_ctx;
 422
 423         /* identify ETB RAM depth and width */
 424         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
 425         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
 426         jtag_execute_queue();
 427
 428         etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
 429         etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
 430
 431         return ERROR_OK;
 432 }
 433
 434 static trace_status_t etb_status(struct etm_context *etm_ctx)
 435 {
 436         struct etb *etb = etm_ctx->capture_driver_priv;
 437         struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
 438         struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
 439         trace_status_t retval = 0;
 440         int etb_timeout = 100;
 441
 442         etb->etm_ctx = etm_ctx;
 443
 444         /* read control and status registers */
 445         etb_read_reg(control);
 446         etb_read_reg(status);
 447         jtag_execute_queue();
 448
 449         /* See if it's (still) active */
 450         retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE;
 451
 452         /* check Full bit to identify wraparound/overflow */
 453         if (buf_get_u32(status->value, 0, 1) == 1)
 454                 retval |= TRACE_OVERFLOWED;
 455
 456         /* check Triggered bit to identify trigger condition */
 457         if (buf_get_u32(status->value, 1, 1) == 1)
 458                 retval |= TRACE_TRIGGERED;
 459
 460         /* check AcqComp to see if trigger counter dropped to zero */
 461         if (buf_get_u32(status->value, 2, 1) == 1) {
 462                 /* wait for DFEmpty */
 463                 while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0)
 464                         etb_get_reg(status);
 465
 466                 if (etb_timeout == 0)
 467                         LOG_ERROR("ETB:  DFEmpty won't go high, status 0x%02x",
 468                                 (unsigned) buf_get_u32(status->value, 0, 4));
 469
 470                 if (!(etm_ctx->capture_status & TRACE_TRIGGERED))
 471                         LOG_WARNING("ETB: trace complete without triggering?");
 472
 473                 retval |= TRACE_COMPLETED;
 474         }
 475
 476         /* NOTE: using a trigger is optional; and at least ETB11 has a mode
 477          * where it can ignore the trigger counter.
 478          */
 479
 480         /* update recorded state */
 481         etm_ctx->capture_status = retval;
 482
 483         return retval;
 484 }
 485
 486 static int etb_read_trace(struct etm_context *etm_ctx)
 487 {
 488         struct etb *etb = etm_ctx->capture_driver_priv;
 489         int first_frame = 0;
 490         int num_frames = etb->ram_depth;
 491         uint32_t *trace_data = NULL;
 492         int i, j;
 493
 494         etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
 495         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
 496         jtag_execute_queue();
 497
 498         /* check if we overflowed, and adjust first frame of the trace accordingly
 499          * if we didn't overflow, read only up to the frame that would be written next,
 500          * i.e. don't read invalid entries
 501          */
 502         if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
 503         {
 504                 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 505         }
 506         else
 507         {
 508                 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 509         }
 510
 511         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
 512
 513         /* read data into temporary array for unpacking */
 514         trace_data = malloc(sizeof(uint32_t) * num_frames);
 515         etb_read_ram(etb, trace_data, num_frames);
 516
 517         if (etm_ctx->trace_depth > 0)
 518         {
 519                 free(etm_ctx->trace_data);
 520         }
 521
 522         if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 523                 etm_ctx->trace_depth = num_frames * 3;
 524         else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 525                 etm_ctx->trace_depth = num_frames * 2;
 526         else
 527                 etm_ctx->trace_depth = num_frames;
 528
 529         etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
 530
 531         for (i = 0, j = 0; i < num_frames; i++)
 532         {
 533                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 534                 {
 535                         /* trace word j */
 536                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 537                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
 538                         etm_ctx->trace_data[j].flags = 0;
 539                         if ((trace_data[i] & 0x80) >> 7)
 540                         {
 541                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 542                         }
 543                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 544                         {
 545                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 546                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 547                         }
 548
 549                         /* trace word j + 1 */
 550                         etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
 551                         etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
 552                         etm_ctx->trace_data[j + 1].flags = 0;
 553                         if ((trace_data[i] & 0x8000) >> 15)
 554                         {
 555                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 556                         }
 557                         if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 558                         {
 559                                 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
 560                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 561                         }
 562
 563                         /* trace word j + 2 */
 564                         etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
 565                         etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
 566                         etm_ctx->trace_data[j + 2].flags = 0;
 567                         if ((trace_data[i] & 0x800000) >> 23)
 568                         {
 569                                 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
 570                         }
 571                         if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
 572                         {
 573                                 etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
 574                                 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
 575                         }
 576
 577                         j += 3;
 578                 }
 579                 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 580                 {
 581                         /* trace word j */
 582                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 583                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
 584                         etm_ctx->trace_data[j].flags = 0;
 585                         if ((trace_data[i] & 0x800) >> 11)
 586                         {
 587                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 588                         }
 589                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 590                         {
 591                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 592                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 593                         }
 594
 595                         /* trace word j + 1 */
 596                         etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
 597                         etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
 598                         etm_ctx->trace_data[j + 1].flags = 0;
 599                         if ((trace_data[i] & 0x800000) >> 23)
 600                         {
 601                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 602                         }
 603                         if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 604                         {
 605                                 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
 606                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 607                         }
 608
 609                         j += 2;
 610                 }
 611                 else
 612                 {
 613                         /* trace word j */
 614                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 615                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
 616                         etm_ctx->trace_data[j].flags = 0;
 617                         if ((trace_data[i] & 0x80000) >> 19)
 618                         {
 619                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 620                         }
 621                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 622                         {
 623                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 624                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 625                         }
 626
 627                         j += 1;
 628                 }
 629         }
 630
 631         free(trace_data);
 632
 633         return ERROR_OK;
 634 }
 635
 636 static int etb_start_capture(struct etm_context *etm_ctx)
 637 {
 638         struct etb *etb = etm_ctx->capture_driver_priv;
 639         uint32_t etb_ctrl_value = 0x1;
 640         uint32_t trigger_count;
 641
 642         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
 643         {
 644                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
 645                 {
 646                         LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
 647                         return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 648                 }
 649                 etb_ctrl_value |= 0x2;
 650         }
 651
 652         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
 653                 LOG_ERROR("ETB: can't run in multiplexed mode");
 654                 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 655         }
 656
 657         trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
 658
 659         etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
 660         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
 661         etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
 662         jtag_execute_queue();
 663
 664         /* we're starting a new trace, initialize capture status */
 665         etm_ctx->capture_status = TRACE_RUNNING;
 666
 667         return ERROR_OK;
 668 }
 669
 670 static int etb_stop_capture(struct etm_context *etm_ctx)
 671 {
 672         struct etb *etb = etm_ctx->capture_driver_priv;
 673         struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
 674
 675         etb_write_reg(etb_ctrl_reg, 0x0);
 676         jtag_execute_queue();
 677
 678         /* trace stopped, just clear running flag, but preserve others */
 679         etm_ctx->capture_status &= ~TRACE_RUNNING;
 680
 681         return ERROR_OK;
 682 }
 683
 684 struct etm_capture_driver etb_capture_driver =
 685 {
 686         .name = "etb",
 687         .register_commands = etb_register_commands,
 688         .init = etb_init,
 689         .status = etb_status,
 690         .start_capture = etb_start_capture,
 691         .stop_capture = etb_stop_capture,
 692         .read_trace = etb_read_trace,
 693 };