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   1 /***************************************************************************
   2  *   Copyright (C) 2018 by Square, Inc.                                    *
   3  *   Steven Stallion <stallion@squareup.com>                               *
   4  *   James Zhao <hjz@squareup.com>                                         *
   5  *                                                                         *
   6  *   This program is free software; you can redistribute it and/or modify  *
   7  *   it under the terms of the GNU General Public License as published by  *
   8  *   the Free Software Foundation; either version 2 of the License, or     *
   9  *   (at your option) any later version.                                   *
  10  *                                                                         *
  11  *   This program is distributed in the hope that it will be useful,       *
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  14  *   GNU General Public License for more details.                          *
  15  *                                                                         *
  16  *   You should have received a copy of the GNU General Public License     *
  17  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  18  ***************************************************************************/
  19
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <helper/binarybuffer.h>
  25 #include <helper/command.h>
  26 #include <helper/log.h>
  27 #include <helper/time_support.h>
  28 #include <helper/types.h>
  29 #include <jtag/interface.h>
  30 #include <target/breakpoints.h>
  31 #include <target/register.h>
  32 #include <target/target.h>
  33 #include <target/target_type.h>
  34
  35 #include "esirisc.h"
  36
  37 #define RESET_TIMEOUT                   5000    /* 5s */
  38 #define STEP_TIMEOUT                    1000    /* 1s */
  39
  40 /*
  41  * eSi-RISC targets support a configurable number of interrupts;
  42  * up to 32 interrupts are supported.
  43  */
  44 static const char * const esirisc_exception_strings[] = {
  45         [EID_RESET]                                     = "Reset",
  46         [EID_HARDWARE_FAILURE]          = "HardwareFailure",
  47         [EID_NMI]                                       = "NMI",
  48         [EID_INST_BREAKPOINT]           = "InstBreakpoint",
  49         [EID_DATA_BREAKPOINT]           = "DataBreakpoint",
  50         [EID_UNSUPPORTED]                       = "Unsupported",
  51         [EID_PRIVILEGE_VIOLATION]       = "PrivilegeViolation",
  52         [EID_INST_BUS_ERROR]            = "InstBusError",
  53         [EID_DATA_BUS_ERROR]            = "DataBusError",
  54         [EID_ALIGNMENT_ERROR]           = "AlignmentError",
  55         [EID_ARITHMETIC_ERROR]          = "ArithmeticError",
  56         [EID_SYSTEM_CALL]                       = "SystemCall",
  57         [EID_MEMORY_MANAGEMENT]         = "MemoryManagement",
  58         [EID_UNRECOVERABLE]                     = "Unrecoverable",
  59         [EID_INTERRUPTn+0]                      = "Interrupt0",
  60         [EID_INTERRUPTn+1]                      = "Interrupt1",
  61         [EID_INTERRUPTn+2]                      = "Interrupt2",
  62         [EID_INTERRUPTn+3]                      = "Interrupt3",
  63         [EID_INTERRUPTn+4]                      = "Interrupt4",
  64         [EID_INTERRUPTn+5]                      = "Interrupt5",
  65         [EID_INTERRUPTn+6]                      = "Interrupt6",
  66         [EID_INTERRUPTn+7]                      = "Interrupt7",
  67         [EID_INTERRUPTn+8]                      = "Interrupt8",
  68         [EID_INTERRUPTn+9]                      = "Interrupt9",
  69         [EID_INTERRUPTn+10]                     = "Interrupt10",
  70         [EID_INTERRUPTn+11]                     = "Interrupt11",
  71         [EID_INTERRUPTn+12]                     = "Interrupt12",
  72         [EID_INTERRUPTn+13]                     = "Interrupt13",
  73         [EID_INTERRUPTn+14]                     = "Interrupt14",
  74         [EID_INTERRUPTn+15]                     = "Interrupt15",
  75         [EID_INTERRUPTn+16]                     = "Interrupt16",
  76         [EID_INTERRUPTn+17]                     = "Interrupt17",
  77         [EID_INTERRUPTn+18]                     = "Interrupt18",
  78         [EID_INTERRUPTn+19]                     = "Interrupt19",
  79         [EID_INTERRUPTn+20]                     = "Interrupt20",
  80         [EID_INTERRUPTn+21]                     = "Interrupt21",
  81         [EID_INTERRUPTn+22]                     = "Interrupt22",
  82         [EID_INTERRUPTn+23]                     = "Interrupt23",
  83         [EID_INTERRUPTn+24]                     = "Interrupt24",
  84         [EID_INTERRUPTn+25]                     = "Interrupt25",
  85         [EID_INTERRUPTn+26]                     = "Interrupt26",
  86         [EID_INTERRUPTn+27]                     = "Interrupt27",
  87         [EID_INTERRUPTn+28]                     = "Interrupt28",
  88         [EID_INTERRUPTn+29]                     = "Interrupt29",
  89         [EID_INTERRUPTn+30]                     = "Interrupt30",
  90         [EID_INTERRUPTn+31]                     = "Interrupt31",
  91 };
  92
  93 /*
  94  * eSi-RISC targets support a configurable number of general purpose
  95  * registers; 8, 16, and 32 registers are supported.
  96  */
  97 static const struct {
  98         enum esirisc_reg_num number;
  99         const char *name;
 100         enum reg_type type;
 101         const char *group;
 102 } esirisc_regs[] = {
 103         { ESIRISC_SP, "sp", REG_TYPE_DATA_PTR, "general" },
 104         { ESIRISC_RA, "ra", REG_TYPE_INT, "general" },
 105         { ESIRISC_R2, "r2", REG_TYPE_INT, "general" },
 106         { ESIRISC_R3, "r3", REG_TYPE_INT, "general" },
 107         { ESIRISC_R4, "r4", REG_TYPE_INT, "general" },
 108         { ESIRISC_R5, "r5", REG_TYPE_INT, "general" },
 109         { ESIRISC_R6, "r6", REG_TYPE_INT, "general" },
 110         { ESIRISC_R7, "r7", REG_TYPE_INT, "general" },
 111         { ESIRISC_R8, "r8", REG_TYPE_INT, "general" },
 112         { ESIRISC_R9, "r9", REG_TYPE_INT, "general" },
 113         { ESIRISC_R10, "r10", REG_TYPE_INT, "general" },
 114         { ESIRISC_R11, "r11", REG_TYPE_INT, "general" },
 115         { ESIRISC_R12, "r12", REG_TYPE_INT, "general" },
 116         { ESIRISC_R13, "r13", REG_TYPE_INT, "general" },
 117         { ESIRISC_R14, "r14", REG_TYPE_INT, "general" },
 118         { ESIRISC_R15, "r15", REG_TYPE_INT, "general" },
 119         { ESIRISC_R16, "r16", REG_TYPE_INT, "general" },
 120         { ESIRISC_R17, "r17", REG_TYPE_INT, "general" },
 121         { ESIRISC_R18, "r18", REG_TYPE_INT, "general" },
 122         { ESIRISC_R19, "r19", REG_TYPE_INT, "general" },
 123         { ESIRISC_R20, "r20", REG_TYPE_INT, "general" },
 124         { ESIRISC_R21, "r21", REG_TYPE_INT, "general" },
 125         { ESIRISC_R22, "r22", REG_TYPE_INT, "general" },
 126         { ESIRISC_R23, "r23", REG_TYPE_INT, "general" },
 127         { ESIRISC_R24, "r24", REG_TYPE_INT, "general" },
 128         { ESIRISC_R25, "r25", REG_TYPE_INT, "general" },
 129         { ESIRISC_R26, "r26", REG_TYPE_INT, "general" },
 130         { ESIRISC_R27, "r27", REG_TYPE_INT, "general" },
 131         { ESIRISC_R28, "r28", REG_TYPE_INT, "general" },
 132         { ESIRISC_R29, "r29", REG_TYPE_INT, "general" },
 133         { ESIRISC_R30, "r30", REG_TYPE_INT, "general" },
 134         { ESIRISC_R31, "r31", REG_TYPE_INT, "general" },
 135 };
 136
 137 /*
 138  * Control and Status Registers (CSRs) are largely defined as belonging
 139  * to the system register group. The exception to this rule are the PC
 140  * and CAS registers, which belong to the general group. While debug is
 141  * active, EPC, ECAS, and ETC must be used to read and write the PC,
 142  * CAS, and TC CSRs, respectively.
 143  */
 144 static const struct {
 145         enum esirisc_reg_num number;
 146         uint8_t bank;
 147         uint8_t csr;
 148         const char *name;
 149         enum reg_type type;
 150         const char *group;
 151 } esirisc_csrs[] = {
 152         { ESIRISC_PC, CSR_THREAD, CSR_THREAD_EPC, "PC", REG_TYPE_CODE_PTR, "general" }, /*  PC -> EPC  */
 153         { ESIRISC_CAS, CSR_THREAD, CSR_THREAD_ECAS, "CAS", REG_TYPE_INT, "general" },   /* CAS -> ECAS */
 154         { ESIRISC_TC, CSR_THREAD, CSR_THREAD_ETC, "TC", REG_TYPE_INT, "system" },               /*  TC -> ETC  */
 155         { ESIRISC_ETA, CSR_THREAD, CSR_THREAD_ETA, "ETA", REG_TYPE_INT, "system" },
 156         { ESIRISC_ETC, CSR_THREAD, CSR_THREAD_ETC, "ETC", REG_TYPE_INT, "system" },
 157         { ESIRISC_EPC, CSR_THREAD, CSR_THREAD_EPC, "EPC", REG_TYPE_CODE_PTR, "system" },
 158         { ESIRISC_ECAS, CSR_THREAD, CSR_THREAD_ECAS, "ECAS", REG_TYPE_INT, "system" },
 159         { ESIRISC_EID, CSR_THREAD, CSR_THREAD_EID, "EID", REG_TYPE_INT, "system" },
 160         { ESIRISC_ED, CSR_THREAD, CSR_THREAD_ED, "ED", REG_TYPE_INT, "system" },
 161         { ESIRISC_IP, CSR_INTERRUPT, CSR_INTERRUPT_IP, "IP", REG_TYPE_INT, "system"},
 162         { ESIRISC_IM, CSR_INTERRUPT, CSR_INTERRUPT_IM, "IM", REG_TYPE_INT, "system"},
 163         { ESIRISC_IS, CSR_INTERRUPT, CSR_INTERRUPT_IS, "IS", REG_TYPE_INT, "system"},
 164         { ESIRISC_IT, CSR_INTERRUPT, CSR_INTERRUPT_IT, "IT", REG_TYPE_INT, "system"},
 165 };
 166
 167 static int esirisc_disable_interrupts(struct target *target)
 168 {
 169         struct esirisc_common *esirisc = target_to_esirisc(target);
 170         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 171         uint32_t etc;
 172         int retval;
 173
 174         LOG_DEBUG("-");
 175
 176         retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, &etc);
 177         if (retval != ERROR_OK) {
 178                 LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target));
 179                 return retval;
 180         }
 181
 182         etc &= ~(1<<0);         /* TC.I */
 183
 184         retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, etc);
 185         if (retval != ERROR_OK) {
 186                 LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target));
 187                 return retval;
 188         }
 189
 190         return ERROR_OK;
 191 }
 192
 193 #if 0
 194 static int esirisc_enable_interrupts(struct target *target)
 195 {
 196         struct esirisc_common *esirisc = target_to_esirisc(target);
 197         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 198         uint32_t etc;
 199         int retval;
 200
 201         LOG_DEBUG("-");
 202
 203         retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, &etc);
 204         if (retval != ERROR_OK) {
 205                 LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target));
 206                 return retval;
 207         }
 208
 209         etc |= (1<<0);          /* TC.I */
 210
 211         retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, etc);
 212         if (retval != ERROR_OK) {
 213                 LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target));
 214                 return retval;
 215         }
 216
 217         return ERROR_OK;
 218 }
 219 #endif
 220
 221 static int esirisc_save_interrupts(struct target *target)
 222 {
 223         struct esirisc_common *esirisc = target_to_esirisc(target);
 224         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 225
 226         LOG_DEBUG("-");
 227
 228         int retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC,
 229                         &esirisc->etc_save);
 230         if (retval != ERROR_OK) {
 231                 LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target));
 232                 return retval;
 233         }
 234
 235         return ERROR_OK;
 236 }
 237
 238 static int esirisc_restore_interrupts(struct target *target)
 239 {
 240         struct esirisc_common *esirisc = target_to_esirisc(target);
 241         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 242
 243         LOG_DEBUG("-");
 244
 245         int retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC,
 246                         esirisc->etc_save);
 247         if (retval != ERROR_OK) {
 248                 LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target));
 249                 return retval;
 250         }
 251
 252         return ERROR_OK;
 253 }
 254
 255 #if 0
 256 static int esirisc_save_hwdc(struct target *target)
 257 {
 258         struct esirisc_common *esirisc = target_to_esirisc(target);
 259         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 260
 261         LOG_DEBUG("-");
 262
 263         int retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_HWDC,
 264                         &esirisc->hwdc_save);
 265         if (retval != ERROR_OK) {
 266                 LOG_ERROR("%s: failed to read Thread CSR: HWDC", target_name(target));
 267                 return retval;
 268         }
 269
 270         return ERROR_OK;
 271 }
 272 #endif
 273
 274 static int esirisc_restore_hwdc(struct target *target)
 275 {
 276         struct esirisc_common *esirisc = target_to_esirisc(target);
 277         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 278
 279         LOG_DEBUG("-");
 280
 281         int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_HWDC,
 282                         esirisc->hwdc_save);
 283         if (retval != ERROR_OK) {
 284                 LOG_ERROR("%s: failed to write Debug CSR: HWDC", target_name(target));
 285                 return retval;
 286         }
 287
 288         return ERROR_OK;
 289 }
 290
 291 static int esirisc_save_context(struct target *target)
 292 {
 293         struct esirisc_common *esirisc = target_to_esirisc(target);
 294
 295         LOG_DEBUG("-");
 296
 297         for (unsigned i = 0; i < esirisc->reg_cache->num_regs; ++i) {
 298                 struct reg *reg = esirisc->reg_cache->reg_list + i;
 299                 struct esirisc_reg *reg_info = reg->arch_info;
 300
 301                 if (reg->exist && !reg->valid)
 302                         reg_info->read(reg);
 303         }
 304
 305         return ERROR_OK;
 306 }
 307
 308 static int esirisc_restore_context(struct target *target)
 309 {
 310         struct esirisc_common *esirisc = target_to_esirisc(target);
 311
 312         LOG_DEBUG("-");
 313
 314         for (unsigned i = 0; i < esirisc->reg_cache->num_regs; ++i) {
 315                 struct reg *reg = esirisc->reg_cache->reg_list + i;
 316                 struct esirisc_reg *reg_info = reg->arch_info;
 317
 318                 if (reg->exist && reg->dirty)
 319                         reg_info->write(reg);
 320         }
 321
 322         return ERROR_OK;
 323 }
 324
 325 static int esirisc_flush_caches(struct target *target)
 326 {
 327         struct esirisc_common *esirisc = target_to_esirisc(target);
 328         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 329
 330         LOG_DEBUG("-");
 331
 332         if (target->state != TARGET_HALTED)
 333                 return ERROR_TARGET_NOT_HALTED;
 334
 335         int retval = esirisc_jtag_flush_caches(jtag_info);
 336         if (retval != ERROR_OK) {
 337                 LOG_ERROR("%s: failed to flush caches", target_name(target));
 338                 return retval;
 339         }
 340
 341         return ERROR_OK;
 342 }
 343
 344 static int esirisc_wait_debug_active(struct esirisc_common *esirisc, int ms)
 345 {
 346         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 347         int64_t t;
 348
 349         LOG_DEBUG("-");
 350
 351         t = timeval_ms();
 352         for (;;) {
 353                 int retval = esirisc_jtag_enable_debug(jtag_info);
 354                 if (retval == ERROR_OK && esirisc_jtag_is_debug_active(jtag_info))
 355                         return retval;
 356
 357                 if ((timeval_ms() - t) > ms)
 358                         return ERROR_TARGET_TIMEOUT;
 359
 360                 alive_sleep(100);
 361         }
 362 }
 363
 364 static int esirisc_read_memory(struct target *target, target_addr_t address,
 365                 uint32_t size, uint32_t count, uint8_t *buffer)
 366 {
 367         struct esirisc_common *esirisc = target_to_esirisc(target);
 368         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 369         int retval;
 370
 371         LOG_DEBUG("-");
 372
 373         int num_bits = 8 * size;
 374         for (uint32_t i = 0; i < count; ++i) {
 375                 union esirisc_memory value;
 376                 void *value_p;
 377
 378                 switch (size) {
 379                         case sizeof(value.word):
 380                                 value_p = &value.word;
 381                                 retval = esirisc_jtag_read_word(jtag_info, address, value_p);
 382                                 break;
 383
 384                         case sizeof(value.hword):
 385                                 value_p = &value.hword;
 386                                 retval = esirisc_jtag_read_hword(jtag_info, address, value_p);
 387                                 break;
 388
 389                         case sizeof(value.byte):
 390                                 value_p = &value.byte;
 391                                 retval = esirisc_jtag_read_byte(jtag_info, address, value_p);
 392                                 break;
 393
 394                         default:
 395                                 LOG_ERROR("%s: unsupported size: %" PRIu32, target_name(target), size);
 396                                 return ERROR_FAIL;
 397                 }
 398
 399                 if (retval != ERROR_OK) {
 400                         LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR, target_name(target),
 401                                         address);
 402                         return retval;
 403                 }
 404
 405                 buf_cpy(value_p, buffer, num_bits);
 406                 address += size;
 407                 buffer += size;
 408         }
 409
 410         return ERROR_OK;
 411 }
 412
 413 static int esirisc_write_memory(struct target *target, target_addr_t address,
 414                 uint32_t size, uint32_t count, const uint8_t *buffer)
 415 {
 416         struct esirisc_common *esirisc = target_to_esirisc(target);
 417         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 418         int retval;
 419
 420         LOG_DEBUG("-");
 421
 422         int num_bits = 8 * size;
 423         for (uint32_t i = 0; i < count; ++i) {
 424                 union esirisc_memory value;
 425
 426                 switch (size) {
 427                         case sizeof(value.word):
 428                                 value.word = buf_get_u32(buffer, 0, num_bits);
 429                                 retval = esirisc_jtag_write_word(jtag_info, address, value.word);
 430                                 break;
 431
 432                         case sizeof(value.hword):
 433                                 value.hword = buf_get_u32(buffer, 0, num_bits);
 434                                 retval = esirisc_jtag_write_hword(jtag_info, address, value.hword);
 435                                 break;
 436
 437                         case sizeof(value.byte):
 438                                 value.byte = buf_get_u32(buffer, 0, num_bits);
 439                                 retval = esirisc_jtag_write_byte(jtag_info, address, value.byte);
 440                                 break;
 441
 442                         default:
 443                                 LOG_ERROR("%s: unsupported size: %" PRIu32, target_name(target), size);
 444                                 return ERROR_FAIL;
 445                 }
 446
 447                 if (retval != ERROR_OK) {
 448                         LOG_ERROR("%s: failed to write address: 0x%" TARGET_PRIxADDR, target_name(target),
 449                                         address);
 450                         return retval;
 451                 }
 452
 453                 address += size;
 454                 buffer += size;
 455         }
 456
 457         return ERROR_OK;
 458 }
 459
 460 static int esirisc_checksum_memory(struct target *target, target_addr_t address,
 461                 uint32_t count, uint32_t *checksum)
 462 {
 463         return ERROR_FAIL;      /* not supported */
 464 }
 465
 466 static int esirisc_next_breakpoint(struct target *target)
 467 {
 468         struct esirisc_common *esirisc = target_to_esirisc(target);
 469         struct breakpoint **breakpoints_p = esirisc->breakpoints_p;
 470         struct breakpoint **breakpoints_e = breakpoints_p + esirisc->num_breakpoints;
 471
 472         LOG_DEBUG("-");
 473
 474         for (int bp_index = 0; breakpoints_p < breakpoints_e; ++breakpoints_p, ++bp_index)
 475                 if (*breakpoints_p == NULL)
 476                         return bp_index;
 477
 478         return -1;
 479 }
 480
 481 static int esirisc_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 482 {
 483         struct esirisc_common *esirisc = target_to_esirisc(target);
 484         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 485         int bp_index;
 486         uint32_t ibc;
 487         int retval;
 488
 489         LOG_DEBUG("-");
 490
 491         /*
 492          * The default linker scripts provided by the eSi-RISC toolchain do
 493          * not specify attributes on memory regions, which results in
 494          * incorrect application of software breakpoints by GDB. Targets
 495          * must be configured with `gdb_breakpoint_override hard` as
 496          * software breakpoints are not supported.
 497          */
 498         if (breakpoint->type != BKPT_HARD)
 499                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 500
 501         bp_index = esirisc_next_breakpoint(target);
 502         if (bp_index < 0) {
 503                 LOG_ERROR("%s: out of hardware breakpoints", target_name(target));
 504                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 505         }
 506
 507         breakpoint->set = bp_index + 1;
 508         esirisc->breakpoints_p[bp_index] = breakpoint;
 509
 510         /* specify instruction breakpoint address */
 511         retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBAn + bp_index,
 512                         breakpoint->address);
 513         if (retval != ERROR_OK) {
 514                 LOG_ERROR("%s: failed to write Debug CSR: IBA", target_name(target));
 515                 return retval;
 516         }
 517
 518         /* enable instruction breakpoint */
 519         retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, &ibc);
 520         if (retval != ERROR_OK) {
 521                 LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target));
 522                 return retval;
 523         }
 524
 525         ibc |= (1 << bp_index);         /* IBC.In */
 526
 527         retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, ibc);
 528         if (retval != ERROR_OK) {
 529                 LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target));
 530                 return retval;
 531         }
 532
 533         return ERROR_OK;
 534 }
 535
 536 static int esirisc_add_breakpoints(struct target *target)
 537 {
 538         struct breakpoint *breakpoint = target->breakpoints;
 539
 540         LOG_DEBUG("-");
 541
 542         while (breakpoint != NULL) {
 543                 if (breakpoint->set == 0)
 544                         esirisc_add_breakpoint(target, breakpoint);
 545
 546                 breakpoint = breakpoint->next;
 547         }
 548
 549         return ERROR_OK;
 550 }
 551
 552 static int esirisc_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
 553 {
 554         struct esirisc_common *esirisc = target_to_esirisc(target);
 555         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 556         int bp_index = breakpoint->set - 1;
 557         uint32_t ibc;
 558         int retval;
 559
 560         LOG_DEBUG("-");
 561
 562         /* disable instruction breakpoint */
 563         retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, &ibc);
 564         if (retval != ERROR_OK) {
 565                 LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target));
 566                 return retval;
 567         }
 568
 569         ibc &= ~(1 << bp_index);        /* IBC.In */
 570
 571         retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, ibc);
 572         if (retval != ERROR_OK) {
 573                 LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target));
 574                 return retval;
 575         }
 576
 577         esirisc->breakpoints_p[bp_index] = NULL;
 578         breakpoint->set = 0;
 579
 580         return ERROR_OK;
 581 }
 582
 583 static int esirisc_remove_breakpoints(struct target *target)
 584 {
 585         struct esirisc_common *esirisc = target_to_esirisc(target);
 586         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 587
 588         LOG_DEBUG("-");
 589
 590         /* clear instruction breakpoints */
 591         int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, 0);
 592         if (retval != ERROR_OK) {
 593                 LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target));
 594                 return retval;
 595         }
 596
 597         memset(esirisc->breakpoints_p, 0, sizeof(esirisc->breakpoints_p));
 598
 599         return ERROR_OK;
 600 }
 601
 602 static int esirisc_next_watchpoint(struct target *target)
 603 {
 604         struct esirisc_common *esirisc = target_to_esirisc(target);
 605         struct watchpoint **watchpoints_p = esirisc->watchpoints_p;
 606         struct watchpoint **watchpoints_e = watchpoints_p + esirisc->num_watchpoints;
 607
 608         LOG_DEBUG("-");
 609
 610         for (int wp_index = 0; watchpoints_p < watchpoints_e; ++watchpoints_p, ++wp_index)
 611                 if (*watchpoints_p == NULL)
 612                         return wp_index;
 613
 614         return -1;
 615 }
 616
 617 static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 618 {
 619         struct esirisc_common *esirisc = target_to_esirisc(target);
 620         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 621         int wp_index;
 622         uint32_t dbs, dbc;
 623         int retval;
 624
 625         LOG_DEBUG("-");
 626
 627         wp_index = esirisc_next_watchpoint(target);
 628         if (wp_index < 0) {
 629                 LOG_ERROR("%s: out of hardware watchpoints", target_name(target));
 630                 return ERROR_FAIL;
 631         }
 632
 633         watchpoint->set = wp_index + 1;
 634         esirisc->watchpoints_p[wp_index] = watchpoint;
 635
 636         /* specify data breakpoint address */
 637         retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBAn + wp_index,
 638                         watchpoint->address);
 639         if (retval != ERROR_OK) {
 640                 LOG_ERROR("%s: failed to write Debug CSR: DBA", target_name(target));
 641                 return retval;
 642         }
 643
 644         /* specify data breakpoint size */
 645         retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBS, &dbs);
 646         if (retval != ERROR_OK) {
 647                 LOG_ERROR("%s: failed to read Debug CSR: DBS", target_name(target));
 648                 return retval;
 649         }
 650
 651         uint32_t sn;
 652         switch (watchpoint->length) {
 653                 case sizeof(uint64_t):
 654                         sn = 0x3;
 655                         break;
 656                 case sizeof(uint32_t):
 657                         sn = 0x2;
 658                         break;
 659
 660                 case sizeof(uint16_t):
 661                         sn = 0x1;
 662                         break;
 663
 664                 case sizeof(uint8_t):
 665                         sn = 0x0;
 666                         break;
 667
 668                 default:
 669                         LOG_ERROR("%s: unsupported length: %" PRIu32, target_name(target),
 670                                         watchpoint->length);
 671                         return ERROR_FAIL;
 672         }
 673
 674         dbs |= (sn << (2 * wp_index));          /* DBS.Sn */
 675
 676         retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBS, dbs);
 677         if (retval != ERROR_OK) {
 678                 LOG_ERROR("%s: failed to write Debug CSR: DBS", target_name(target));
 679                 return retval;
 680         }
 681
 682         /* enable data breakpoint */
 683         retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, &dbc);
 684         if (retval != ERROR_OK) {
 685                 LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target));
 686                 return retval;
 687         }
 688
 689         uint32_t dn;
 690         switch (watchpoint->rw) {
 691                 case WPT_READ:
 692                         dn = 0x1;
 693                         break;
 694
 695                 case WPT_WRITE:
 696                         dn = 0x2;
 697                         break;
 698
 699                 case WPT_ACCESS:
 700                         dn = 0x3;
 701                         break;
 702
 703                 default:
 704                         LOG_ERROR("%s: unsupported rw: %" PRId32, target_name(target),
 705                                         watchpoint->rw);
 706                         return ERROR_FAIL;
 707         }
 708
 709         dbc |= (dn << (2 * wp_index));          /* DBC.Dn */
 710
 711         retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, dbc);
 712         if (retval != ERROR_OK) {
 713                 LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target));
 714                 return retval;
 715         }
 716
 717         return ERROR_OK;
 718 }
 719
 720 static int esirisc_add_watchpoints(struct target *target)
 721 {
 722         struct watchpoint *watchpoint = target->watchpoints;
 723
 724         LOG_DEBUG("-");
 725
 726         while (watchpoint != NULL) {
 727                 if (watchpoint->set == 0)
 728                         esirisc_add_watchpoint(target, watchpoint);
 729
 730                 watchpoint = watchpoint->next;
 731         }
 732
 733         return ERROR_OK;
 734 }
 735
 736 static int esirisc_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
 737 {
 738         struct esirisc_common *esirisc = target_to_esirisc(target);
 739         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 740         int wp_index = watchpoint->set - 1;
 741         uint32_t dbc;
 742         int retval;
 743
 744         LOG_DEBUG("-");
 745
 746         /* disable data breakpoint */
 747         retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, &dbc);
 748         if (retval != ERROR_OK) {
 749                 LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target));
 750                 return retval;
 751         }
 752
 753         dbc &= ~(0x3 << (2 * wp_index));        /* DBC.Dn */
 754
 755         retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, dbc);
 756         if (retval != ERROR_OK) {
 757                 LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target));
 758                 return retval;
 759         }
 760
 761         esirisc->watchpoints_p[wp_index] = NULL;
 762         watchpoint->set = 0;
 763
 764         return ERROR_OK;
 765 }
 766
 767 static int esirisc_remove_watchpoints(struct target *target)
 768 {
 769         struct esirisc_common *esirisc = target_to_esirisc(target);
 770         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 771
 772         LOG_DEBUG("-");
 773
 774         /* clear data breakpoints */
 775         int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, 0);
 776         if (retval != ERROR_OK) {
 777                 LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target));
 778                 return retval;
 779         }
 780
 781         memset(esirisc->watchpoints_p, 0, sizeof(esirisc->watchpoints_p));
 782
 783         return ERROR_OK;
 784 }
 785
 786 static int esirisc_halt(struct target *target)
 787 {
 788         struct esirisc_common *esirisc = target_to_esirisc(target);
 789         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 790
 791         LOG_DEBUG("-");
 792
 793         if (target->state == TARGET_HALTED)
 794                 return ERROR_OK;
 795
 796         int retval = esirisc_jtag_break(jtag_info);
 797         if (retval != ERROR_OK) {
 798                 LOG_ERROR("%s: failed to halt target", target_name(target));
 799                 return retval;
 800         }
 801
 802         target->debug_reason = DBG_REASON_DBGRQ;
 803
 804         return ERROR_OK;
 805 }
 806
 807 static int esirisc_disable_step(struct target *target)
 808 {
 809         struct esirisc_common *esirisc = target_to_esirisc(target);
 810         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 811         uint32_t dc;
 812         int retval;
 813
 814         LOG_DEBUG("-");
 815
 816         retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, &dc);
 817         if (retval != ERROR_OK) {
 818                 LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target));
 819                 return retval;
 820         }
 821
 822         dc &= ~(1<<0);  /* DC.S */
 823
 824         retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, dc);
 825         if (retval != ERROR_OK) {
 826                 LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target));
 827                 return retval;
 828         }
 829
 830         return ERROR_OK;
 831 }
 832
 833 static int esirisc_enable_step(struct target *target)
 834 {
 835         struct esirisc_common *esirisc = target_to_esirisc(target);
 836         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 837         uint32_t dc;
 838         int retval;
 839
 840         LOG_DEBUG("-");
 841
 842         retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, &dc);
 843         if (retval != ERROR_OK) {
 844                 LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target));
 845                 return retval;
 846         }
 847
 848         dc |= (1<<0);   /* DC.S */
 849
 850         retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, dc);
 851         if (retval != ERROR_OK) {
 852                 LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target));
 853                 return retval;
 854         }
 855
 856         return ERROR_OK;
 857 }
 858
 859 static int esirisc_resume_or_step(struct target *target, int current, target_addr_t address,
 860                 int handle_breakpoints, int debug_execution, bool step)
 861 {
 862         struct esirisc_common *esirisc = target_to_esirisc(target);
 863         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 864         struct breakpoint *breakpoint = NULL;
 865         int retval;
 866
 867         LOG_DEBUG("-");
 868
 869         if (target->state != TARGET_HALTED)
 870                 return ERROR_TARGET_NOT_HALTED;
 871
 872         if (!debug_execution) {
 873                 target_free_all_working_areas(target);
 874                 esirisc_add_breakpoints(target);
 875                 esirisc_add_watchpoints(target);
 876         }
 877
 878         if (current)
 879                 address = buf_get_u32(esirisc->epc->value, 0, esirisc->epc->size);
 880         else {
 881                 buf_set_u32(esirisc->epc->value, 0, esirisc->epc->size, address);
 882                 esirisc->epc->dirty = true;
 883                 esirisc->epc->valid = true;
 884         }
 885
 886         esirisc_restore_context(target);
 887
 888         if (esirisc_has_cache(esirisc))
 889                 esirisc_flush_caches(target);
 890
 891         if (handle_breakpoints) {
 892                 breakpoint = breakpoint_find(target, address);
 893                 if (breakpoint != NULL)
 894                         esirisc_remove_breakpoint(target, breakpoint);
 895         }
 896
 897         if (step) {
 898                 esirisc_disable_interrupts(target);
 899                 esirisc_enable_step(target);
 900                 target->debug_reason = DBG_REASON_SINGLESTEP;
 901         } else {
 902                 esirisc_disable_step(target);
 903                 esirisc_restore_interrupts(target);
 904                 target->debug_reason = DBG_REASON_NOTHALTED;
 905         }
 906
 907         esirisc_restore_hwdc(target);
 908
 909         retval = esirisc_jtag_continue(jtag_info);
 910         if (retval != ERROR_OK) {
 911                 LOG_ERROR("%s: failed to resume target", target_name(target));
 912                 return retval;
 913         }
 914
 915         register_cache_invalidate(esirisc->reg_cache);
 916
 917         if (!debug_execution) {
 918                 target->state = TARGET_RUNNING;
 919                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 920         } else {
 921                 target->state = TARGET_DEBUG_RUNNING;
 922                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 923         }
 924
 925         return ERROR_OK;
 926 }
 927
 928 static int esirisc_resume(struct target *target, int current, target_addr_t address,
 929                 int handle_breakpoints, int debug_execution)
 930 {
 931         LOG_DEBUG("-");
 932
 933         return esirisc_resume_or_step(target, current, address,
 934                         handle_breakpoints, debug_execution, false);
 935 }
 936
 937 static int esirisc_step(struct target *target, int current, target_addr_t address,
 938                 int handle_breakpoints)
 939 {
 940         LOG_DEBUG("-");
 941
 942         return esirisc_resume_or_step(target, current, address,
 943                         handle_breakpoints, 0, true);
 944 }
 945
 946 static int esirisc_debug_step(struct target *target)
 947 {
 948         struct esirisc_common *esirisc = target_to_esirisc(target);
 949         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 950         int retval;
 951
 952         LOG_DEBUG("-");
 953
 954         esirisc_disable_interrupts(target);
 955         esirisc_enable_step(target);
 956
 957         retval = esirisc_jtag_continue(jtag_info);
 958         if (retval != ERROR_OK) {
 959                 LOG_ERROR("%s: failed to resume target", target_name(target));
 960                 return retval;
 961         }
 962
 963         retval = esirisc_wait_debug_active(esirisc, STEP_TIMEOUT);
 964         if (retval != ERROR_OK) {
 965                 LOG_ERROR("%s: step timed out", target_name(target));
 966                 return retval;
 967         }
 968
 969         esirisc_disable_step(target);
 970         esirisc_restore_interrupts(target);
 971
 972         return ERROR_OK;
 973 }
 974
 975 static int esirisc_debug_reset(struct target *target)
 976 {
 977         struct esirisc_common *esirisc = target_to_esirisc(target);
 978         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
 979         int retval;
 980
 981         LOG_DEBUG("-");
 982
 983         retval = esirisc_jtag_assert_reset(jtag_info);
 984         if (retval != ERROR_OK) {
 985                 LOG_ERROR("%s: failed to assert reset", target_name(target));
 986                 return retval;
 987         }
 988
 989         retval = esirisc_jtag_deassert_reset(jtag_info);
 990         if (retval != ERROR_OK) {
 991                 LOG_ERROR("%s: failed to deassert reset", target_name(target));
 992                 return retval;
 993         }
 994
 995         retval = esirisc_wait_debug_active(esirisc, RESET_TIMEOUT);
 996         if (retval != ERROR_OK) {
 997                 LOG_ERROR("%s: reset timed out", target_name(target));
 998                 return retval;
 999         }
1000
1001         return ERROR_OK;
1002 }
1003
1004 static int esirisc_debug_enable(struct target *target)
1005 {
1006         struct esirisc_common *esirisc = target_to_esirisc(target);
1007         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1008         int retval;
1009
1010         LOG_DEBUG("-");
1011
1012         retval = esirisc_jtag_enable_debug(jtag_info);
1013         if (retval != ERROR_OK) {
1014                 LOG_ERROR("%s: failed to enable debug mode", target_name(target));
1015                 return retval;
1016         }
1017
1018         /*
1019          * The debug clock is inactive until the first command is sent.
1020          * If the target is stopped, we must first issue a reset before
1021          * attempting further communication. This also handles unpowered
1022          * targets, which will respond with all ones and appear active.
1023          */
1024         if (esirisc_jtag_is_stopped(jtag_info)) {
1025                 LOG_INFO("%s: debug clock inactive; attempting debug reset", target_name(target));
1026                 retval = esirisc_debug_reset(target);
1027                 if (retval != ERROR_OK)
1028                         return retval;
1029
1030                 if (esirisc_jtag_is_stopped(jtag_info)) {
1031                         LOG_ERROR("%s: target unresponsive; giving up", target_name(target));
1032                         return ERROR_FAIL;
1033                 }
1034         }
1035
1036         return ERROR_OK;
1037 }
1038
1039 static int esirisc_debug_entry(struct target *target)
1040 {
1041         struct esirisc_common *esirisc = target_to_esirisc(target);
1042         struct breakpoint *breakpoint;
1043
1044         LOG_DEBUG("-");
1045
1046         esirisc_save_context(target);
1047
1048         if (esirisc_has_cache(esirisc))
1049                 esirisc_flush_caches(target);
1050
1051         if (target->debug_reason != DBG_REASON_SINGLESTEP) {
1052                 esirisc_save_interrupts(target);
1053
1054                 uint32_t eid = buf_get_u32(esirisc->eid->value, 0, esirisc->eid->size);
1055                 switch (eid) {
1056                         /*
1057                          * InstBreakpoint exceptions are also raised when a core is
1058                          * halted for debugging. The following is required to
1059                          * determine if a breakpoint was encountered.
1060                          */
1061                         case EID_INST_BREAKPOINT:
1062                                 breakpoint = breakpoint_find(target,
1063                                                 buf_get_u32(esirisc->epc->value, 0, esirisc->epc->size));
1064                                 target->debug_reason = (breakpoint != NULL) ?
1065                                                 DBG_REASON_BREAKPOINT : DBG_REASON_DBGRQ;
1066                                 break;
1067
1068                         /*
1069                          * eSi-RISC treats watchpoints similarly to breakpoints,
1070                          * however GDB will not request to step over the current
1071                          * instruction when a watchpoint fires. The following is
1072                          * required to resume the target.
1073                          */
1074                         case EID_DATA_BREAKPOINT:
1075                                 esirisc_remove_watchpoints(target);
1076                                 esirisc_debug_step(target);
1077                                 esirisc_add_watchpoints(target);
1078                                 target->debug_reason = DBG_REASON_WATCHPOINT;
1079                                 break;
1080
1081                         default:
1082                                 target->debug_reason = DBG_REASON_DBGRQ;
1083                 }
1084         }
1085
1086         return ERROR_OK;
1087 }
1088
1089 static int esirisc_poll(struct target *target)
1090 {
1091         struct esirisc_common *esirisc = target_to_esirisc(target);
1092         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1093         int retval;
1094
1095         retval = esirisc_jtag_enable_debug(jtag_info);
1096         if (retval != ERROR_OK) {
1097                 LOG_ERROR("%s: failed to poll target", target_name(target));
1098                 return retval;
1099         }
1100
1101         if (esirisc_jtag_is_stopped(jtag_info)) {
1102                 LOG_ERROR("%s: target has stopped; reset required", target_name(target));
1103                 target->state = TARGET_UNKNOWN;
1104                 return ERROR_TARGET_FAILURE;
1105         }
1106
1107         if (esirisc_jtag_is_debug_active(jtag_info)) {
1108                 if (target->state == TARGET_RUNNING || target->state == TARGET_RESET) {
1109                         target->state = TARGET_HALTED;
1110
1111                         retval = esirisc_debug_entry(target);
1112                         if (retval != ERROR_OK)
1113                                 return retval;
1114
1115                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1116                 }
1117
1118         } else if (target->state == TARGET_HALTED || target->state == TARGET_RESET) {
1119                 target->state = TARGET_RUNNING;
1120                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1121         }
1122
1123         return ERROR_OK;
1124 }
1125
1126 static int esirisc_assert_reset(struct target *target)
1127 {
1128         struct esirisc_common *esirisc = target_to_esirisc(target);
1129         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1130         int retval;
1131
1132         LOG_DEBUG("-");
1133
1134         if (jtag_get_reset_config() & RESET_HAS_SRST) {
1135                 jtag_add_reset(1, 1);
1136                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) == 0)
1137                         jtag_add_reset(0, 1);
1138         } else {
1139                 esirisc_remove_breakpoints(target);
1140                 esirisc_remove_watchpoints(target);
1141
1142                 retval = esirisc_jtag_assert_reset(jtag_info);
1143                 if (retval != ERROR_OK) {
1144                         LOG_ERROR("%s: failed to assert reset", target_name(target));
1145                         return retval;
1146                 }
1147         }
1148
1149         target->state = TARGET_RESET;
1150
1151         register_cache_invalidate(esirisc->reg_cache);
1152
1153         return ERROR_OK;
1154 }
1155
1156 static int esirisc_reset_entry(struct target *target)
1157 {
1158         struct esirisc_common *esirisc = target_to_esirisc(target);
1159         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1160         uint32_t eta, epc;
1161         int retval;
1162
1163         LOG_DEBUG("-");
1164
1165         /* read exception table address */
1166         retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETA, &eta);
1167         if (retval != ERROR_OK) {
1168                 LOG_ERROR("%s: failed to read Thread CSR: ETA", target_name(target));
1169                 return retval;
1170         }
1171
1172         /* read reset entry point */
1173         retval = esirisc_jtag_read_word(jtag_info, eta + ENTRY_RESET, &epc);
1174         if (retval != ERROR_OK) {
1175                 LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR, target_name(target),
1176                                 (target_addr_t)epc);
1177                 return retval;
1178         }
1179
1180         /* write reset entry point */
1181         retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_EPC, epc);
1182         if (retval != ERROR_OK) {
1183                 LOG_ERROR("%s: failed to write Thread CSR: EPC", target_name(target));
1184                 return retval;
1185         }
1186
1187         return ERROR_OK;
1188 }
1189
1190 static int esirisc_deassert_reset(struct target *target)
1191 {
1192         struct esirisc_common *esirisc = target_to_esirisc(target);
1193         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1194         int retval;
1195
1196         LOG_DEBUG("-");
1197
1198         if (jtag_get_reset_config() & RESET_HAS_SRST) {
1199                 jtag_add_reset(0, 0);
1200
1201                 retval = esirisc_debug_enable(target);
1202                 if (retval != ERROR_OK)
1203                         return retval;
1204
1205                 retval = esirisc_debug_reset(target);
1206                 if (retval != ERROR_OK)
1207                         return retval;
1208
1209         } else {
1210                 retval = esirisc_jtag_deassert_reset(jtag_info);
1211                 if (retval != ERROR_OK) {
1212                         LOG_ERROR("%s: failed to deassert reset", target_name(target));
1213                         return retval;
1214                 }
1215         }
1216
1217         retval = esirisc_wait_debug_active(esirisc, RESET_TIMEOUT);
1218         if (retval != ERROR_OK) {
1219                 LOG_ERROR("%s: reset timed out", target_name(target));
1220                 return retval;
1221         }
1222
1223         retval = esirisc_reset_entry(target);
1224         if (retval != ERROR_OK)
1225                 return retval;
1226
1227         esirisc_add_breakpoints(target);
1228         esirisc_add_watchpoints(target);
1229
1230         esirisc_restore_hwdc(target);
1231
1232         if (!target->reset_halt) {
1233                 retval = esirisc_jtag_continue(jtag_info);
1234                 if (retval != ERROR_OK) {
1235                         LOG_ERROR("%s: failed to resume target", target_name(target));
1236                         return retval;
1237                 }
1238         }
1239
1240         return ERROR_OK;
1241 }
1242
1243 static int esirisc_arch_state(struct target *target)
1244 {
1245         struct esirisc_common *esirisc = target_to_esirisc(target);
1246         uint32_t epc = buf_get_u32(esirisc->epc->value, 0, esirisc->epc->size);
1247         uint32_t ecas = buf_get_u32(esirisc->ecas->value, 0, esirisc->ecas->size);
1248         uint32_t eid = buf_get_u32(esirisc->eid->value, 0, esirisc->eid->size);
1249         uint32_t ed = buf_get_u32(esirisc->ed->value, 0, esirisc->ed->size);
1250
1251         LOG_USER("target halted due to %s, exception: %s\n"
1252                         "EPC: 0x%" PRIx32 ", ECAS: 0x%" PRIx32 ", EID: 0x%" PRIx32 ", ED: 0x%" PRIx32,
1253                         debug_reason_name(target), esirisc_exception_strings[eid], epc, ecas, eid, ed);
1254
1255         return ERROR_OK;
1256 }
1257
1258 static const char *esirisc_get_gdb_arch(struct target *target)
1259 {
1260         struct esirisc_common *esirisc = target_to_esirisc(target);
1261
1262         LOG_DEBUG("-");
1263
1264         /*
1265          * Targets with the UNIFIED_ADDRESS_SPACE option disabled employ a
1266          * Harvard architecture. This option is not exposed in a CSR, which
1267          * requires additional configuration to properly interact with these
1268          * targets in GDB (also see: `esirisc cache_arch`).
1269          */
1270         if (esirisc->gdb_arch == NULL && target_was_examined(target))
1271                 esirisc->gdb_arch = alloc_printf("esirisc:%d_bit_%d_reg_%s",
1272                                 esirisc->num_bits, esirisc->num_regs, esirisc_cache_arch_name(esirisc));
1273
1274         return esirisc->gdb_arch;
1275 }
1276
1277 static int esirisc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
1278                 int *reg_list_size, enum target_register_class reg_class)
1279 {
1280         struct esirisc_common *esirisc = target_to_esirisc(target);
1281
1282         LOG_DEBUG("-");
1283
1284         *reg_list_size = ESIRISC_NUM_REGS;
1285
1286         *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
1287         if (*reg_list == NULL)
1288                 return ERROR_FAIL;
1289
1290         if (reg_class == REG_CLASS_ALL)
1291                 for (int i = 0; i < *reg_list_size; ++i)
1292                         (*reg_list)[i] = esirisc->reg_cache->reg_list + i;
1293         else {
1294                 for (int i = 0; i < esirisc->num_regs; ++i)
1295                         (*reg_list)[i] = esirisc->reg_cache->reg_list + i;
1296
1297                 (*reg_list)[ESIRISC_PC] = esirisc->reg_cache->reg_list + ESIRISC_PC;
1298                 (*reg_list)[ESIRISC_CAS] = esirisc->reg_cache->reg_list + ESIRISC_CAS;
1299         }
1300
1301         return ERROR_OK;
1302 }
1303
1304 static int esirisc_read_reg(struct reg *reg)
1305 {
1306         struct esirisc_reg *reg_info = reg->arch_info;
1307         struct esirisc_common *esirisc = reg_info->esirisc;
1308         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1309         struct target *target = esirisc->target;
1310         uint32_t data;
1311
1312         LOG_DEBUG("-");
1313
1314         int retval = esirisc_jtag_read_reg(jtag_info, reg->number, &data);
1315         if (retval != ERROR_OK) {
1316                 LOG_ERROR("%s: failed to read register: %s", target_name(target), reg->name);
1317                 return retval;
1318         }
1319
1320         buf_set_u32(reg->value, 0, reg->size, data);
1321         reg->dirty = false;
1322         reg->valid = true;
1323
1324         return ERROR_OK;
1325 }
1326
1327 static int esirisc_write_reg(struct reg *reg)
1328 {
1329         struct esirisc_reg *reg_info = reg->arch_info;
1330         struct esirisc_common *esirisc = reg_info->esirisc;
1331         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1332         struct target *target = esirisc->target;
1333         uint32_t data = buf_get_u32(reg->value, 0, reg->size);
1334
1335         LOG_DEBUG("-");
1336
1337         int retval = esirisc_jtag_write_reg(jtag_info, reg->number, data);
1338         if (retval != ERROR_OK) {
1339                 LOG_ERROR("%s: failed to write register: %s", target_name(target), reg->name);
1340                 return retval;
1341         }
1342
1343         reg->dirty = false;
1344         reg->valid = true;
1345
1346         return ERROR_OK;
1347 }
1348
1349 static int esirisc_read_csr(struct reg *reg)
1350 {
1351         struct esirisc_reg *reg_info = reg->arch_info;
1352         struct esirisc_common *esirisc = reg_info->esirisc;
1353         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1354         struct target *target = esirisc->target;
1355         uint32_t data;
1356
1357         LOG_DEBUG("-");
1358
1359         int retval = esirisc_jtag_read_csr(jtag_info, reg_info->bank, reg_info->csr, &data);
1360         if (retval != ERROR_OK) {
1361                 LOG_ERROR("%s: failed to read CSR: %s", target_name(target), reg->name);
1362                 return retval;
1363         }
1364
1365         buf_set_u32(reg->value, 0, reg->size, data);
1366         reg->dirty = false;
1367         reg->valid = true;
1368
1369         return ERROR_OK;
1370 }
1371
1372 static int esirisc_write_csr(struct reg *reg)
1373 {
1374         struct esirisc_reg *reg_info = reg->arch_info;
1375         struct esirisc_common *esirisc = reg_info->esirisc;
1376         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1377         struct target *target = esirisc->target;
1378         uint32_t data = buf_get_u32(reg->value, 0, reg->size);
1379
1380         LOG_DEBUG("-");
1381
1382         int retval = esirisc_jtag_write_csr(jtag_info, reg_info->bank, reg_info->csr, data);
1383         if (retval != ERROR_OK) {
1384                 LOG_ERROR("%s: failed to write CSR: %s", target_name(target), reg->name);
1385                 return retval;
1386         }
1387
1388         reg->dirty = false;
1389         reg->valid = true;
1390
1391         return ERROR_OK;
1392 }
1393
1394 static int esirisc_get_reg(struct reg *reg)
1395 {
1396         struct esirisc_reg *reg_info = reg->arch_info;
1397         struct esirisc_common *esirisc = reg_info->esirisc;
1398         struct target *target = esirisc->target;
1399
1400         LOG_DEBUG("-");
1401
1402         if (target->state != TARGET_HALTED)
1403                 return ERROR_TARGET_NOT_HALTED;
1404
1405         return reg_info->read(reg);
1406 }
1407
1408 static int esirisc_set_reg(struct reg *reg, uint8_t *buf)
1409 {
1410         struct esirisc_reg *reg_info = reg->arch_info;
1411         struct esirisc_common *esirisc = reg_info->esirisc;
1412         struct target *target = esirisc->target;
1413         uint32_t value = buf_get_u32(buf, 0, reg->size);
1414
1415         LOG_DEBUG("-");
1416
1417         if (target->state != TARGET_HALTED)
1418                 return ERROR_TARGET_NOT_HALTED;
1419
1420         buf_set_u32(reg->value, 0, reg->size, value);
1421         reg->dirty = true;
1422         reg->valid = true;
1423
1424         return ERROR_OK;
1425 }
1426
1427 static const struct reg_arch_type esirisc_reg_type = {
1428         .get = esirisc_get_reg,
1429         .set = esirisc_set_reg,
1430 };
1431
1432 static struct reg_cache *esirisc_build_reg_cache(struct target *target)
1433 {
1434         struct esirisc_common *esirisc = target_to_esirisc(target);
1435         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1436         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
1437         struct reg *reg_list = calloc(ESIRISC_NUM_REGS, sizeof(struct reg));
1438
1439         LOG_DEBUG("-");
1440
1441         cache->name = "eSi-RISC registers";
1442         cache->next = NULL;
1443         cache->reg_list = reg_list;
1444         cache->num_regs = ESIRISC_NUM_REGS;
1445         (*cache_p) = cache;
1446
1447         esirisc->reg_cache = cache;
1448         esirisc->epc = reg_list + ESIRISC_EPC;
1449         esirisc->ecas = reg_list + ESIRISC_ECAS;
1450         esirisc->eid = reg_list + ESIRISC_EID;
1451         esirisc->ed = reg_list + ESIRISC_ED;
1452
1453         for (int i = 0; i < esirisc->num_regs; ++i) {
1454                 struct reg *reg = reg_list + esirisc_regs[i].number;
1455                 struct esirisc_reg *reg_info = calloc(1, sizeof(struct esirisc_reg));
1456
1457                 reg->name = esirisc_regs[i].name;
1458                 reg->number = esirisc_regs[i].number;
1459                 reg->value = calloc(1, DIV_ROUND_UP(esirisc->num_bits, 8));
1460                 reg->size = esirisc->num_bits;
1461                 reg->reg_data_type = calloc(1, sizeof(struct reg_data_type));
1462                 reg->reg_data_type->type = esirisc_regs[i].type;
1463                 reg->group = esirisc_regs[i].group;
1464                 reg_info->esirisc = esirisc;
1465                 reg_info->read = esirisc_read_reg;
1466                 reg_info->write = esirisc_write_reg;
1467                 reg->arch_info = reg_info;
1468                 reg->type = &esirisc_reg_type;
1469                 reg->exist = true;
1470         }
1471
1472         for (size_t i = 0; i < ARRAY_SIZE(esirisc_csrs); ++i) {
1473                 struct reg *reg = reg_list + esirisc_csrs[i].number;
1474                 struct esirisc_reg *reg_info = calloc(1, sizeof(struct esirisc_reg));
1475
1476                 reg->name = esirisc_csrs[i].name;
1477                 reg->number = esirisc_csrs[i].number;
1478                 reg->value = calloc(1, DIV_ROUND_UP(esirisc->num_bits, 8));
1479                 reg->size = esirisc->num_bits;
1480                 reg->reg_data_type = calloc(1, sizeof(struct reg_data_type));
1481                 reg->reg_data_type->type = esirisc_csrs[i].type;
1482                 reg->group = esirisc_csrs[i].group;
1483                 reg_info->esirisc = esirisc;
1484                 reg_info->bank = esirisc_csrs[i].bank;
1485                 reg_info->csr = esirisc_csrs[i].csr;
1486                 reg_info->read = esirisc_read_csr;
1487                 reg_info->write = esirisc_write_csr;
1488                 reg->arch_info = reg_info;
1489                 reg->type = &esirisc_reg_type;
1490                 reg->exist = true;
1491         }
1492
1493         return cache;
1494 }
1495
1496 static int esirisc_identify(struct target *target)
1497 {
1498         struct esirisc_common *esirisc = target_to_esirisc(target);
1499         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1500         uint32_t csr;
1501         int retval;
1502
1503         LOG_DEBUG("-");
1504
1505         retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_ARCH0, &csr);
1506         if (retval != ERROR_OK) {
1507                 LOG_ERROR("%s: failed to read Configuration CSR: ARCH0", target_name(target));
1508                 return retval;
1509         }
1510
1511         esirisc->num_bits = (csr >> 0) & 0x3f;                  /* ARCH0.B */
1512         esirisc->num_regs = (csr >> 10) & 0x3f;                 /* ARCH0.R */
1513
1514         retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_MEM, &csr);
1515         if (retval != ERROR_OK) {
1516                 LOG_ERROR("%s: failed to read Configuration CSR: MEM", target_name(target));
1517                 return retval;
1518         }
1519
1520         target->endianness = (csr & 1<<0) ?                             /* MEM.E */
1521                         TARGET_BIG_ENDIAN : TARGET_LITTLE_ENDIAN;
1522
1523         retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_IC, &csr);
1524         if (retval != ERROR_OK) {
1525                 LOG_ERROR("%s: failed to read Configuration CSR: IC", target_name(target));
1526                 return retval;
1527         }
1528
1529         esirisc->has_icache = !!(csr & 1<<0);                   /* IC.E */
1530
1531         retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_DC, &csr);
1532         if (retval != ERROR_OK) {
1533                 LOG_ERROR("%s: failed to read Configuration CSR: DC", target_name(target));
1534                 return retval;
1535         }
1536
1537         esirisc->has_dcache = !!(csr & 1<<0);                   /* DC.E */
1538
1539         retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_DBG, &csr);
1540         if (retval != ERROR_OK) {
1541                 LOG_ERROR("%s: failed to read Configuration CSR: DBG", target_name(target));
1542                 return retval;
1543         }
1544
1545         esirisc->num_breakpoints = (csr >> 7) & 0xf;    /* DBG.BP */
1546         esirisc->num_watchpoints = (csr >> 12) & 0xf;   /* DBG.WP */
1547
1548         retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_TRACE, &csr);
1549         if (retval != ERROR_OK) {
1550                 LOG_ERROR("%s: failed to read Configuration CSR: TRACE", target_name(target));
1551                 return retval;
1552         }
1553
1554         esirisc->has_trace = !!(csr & 1<<0);                    /* TRACE.T */
1555
1556         return ERROR_OK;
1557 }
1558
1559 static int esirisc_target_create(struct target *target, Jim_Interp *interp)
1560 {
1561         struct jtag_tap *tap = target->tap;
1562         struct esirisc_common *esirisc;
1563
1564         if (tap == NULL)
1565                 return ERROR_FAIL;
1566
1567         if (tap->ir_length != INSTR_LENGTH) {
1568                 LOG_ERROR("%s: invalid IR length; expected %d", target_name(target),
1569                                 INSTR_LENGTH);
1570                 return ERROR_FAIL;
1571         }
1572
1573         esirisc = calloc(1, sizeof(struct esirisc_common));
1574         if (esirisc == NULL)
1575                 return ERROR_FAIL;
1576
1577         esirisc->target = target;
1578         esirisc->jtag_info.tap = tap;
1579         target->arch_info = esirisc;
1580
1581         return ERROR_OK;
1582 }
1583
1584 static int esirisc_init_target(struct command_context *cmd_ctx, struct target *target)
1585 {
1586         struct esirisc_common *esirisc = target_to_esirisc(target);
1587
1588         /* trap reset, error, and debug exceptions */
1589         esirisc->hwdc_save = HWDC_R | HWDC_E | HWDC_D;
1590
1591         return ERROR_OK;
1592 }
1593
1594 static int esirisc_examine(struct target *target)
1595 {
1596         struct esirisc_common *esirisc = target_to_esirisc(target);
1597         struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1598         int retval;
1599
1600         LOG_DEBUG("-");
1601
1602         if (!target_was_examined(target)) {
1603                 retval = esirisc_debug_enable(target);
1604                 if (retval != ERROR_OK)
1605                         return retval;
1606
1607                 /*
1608                  * In order to identify the target we must first halt the core.
1609                  * We quietly resume once identification has completed for those
1610                  * targets that were running when target_examine was called.
1611                  */
1612                 if (esirisc_jtag_is_debug_active(jtag_info)) {
1613                         if (target->state == TARGET_UNKNOWN)
1614                                 target->debug_reason = DBG_REASON_DBGRQ;
1615
1616                         target->state = TARGET_HALTED;
1617                 } else {
1618                         retval = esirisc_jtag_break(jtag_info);
1619                         if (retval != ERROR_OK) {
1620                                 LOG_ERROR("%s: failed to halt target", target_name(target));
1621                                 return retval;
1622                         }
1623
1624                         target->state = TARGET_RUNNING;
1625                 }
1626
1627                 retval = esirisc_identify(target);
1628                 if (retval != ERROR_OK) {
1629                         LOG_ERROR("%s: failed to identify target", target_name(target));
1630                         return retval;
1631                 }
1632
1633                 esirisc_build_reg_cache(target);
1634
1635                 esirisc_remove_breakpoints(target);
1636                 esirisc_remove_watchpoints(target);
1637
1638                 esirisc_disable_step(target);
1639                 esirisc_restore_hwdc(target);
1640
1641                 if (target->state == TARGET_HALTED)
1642                         esirisc_save_interrupts(target);
1643                 else {
1644                         retval = esirisc_jtag_continue(jtag_info);
1645                         if (retval != ERROR_OK) {
1646                                 LOG_ERROR("%s: failed to resume target", target_name(target));
1647                                 return retval;
1648                         }
1649                 }
1650
1651                 target_set_examined(target);
1652
1653                 LOG_INFO("%s: %d bit, %d registers, %s%s%s", target_name(target),
1654                                 esirisc->num_bits, esirisc->num_regs,
1655                                 target_endianness(target),
1656                                 esirisc->has_icache ? ", icache" : "",
1657                                 esirisc->has_dcache ? ", dcache" : "");
1658
1659                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints%s", target_name(target),
1660                                 esirisc->num_breakpoints, esirisc->num_watchpoints,
1661                                 esirisc->has_trace ? ", trace" : "");
1662         }
1663
1664         return ERROR_OK;
1665 }
1666
1667 COMMAND_HANDLER(handle_esirisc_cache_arch_command)
1668 {
1669         struct target *target = get_current_target(CMD_CTX);
1670         struct esirisc_common *esirisc = target_to_esirisc(target);
1671
1672         if (CMD_ARGC > 0) {
1673                 if (strcmp(*CMD_ARGV, "harvard") == 0)
1674                         esirisc->cache_arch = ESIRISC_CACHE_HARVARD;
1675                 else if (strcmp(*CMD_ARGV, "von_neumann") == 0)
1676                         esirisc->cache_arch = ESIRISC_CACHE_VON_NEUMANN;
1677                 else {
1678                         LOG_ERROR("invalid cache_arch: %s", *CMD_ARGV);
1679                         return ERROR_COMMAND_SYNTAX_ERROR;
1680                 }
1681         }
1682
1683         command_print(CMD_CTX, "esirisc cache_arch %s", esirisc_cache_arch_name(esirisc));
1684
1685         return ERROR_OK;
1686 }
1687
1688 COMMAND_HANDLER(handle_esirisc_flush_caches_command)
1689 {
1690         struct target *target = get_current_target(CMD_CTX);
1691         struct esirisc_common *esirisc = target_to_esirisc(target);
1692         int retval;
1693
1694         if (!esirisc_has_cache(esirisc)) {
1695                 LOG_ERROR("target does not support caching");
1696                 return ERROR_FAIL;
1697         }
1698
1699         retval = esirisc_flush_caches(target);
1700
1701         command_print(CMD_CTX, "cache flush %s",
1702                         (retval == ERROR_OK) ? "successful" : "failed");
1703
1704         return retval;
1705 }
1706
1707 static const struct {
1708         const char *name;
1709         int mask;
1710 } esirisc_hwdc_masks[] = {
1711         { "reset",              HWDC_R },
1712         { "interrupt",  HWDC_I },
1713         { "syscall",    HWDC_S },
1714         { "error",              HWDC_E },
1715         { "debug",              HWDC_D },
1716 };
1717
1718 static int esirisc_find_hwdc_mask(const char *name)
1719 {
1720         for (size_t i = 0; i < ARRAY_SIZE(esirisc_hwdc_masks); ++i)
1721                 if (strcmp(esirisc_hwdc_masks[i].name, name) == 0)
1722                         return esirisc_hwdc_masks[i].mask;
1723
1724         return -1;
1725 }
1726
1727 COMMAND_HANDLER(handle_esirisc_hwdc_command)
1728 {
1729         struct target *target = get_current_target(CMD_CTX);
1730         struct esirisc_common *esirisc = target_to_esirisc(target);
1731
1732         if (CMD_ARGC > 0) {
1733                 if (strcmp(CMD_ARGV[0], "all") == 0)
1734                         esirisc->hwdc_save = HWDC_R | HWDC_I | HWDC_S | HWDC_E | HWDC_D;
1735                 else {
1736                         esirisc->hwdc_save = 0;
1737                         if (strcmp(CMD_ARGV[0], "none") != 0) {
1738                                 while (CMD_ARGC-- > 0) {
1739                                         int mask = esirisc_find_hwdc_mask(CMD_ARGV[CMD_ARGC]);
1740                                         if (mask < 0) {
1741                                                 LOG_ERROR("invalid mask: %s", CMD_ARGV[CMD_ARGC]);
1742                                                 return ERROR_COMMAND_SYNTAX_ERROR;
1743                                         }
1744                                         esirisc->hwdc_save |= mask;
1745                                 }
1746                         }
1747                 }
1748         }
1749
1750         for (size_t i = 0; i < ARRAY_SIZE(esirisc_hwdc_masks); ++i)
1751                 command_print(CMD_CTX, "%9s: %s", esirisc_hwdc_masks[i].name,
1752                                 (esirisc->hwdc_save & esirisc_hwdc_masks[i].mask) ? "enabled" : "disabled");
1753
1754         return ERROR_OK;
1755 }
1756
1757 static const struct command_registration esirisc_exec_command_handlers[] = {
1758         {
1759                 .name = "flush_caches",
1760                 .handler = handle_esirisc_flush_caches_command,
1761                 .mode = COMMAND_EXEC,
1762                 .help = "flush instruction and data caches",
1763                 .usage = "",
1764         },
1765         COMMAND_REGISTRATION_DONE
1766 };
1767
1768 static const struct command_registration esirisc_any_command_handlers[] = {
1769         {
1770                 .name = "cache_arch",
1771                 .handler = handle_esirisc_cache_arch_command,
1772                 .mode = COMMAND_ANY,
1773                 .help = "configure cache architecture",
1774                 .usage = "['harvard'|'von_neumann']",
1775         },
1776         {
1777                 .name = "hwdc",
1778                 .handler = handle_esirisc_hwdc_command,
1779                 .mode = COMMAND_ANY,
1780                 .help = "configure hardware debug control",
1781                 .usage = "['all'|'none'|mask ...]",
1782         },
1783         {
1784                 .chain = esirisc_exec_command_handlers
1785         },
1786         {
1787                 .chain = esirisc_trace_command_handlers
1788         },
1789         COMMAND_REGISTRATION_DONE
1790 };
1791
1792 static const struct command_registration esirisc_command_handlers[] = {
1793         {
1794                 .name = "esirisc",
1795                 .mode = COMMAND_ANY,
1796                 .help = "eSi-RISC command group",
1797                 .usage = "",
1798                 .chain = esirisc_any_command_handlers,
1799         },
1800         COMMAND_REGISTRATION_DONE
1801 };
1802
1803 struct target_type esirisc_target = {
1804         .name = "esirisc",
1805
1806         .poll = esirisc_poll,
1807         .arch_state = esirisc_arch_state,
1808
1809         .halt = esirisc_halt,
1810         .resume = esirisc_resume,
1811         .step = esirisc_step,
1812
1813         .assert_reset = esirisc_assert_reset,
1814         .deassert_reset = esirisc_deassert_reset,
1815
1816         .get_gdb_arch = esirisc_get_gdb_arch,
1817         .get_gdb_reg_list = esirisc_get_gdb_reg_list,
1818
1819         .read_memory = esirisc_read_memory,
1820         .write_memory = esirisc_write_memory,
1821         .checksum_memory = esirisc_checksum_memory,
1822
1823         .add_breakpoint = esirisc_add_breakpoint,
1824         .remove_breakpoint = esirisc_remove_breakpoint,
1825         .add_watchpoint = esirisc_add_watchpoint,
1826         .remove_watchpoint = esirisc_remove_watchpoint,
1827
1828         .commands = esirisc_command_handlers,
1829
1830         .target_create = esirisc_target_create,
1831         .init_target = esirisc_init_target,
1832         .examine = esirisc_examine,
1833 };