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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008,2009 Øyvind Harboe                            *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "embeddedice.h"
  31 #include "register.h"
  32
  33 /**
  34  * @file
  35  *
  36  * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT)
  37  * module found on scan chain 2 in ARM7, ARM9, and some other families
  38  * of ARM cores.
  39  *
  40  * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug
  41  * Communications Channel (DCC) used to read or write 32-bit words to
  42  * OpenOCD-aware code running on the target CPU.
  43  * Newer modules also include vector catch hardware.  Some versions
  44  * support hardware single-stepping, "monitor mode" debug (which is not
  45  * currently supported by OpenOCD), or extended reporting on why the
  46  * core entered debug mode.
  47  */
  48
  49 /*
  50  * From:  ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
  51  */
  52 static const struct {
  53         char            *name;
  54         unsigned short  addr;
  55         unsigned short  width;
  56 } eice_regs[] = {
  57         [EICE_DBG_CTRL] = {
  58                 .name =         "debug_ctrl",
  59                 .addr =         0,
  60                 /* width is assigned based on EICE version */
  61         },
  62         [EICE_DBG_STAT] = {
  63                 .name =         "debug_status",
  64                 .addr =         1,
  65                 /* width is assigned based on EICE version */
  66         },
  67         [EICE_COMMS_CTRL] = {
  68                 .name =         "comms_ctrl",
  69                 .addr =         4,
  70                 .width =        6,
  71         },
  72         [EICE_COMMS_DATA] = {
  73                 .name =         "comms_data",
  74                 .addr =         5,
  75                 .width =        32,
  76         },
  77         [EICE_W0_ADDR_VALUE] = {
  78                 .name =         "watch_0_addr_value",
  79                 .addr =         8,
  80                 .width =        32,
  81         },
  82         [EICE_W0_ADDR_MASK] = {
  83                 .name =         "watch_0_addr_mask",
  84                 .addr =         9,
  85                 .width =        32,
  86         },
  87         [EICE_W0_DATA_VALUE ] = {
  88                 .name =         "watch_0_data_value",
  89                 .addr =         10,
  90                 .width =        32,
  91         },
  92         [EICE_W0_DATA_MASK] = {
  93                 .name =         "watch_0_data_mask",
  94                 .addr =         11,
  95                 .width =        32,
  96         },
  97         [EICE_W0_CONTROL_VALUE] = {
  98                 .name =         "watch_0_control_value",
  99                 .addr =         12,
 100                 .width =        9,
 101         },
 102         [EICE_W0_CONTROL_MASK] = {
 103                 .name =         "watch_0_control_mask",
 104                 .addr =         13,
 105                 .width =        8,
 106         },
 107         [EICE_W1_ADDR_VALUE] = {
 108                 .name =         "watch_1_addr_value",
 109                 .addr =         16,
 110                 .width =        32,
 111         },
 112         [EICE_W1_ADDR_MASK] = {
 113                 .name =         "watch_1_addr_mask",
 114                 .addr =         17,
 115                 .width =        32,
 116         },
 117         [EICE_W1_DATA_VALUE] = {
 118                 .name =         "watch_1_data_value",
 119                 .addr =         18,
 120                 .width =        32,
 121         },
 122         [EICE_W1_DATA_MASK] = {
 123                 .name =         "watch_1_data_mask",
 124                 .addr =         19,
 125                 .width =        32,
 126         },
 127         [EICE_W1_CONTROL_VALUE] = {
 128                 .name =         "watch_1_control_value",
 129                 .addr =         20,
 130                 .width =        9,
 131         },
 132         [EICE_W1_CONTROL_MASK] = {
 133                 .name =         "watch_1_control_mask",
 134                 .addr =         21,
 135                 .width =        8,
 136         },
 137         /* vector_catch isn't always present */
 138         [EICE_VEC_CATCH] = {
 139                 .name =         "vector_catch",
 140                 .addr =         2,
 141                 .width =        8,
 142         },
 143 };
 144
 145
 146 static int embeddedice_get_reg(struct reg *reg)
 147 {
 148         int retval;
 149
 150         if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
 151                 LOG_ERROR("error queueing EmbeddedICE register read");
 152         else if ((retval = jtag_execute_queue()) != ERROR_OK)
 153                 LOG_ERROR("EmbeddedICE register read failed");
 154
 155         return retval;
 156 }
 157
 158 static const struct reg_arch_type eice_reg_type = {
 159         .get = embeddedice_get_reg,
 160         .set = embeddedice_set_reg_w_exec,
 161 };
 162
 163 /**
 164  * Probe EmbeddedICE module and set up local records of its registers.
 165  * Different versions of the modules have different capabilities, such as
 166  * hardware support for vector_catch, single stepping, and monitor mode.
 167  */
 168 struct reg_cache *
 169 embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
 170 {
 171         int retval;
 172         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 173         struct reg *reg_list = NULL;
 174         struct embeddedice_reg *arch_info = NULL;
 175         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 176         int num_regs = ARRAY_SIZE(eice_regs);
 177         int i;
 178         int eice_version = 0;
 179
 180         /* vector_catch isn't always present */
 181         if (!arm7_9->has_vector_catch)
 182                 num_regs--;
 183
 184         /* the actual registers are kept in two arrays */
 185         reg_list = calloc(num_regs, sizeof(struct reg));
 186         arch_info = calloc(num_regs, sizeof(struct embeddedice_reg));
 187
 188         /* fill in values for the reg cache */
 189         reg_cache->name = "EmbeddedICE registers";
 190         reg_cache->next = NULL;
 191         reg_cache->reg_list = reg_list;
 192         reg_cache->num_regs = num_regs;
 193
 194         /* set up registers */
 195         for (i = 0; i < num_regs; i++)
 196         {
 197                 reg_list[i].name = eice_regs[i].name;
 198                 reg_list[i].size = eice_regs[i].width;
 199                 reg_list[i].dirty = 0;
 200                 reg_list[i].valid = 0;
 201                 reg_list[i].value = calloc(1, 4);
 202                 reg_list[i].arch_info = &arch_info[i];
 203                 reg_list[i].type = &eice_reg_type;
 204                 arch_info[i].addr = eice_regs[i].addr;
 205                 arch_info[i].jtag_info = jtag_info;
 206         }
 207
 208         /* identify EmbeddedICE version by reading DCC control register */
 209         embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
 210         if ((retval = jtag_execute_queue()) != ERROR_OK)
 211         {
 212                 for (i = 0; i < num_regs; i++)
 213                 {
 214                         free(reg_list[i].value);
 215                 }
 216                 free(reg_list);
 217                 free(reg_cache);
 218                 free(arch_info);
 219                 return NULL;
 220         }
 221
 222         eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
 223         LOG_INFO("Embedded ICE version %d", eice_version);
 224
 225         switch (eice_version)
 226         {
 227                 case 1:
 228                         /* ARM7TDMI r3, ARM7TDMI-S r3
 229                          *
 230                          * REVISIT docs say ARM7TDMI-S r4 uses version 1 but
 231                          * that it has 6-bit CTRL and 5-bit STAT... doc bug?
 232                          * ARM7TDMI r4 docs say EICE v4.
 233                          */
 234                         reg_list[EICE_DBG_CTRL].size = 3;
 235                         reg_list[EICE_DBG_STAT].size = 5;
 236                         break;
 237                 case 2:
 238                         /* ARM9TDMI */
 239                         reg_list[EICE_DBG_CTRL].size = 4;
 240                         reg_list[EICE_DBG_STAT].size = 5;
 241                         arm7_9->has_single_step = 1;
 242                         break;
 243                 case 3:
 244                         LOG_ERROR("EmbeddedICE v%d handling might be broken",
 245                                         eice_version);
 246                         reg_list[EICE_DBG_CTRL].size = 6;
 247                         reg_list[EICE_DBG_STAT].size = 5;
 248                         arm7_9->has_single_step = 1;
 249                         arm7_9->has_monitor_mode = 1;
 250                         break;
 251                 case 4:
 252                         /* ARM7TDMI r4 */
 253                         reg_list[EICE_DBG_CTRL].size = 6;
 254                         reg_list[EICE_DBG_STAT].size = 5;
 255                         arm7_9->has_monitor_mode = 1;
 256                         break;
 257                 case 5:
 258                         /* ARM9E-S rev 1 */
 259                         reg_list[EICE_DBG_CTRL].size = 6;
 260                         reg_list[EICE_DBG_STAT].size = 5;
 261                         arm7_9->has_single_step = 1;
 262                         arm7_9->has_monitor_mode = 1;
 263                         break;
 264                 case 6:
 265                         /* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */
 266                         reg_list[EICE_DBG_CTRL].size = 6;
 267                         reg_list[EICE_DBG_STAT].size = 10;
 268                         /* DBG_STAT has MOE bits */
 269                         arm7_9->has_monitor_mode = 1;
 270                         break;
 271                 case 7:
 272                         LOG_ERROR("EmbeddedICE v%d handling might be broken",
 273                                         eice_version);
 274                         reg_list[EICE_DBG_CTRL].size = 6;
 275                         reg_list[EICE_DBG_STAT].size = 5;
 276                         arm7_9->has_monitor_mode = 1;
 277                         break;
 278                 default:
 279                         /*
 280                          * The Feroceon implementation has the version number
 281                          * in some unusual bits.  Let feroceon.c validate it
 282                          * and do the appropriate setup itself.
 283                          */
 284                         if (strcmp(target_type_name(target), "feroceon") == 0 ||
 285                             strcmp(target_type_name(target), "dragonite") == 0)
 286                                 break;
 287                         LOG_ERROR("unknown EmbeddedICE version "
 288                                 "(comms ctrl: 0x%8.8" PRIx32 ")",
 289                                 buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 290         }
 291
 292         LOG_INFO("%s: hardware has 2 breakpoints or watchpoints",
 293                         target_name(target));
 294
 295         return reg_cache;
 296 }
 297
 298 /**
 299  * Initialize EmbeddedICE module, if needed.
 300  */
 301 int embeddedice_setup(struct target *target)
 302 {
 303         int retval;
 304         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 305
 306         /* Explicitly disable monitor mode.  For now we only support halting
 307          * debug ... we don't know how to talk with a resident debug monitor
 308          * that manages break requests.  ARM's "Angel Debug Monitor" is one
 309          * common example of such code.
 310          */
 311         if (arm7_9->has_monitor_mode)
 312         {
 313                 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 314
 315                 embeddedice_read_reg(dbg_ctrl);
 316                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 317                         return retval;
 318                 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
 319                 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
 320         }
 321         return jtag_execute_queue();
 322 }
 323
 324 /**
 325  * Queue a read for an EmbeddedICE register into the register cache,
 326  * optionally checking the value read.
 327  * Note that at this level, all registers are 32 bits wide.
 328  */
 329 int embeddedice_read_reg_w_check(struct reg *reg,
 330                 uint8_t *check_value, uint8_t *check_mask)
 331 {
 332         struct embeddedice_reg *ice_reg = reg->arch_info;
 333         uint8_t reg_addr = ice_reg->addr & 0x1f;
 334         struct scan_field fields[3];
 335         uint8_t field1_out[1];
 336         uint8_t field2_out[1];
 337
 338         jtag_set_end_state(TAP_IDLE);
 339         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 340
 341         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 342
 343         /* bits 31:0 -- data (ignored here) */
 344         fields[0].tap = ice_reg->jtag_info->tap;
 345         fields[0].num_bits = 32;
 346         fields[0].out_value = reg->value;
 347         fields[0].in_value = NULL;
 348         fields[0].check_value = NULL;
 349         fields[0].check_mask = NULL;
 350
 351         /* bits 36:32 -- register */
 352         fields[1].tap = ice_reg->jtag_info->tap;
 353         fields[1].num_bits = 5;
 354         fields[1].out_value = field1_out;
 355         fields[1].out_value[0] = reg_addr;
 356         fields[1].in_value = NULL;
 357         fields[1].check_value = NULL;
 358         fields[1].check_mask = NULL;
 359
 360         /* bit 37 -- 0/read */
 361         fields[2].tap = ice_reg->jtag_info->tap;
 362         fields[2].num_bits = 1;
 363         fields[2].out_value = field2_out;
 364         fields[2].out_value[0] = 0;
 365         fields[2].in_value = NULL;
 366         fields[2].check_value = NULL;
 367         fields[2].check_mask = NULL;
 368
 369         /* traverse Update-DR, setting address for the next read */
 370         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 371
 372         /* bits 31:0 -- the data we're reading (and maybe checking) */
 373         fields[0].in_value = reg->value;
 374         fields[0].check_value = check_value;
 375         fields[0].check_mask = check_mask;
 376
 377         /* when reading the DCC data register, leaving the address field set to
 378          * EICE_COMMS_DATA would read the register twice
 379          * reading the control register is safe
 380          */
 381         fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
 382
 383         /* traverse Update-DR, reading but with no other side effects */
 384         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 385
 386         return ERROR_OK;
 387 }
 388
 389 /**
 390  * Receive a block of size 32-bit words from the DCC.
 391  * We assume the target is always going to be fast enough (relative to
 392  * the JTAG clock) that the debugger won't need to poll the handshake
 393  * bit.  The JTAG clock is usually at least six times slower than the
 394  * functional clock, so the 50+ JTAG clocks needed to receive the word
 395  * allow hundreds of instruction cycles (per word) in the target.
 396  */
 397 int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 398 {
 399         struct scan_field fields[3];
 400         uint8_t field1_out[1];
 401         uint8_t field2_out[1];
 402
 403         jtag_set_end_state(TAP_IDLE);
 404         arm_jtag_scann(jtag_info, 0x2);
 405         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 406
 407         fields[0].tap = jtag_info->tap;
 408         fields[0].num_bits = 32;
 409         fields[0].out_value = NULL;
 410         fields[0].in_value = NULL;
 411
 412         fields[1].tap = jtag_info->tap;
 413         fields[1].num_bits = 5;
 414         fields[1].out_value = field1_out;
 415         fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
 416         fields[1].in_value = NULL;
 417
 418         fields[2].tap = jtag_info->tap;
 419         fields[2].num_bits = 1;
 420         fields[2].out_value = field2_out;
 421         fields[2].out_value[0] = 0;
 422         fields[2].in_value = NULL;
 423
 424         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 425
 426         while (size > 0)
 427         {
 428                 /* when reading the last item, set the register address to the DCC control reg,
 429                  * to avoid reading additional data from the DCC data reg
 430                  */
 431                 if (size == 1)
 432                         fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
 433
 434                 fields[0].in_value = (uint8_t *)data;
 435                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 436                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data);
 437
 438                 data++;
 439                 size--;
 440         }
 441
 442         return jtag_execute_queue();
 443 }
 444
 445 /**
 446  * Queue a read for an EmbeddedICE register into the register cache,
 447  * not checking the value read.
 448  */
 449 int embeddedice_read_reg(struct reg *reg)
 450 {
 451         return embeddedice_read_reg_w_check(reg, NULL, NULL);
 452 }
 453
 454 /**
 455  * Queue a write for an EmbeddedICE register, updating the register cache.
 456  * Uses embeddedice_write_reg().
 457  */
 458 void embeddedice_set_reg(struct reg *reg, uint32_t value)
 459 {
 460         embeddedice_write_reg(reg, value);
 461
 462         buf_set_u32(reg->value, 0, reg->size, value);
 463         reg->valid = 1;
 464         reg->dirty = 0;
 465
 466 }
 467
 468 /**
 469  * Write an EmbeddedICE register, updating the register cache.
 470  * Uses embeddedice_set_reg(); not queued.
 471  */
 472 int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 473 {
 474         int retval;
 475
 476         embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 477         if ((retval = jtag_execute_queue()) != ERROR_OK)
 478                 LOG_ERROR("register write failed");
 479         return retval;
 480 }
 481
 482 /**
 483  * Queue a write for an EmbeddedICE register, bypassing the register cache.
 484  */
 485 void embeddedice_write_reg(struct reg *reg, uint32_t value)
 486 {
 487         struct embeddedice_reg *ice_reg = reg->arch_info;
 488
 489         LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 490
 491         jtag_set_end_state(TAP_IDLE);
 492         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 493
 494         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 495
 496         uint8_t reg_addr = ice_reg->addr & 0x1f;
 497         embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
 498 }
 499
 500 /**
 501  * Queue a write for an EmbeddedICE register, using cached value.
 502  * Uses embeddedice_write_reg().
 503  */
 504 void embeddedice_store_reg(struct reg *reg)
 505 {
 506         embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 507 }
 508
 509 /**
 510  * Send a block of size 32-bit words to the DCC.
 511  * We assume the target is always going to be fast enough (relative to
 512  * the JTAG clock) that the debugger won't need to poll the handshake
 513  * bit.  The JTAG clock is usually at least six times slower than the
 514  * functional clock, so the 50+ JTAG clocks needed to receive the word
 515  * allow hundreds of instruction cycles (per word) in the target.
 516  */
 517 int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 518 {
 519         struct scan_field fields[3];
 520         uint8_t field0_out[4];
 521         uint8_t field1_out[1];
 522         uint8_t field2_out[1];
 523
 524         jtag_set_end_state(TAP_IDLE);
 525         arm_jtag_scann(jtag_info, 0x2);
 526         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 527
 528         fields[0].tap = jtag_info->tap;
 529         fields[0].num_bits = 32;
 530         fields[0].out_value = field0_out;
 531         fields[0].in_value = NULL;
 532
 533         fields[1].tap = jtag_info->tap;
 534         fields[1].num_bits = 5;
 535         fields[1].out_value = field1_out;
 536         fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
 537         fields[1].in_value = NULL;
 538
 539         fields[2].tap = jtag_info->tap;
 540         fields[2].num_bits = 1;
 541         fields[2].out_value = field2_out;
 542         fields[2].out_value[0] = 1;
 543
 544         fields[2].in_value = NULL;
 545
 546         while (size > 0)
 547         {
 548                 buf_set_u32(fields[0].out_value, 0, 32, *data);
 549                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 550
 551                 data++;
 552                 size--;
 553         }
 554
 555         /* call to jtag_execute_queue() intentionally omitted */
 556         return ERROR_OK;
 557 }
 558
 559 /**
 560  * Poll DCC control register until read or write handshake completes.
 561  */
 562 int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout)
 563 {
 564         struct scan_field fields[3];
 565         uint8_t field0_in[4];
 566         uint8_t field1_out[1];
 567         uint8_t field2_out[1];
 568         int retval;
 569         uint32_t hsact;
 570         struct timeval lap;
 571         struct timeval now;
 572
 573         if (hsbit == EICE_COMM_CTRL_WBIT)
 574                 hsact = 1;
 575         else if (hsbit == EICE_COMM_CTRL_RBIT)
 576                 hsact = 0;
 577         else
 578                 return ERROR_INVALID_ARGUMENTS;
 579
 580         jtag_set_end_state(TAP_IDLE);
 581         arm_jtag_scann(jtag_info, 0x2);
 582         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 583
 584         fields[0].tap = jtag_info->tap;
 585         fields[0].num_bits = 32;
 586         fields[0].out_value = NULL;
 587         fields[0].in_value = field0_in;
 588
 589         fields[1].tap = jtag_info->tap;
 590         fields[1].num_bits = 5;
 591         fields[1].out_value = field1_out;
 592         fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
 593         fields[1].in_value = NULL;
 594
 595         fields[2].tap = jtag_info->tap;
 596         fields[2].num_bits = 1;
 597         fields[2].out_value = field2_out;
 598         fields[2].out_value[0] = 0;
 599         fields[2].in_value = NULL;
 600
 601         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 602         gettimeofday(&lap, NULL);
 603         do {
 604                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 605                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 606                         return retval;
 607
 608                 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
 609                         return ERROR_OK;
 610
 611                 gettimeofday(&now, NULL);
 612         } while ((uint32_t)((now.tv_sec - lap.tv_sec) * 1000
 613                         + (now.tv_usec - lap.tv_usec) / 1000) <= timeout);
 614
 615         return ERROR_TARGET_TIMEOUT;
 616 }
 617
 618 #ifndef HAVE_JTAG_MINIDRIVER_H
 619 /**
 620  * This is an inner loop of the open loop DCC write of data to target
 621  */
 622 void embeddedice_write_dcc(struct jtag_tap *tap,
 623                 int reg_addr, uint8_t *buffer, int little, int count)
 624 {
 625         int i;
 626
 627         for (i = 0; i < count; i++)
 628         {
 629                 embeddedice_write_reg_inner(tap, reg_addr,
 630                                 fast_target_buffer_get_u32(buffer, little));
 631                 buffer += 4;
 632         }
 633 }
 634 #else
 635 /* provided by minidriver */
 636 #endif