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   1 /***************************************************************************\r
   2  *   Copyright (C) 2005 by Dominic Rath                                    *\r
   3  *   Dominic.Rath@gmx.de                                                   *\r
   4  *                                                                         *\r
   5  *   This program is free software; you can redistribute it and/or modify  *\r
   6  *   it under the terms of the GNU General Public License as published by  *\r
   7  *   the Free Software Foundation; either version 2 of the License, or     *\r
   8  *   (at your option) any later version.                                   *\r
   9  *                                                                         *\r
  10  *   This program is distributed in the hope that it will be useful,       *\r
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\r
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\r
  13  *   GNU General Public License for more details.                          *\r
  14  *                                                                         *\r
  15  *   You should have received a copy of the GNU General Public License     *\r
  16  *   along with this program; if not, write to the                         *\r
  17  *   Free Software Foundation, Inc.,                                       *\r
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\r
  19  ***************************************************************************/\r
  20 #ifdef HAVE_CONFIG_H\r
  21 #include "config.h"\r
  22 #endif\r
  23 \r
  24 #include "embeddedice.h"\r
  25 \r
  26 #include "armv4_5.h"\r
  27 #include "arm7_9_common.h"\r
  28 \r
  29 #include "log.h"\r
  30 #include "arm_jtag.h"\r
  31 #include "types.h"\r
  32 #include "binarybuffer.h"\r
  33 #include "target.h"\r
  34 #include "register.h"\r
  35 #include "jtag.h"\r
  36 \r
  37 #include <stdlib.h>\r
  38 \r
  39 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] = \r
  40 {\r
  41         {"R", 1},\r
  42         {"W", 1},\r
  43         {"reserved", 26},\r
  44         {"version", 4}\r
  45 };\r
  46 \r
  47 int embeddedice_reg_arch_info[] =\r
  48 {\r
  49         0x0, 0x1, 0x4, 0x5,\r
  50         0x8, 0x9, 0xa, 0xb, 0xc, 0xd,\r
  51         0x10, 0x11, 0x12, 0x13, 0x14, 0x15,\r
  52         0x2\r
  53 };\r
  54 \r
  55 char* embeddedice_reg_list[] =\r
  56 {\r
  57         "debug_ctrl",\r
  58         "debug_status",\r
  59         \r
  60         "comms_ctrl",\r
  61         "comms_data",\r
  62         \r
  63         "watch 0 addr value",\r
  64         "watch 0 addr mask",\r
  65         "watch 0 data value",\r
  66         "watch 0 data mask",\r
  67         "watch 0 control value",\r
  68         "watch 0 control mask",\r
  69         \r
  70         "watch 1 addr value",\r
  71         "watch 1 addr mask",\r
  72         "watch 1 data value",\r
  73         "watch 1 data mask",\r
  74         "watch 1 control value",\r
  75         "watch 1 control mask",\r
  76         \r
  77         "vector catch"\r
  78 };\r
  79 \r
  80 int embeddedice_reg_arch_type = -1;\r
  81 \r
  82 int embeddedice_get_reg(reg_t *reg);\r
  83 int embeddedice_set_reg(reg_t *reg, u32 value);\r
  84 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);\r
  85 \r
  86 int embeddedice_write_reg(reg_t *reg, u32 value);\r
  87 int embeddedice_read_reg(reg_t *reg);\r
  88 \r
  89 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)\r
  90 {\r
  91         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));\r
  92         reg_t *reg_list = NULL;\r
  93         embeddedice_reg_t *arch_info = NULL;\r
  94         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
  95         int num_regs;\r
  96         int i;\r
  97         int eice_version = 0;\r
  98         \r
  99         /* register a register arch-type for EmbeddedICE registers only once */\r
 100         if (embeddedice_reg_arch_type == -1)\r
 101                 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);\r
 102         \r
 103         if (arm7_9->has_vector_catch)\r
 104                 num_regs = 17;\r
 105         else\r
 106                 num_regs = 16;\r
 107                 \r
 108         /* the actual registers are kept in two arrays */\r
 109         reg_list = calloc(num_regs, sizeof(reg_t));\r
 110         arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));\r
 111         \r
 112         /* fill in values for the reg cache */\r
 113         reg_cache->name = "EmbeddedICE registers";\r
 114         reg_cache->next = NULL;\r
 115         reg_cache->reg_list = reg_list;\r
 116         reg_cache->num_regs = num_regs;\r
 117         \r
 118         /* set up registers */\r
 119         for (i = 0; i < num_regs; i++)\r
 120         {\r
 121                 reg_list[i].name = embeddedice_reg_list[i];\r
 122                 reg_list[i].size = 32;\r
 123                 reg_list[i].dirty = 0;\r
 124                 reg_list[i].valid = 0;\r
 125                 reg_list[i].bitfield_desc = NULL;\r
 126                 reg_list[i].num_bitfields = 0;\r
 127                 reg_list[i].value = calloc(1, 4);\r
 128                 reg_list[i].arch_info = &arch_info[i];\r
 129                 reg_list[i].arch_type = embeddedice_reg_arch_type;\r
 130                 arch_info[i].addr = embeddedice_reg_arch_info[i];\r
 131                 arch_info[i].jtag_info = jtag_info;\r
 132         }\r
 133         \r
 134         /* identify EmbeddedICE version by reading DCC control register */\r
 135         embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);\r
 136         jtag_execute_queue();\r
 137         \r
 138         eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);\r
 139         \r
 140         switch (eice_version)\r
 141         {\r
 142                 case 1:\r
 143                         reg_list[EICE_DBG_CTRL].size = 3;\r
 144                         reg_list[EICE_DBG_STAT].size = 5;\r
 145                         break;\r
 146                 case 2:\r
 147                         reg_list[EICE_DBG_CTRL].size = 4;\r
 148                         reg_list[EICE_DBG_STAT].size = 5;\r
 149                         arm7_9->has_single_step = 1;\r
 150                         break;\r
 151                 case 3:\r
 152                         ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken"); \r
 153                         reg_list[EICE_DBG_CTRL].size = 6;\r
 154                         reg_list[EICE_DBG_STAT].size = 5;\r
 155                         arm7_9->has_single_step = 1;\r
 156                         arm7_9->has_monitor_mode = 1;\r
 157                         break;\r
 158                 case 4:\r
 159                         reg_list[EICE_DBG_CTRL].size = 6;\r
 160                         reg_list[EICE_DBG_STAT].size = 5;\r
 161                         arm7_9->has_monitor_mode = 1;\r
 162                         break;\r
 163                 case 5:\r
 164                         reg_list[EICE_DBG_CTRL].size = 6;\r
 165                         reg_list[EICE_DBG_STAT].size = 5;\r
 166                         arm7_9->has_single_step = 1;\r
 167                         arm7_9->has_monitor_mode = 1;\r
 168                         break;\r
 169                 case 6:\r
 170                         reg_list[EICE_DBG_CTRL].size = 6;\r
 171                         reg_list[EICE_DBG_STAT].size = 10;\r
 172                         arm7_9->has_monitor_mode = 1;\r
 173                         break;\r
 174                 case 7:\r
 175                         WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");\r
 176                         reg_list[EICE_DBG_CTRL].size = 6;\r
 177                         reg_list[EICE_DBG_STAT].size = 5;\r
 178                         arm7_9->has_monitor_mode = 1;\r
 179                         break;\r
 180                 default:\r
 181                         ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));\r
 182         }\r
 183         \r
 184         /* explicitly disable monitor mode */\r
 185         if (arm7_9->has_monitor_mode)\r
 186         {\r
 187                 embeddedice_read_reg(&reg_list[EICE_DBG_CTRL]);\r
 188                 jtag_execute_queue();\r
 189                 buf_set_u32(reg_list[EICE_DBG_CTRL].value, 4, 1, 0);\r
 190                 embeddedice_set_reg_w_exec(&reg_list[EICE_DBG_CTRL], reg_list[EICE_DBG_CTRL].value);\r
 191         }\r
 192         \r
 193         return reg_cache;\r
 194 }\r
 195 \r
 196 int embeddedice_get_reg(reg_t *reg)\r
 197 {\r
 198         if (embeddedice_read_reg(reg) != ERROR_OK)\r
 199         {\r
 200                 ERROR("BUG: error scheduling EmbeddedICE register read");\r
 201                 exit(-1);\r
 202         }\r
 203         \r
 204         if (jtag_execute_queue() != ERROR_OK)\r
 205         {\r
 206                 ERROR("register read failed");\r
 207         }\r
 208         \r
 209         return ERROR_OK;\r
 210 }\r
 211 \r
 212 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)\r
 213 {\r
 214         embeddedice_reg_t *ice_reg = reg->arch_info;\r
 215         u8 reg_addr = ice_reg->addr & 0x1f;\r
 216         scan_field_t fields[3];\r
 217         u8 field1_out[1];\r
 218         u8 field2_out[1];\r
 219 \r
 220         DEBUG("%i", ice_reg->addr);\r
 221 \r
 222         jtag_add_end_state(TAP_RTI);\r
 223         arm_jtag_scann(ice_reg->jtag_info, 0x2);\r
 224         \r
 225         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);\r
 226         \r
 227         fields[0].device = ice_reg->jtag_info->chain_pos;\r
 228         fields[0].num_bits = 32;\r
 229         fields[0].out_value = reg->value;\r
 230         fields[0].out_mask = NULL;\r
 231         fields[0].in_value = NULL;\r
 232         fields[0].in_check_value = NULL;\r
 233         fields[0].in_check_mask = NULL;\r
 234         fields[0].in_handler = NULL;\r
 235         fields[0].in_handler_priv = NULL;\r
 236         \r
 237         fields[1].device = ice_reg->jtag_info->chain_pos;\r
 238         fields[1].num_bits = 5;\r
 239         fields[1].out_value = field1_out;\r
 240         buf_set_u32(fields[1].out_value, 0, 5, reg_addr);\r
 241         fields[1].out_mask = NULL;\r
 242         fields[1].in_value = NULL;\r
 243         fields[1].in_check_value = NULL;\r
 244         fields[1].in_check_mask = NULL;\r
 245         fields[1].in_handler = NULL;\r
 246         fields[1].in_handler_priv = NULL;\r
 247 \r
 248         fields[2].device = ice_reg->jtag_info->chain_pos;\r
 249         fields[2].num_bits = 1;\r
 250         fields[2].out_value = field2_out;\r
 251         buf_set_u32(fields[2].out_value, 0, 1, 0);\r
 252         fields[2].out_mask = NULL;\r
 253         fields[2].in_value = NULL;\r
 254         fields[2].in_check_value = NULL;\r
 255         fields[2].in_check_mask = NULL;\r
 256         fields[2].in_handler = NULL;\r
 257         fields[2].in_handler_priv = NULL;\r
 258         \r
 259         jtag_add_dr_scan(3, fields, -1);\r
 260         \r
 261         fields[0].in_value = reg->value;\r
 262         jtag_set_check_value(fields+0, check_value, check_mask, NULL);\r
 263         \r
 264         /* when reading the DCC data register, leaving the address field set to\r
 265          * EICE_COMMS_DATA would read the register twice\r
 266          * reading the control register is safe\r
 267          */\r
 268         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);\r
 269         \r
 270         jtag_add_dr_scan(3, fields, -1);\r
 271 \r
 272         return ERROR_OK;\r
 273 }\r
 274 \r
 275 /* receive <size> words of 32 bit from the DCC\r
 276  * we pretend the target is always going to be fast enough\r
 277  * (relative to the JTAG clock), so we don't need to handshake\r
 278  */\r
 279 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)\r
 280 {\r
 281         scan_field_t fields[3];\r
 282         u8 field1_out[1];\r
 283         u8 field2_out[1];\r
 284 \r
 285         jtag_add_end_state(TAP_RTI);\r
 286         arm_jtag_scann(jtag_info, 0x2);\r
 287         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
 288         \r
 289         fields[0].device = jtag_info->chain_pos;\r
 290         fields[0].num_bits = 32;\r
 291         fields[0].out_value = NULL;\r
 292         fields[0].out_mask = NULL;\r
 293         fields[0].in_value = NULL;\r
 294         fields[0].in_check_value = NULL;\r
 295         fields[0].in_check_mask = NULL;\r
 296         fields[0].in_handler = NULL;\r
 297         fields[0].in_handler_priv = NULL;\r
 298         \r
 299         fields[1].device = jtag_info->chain_pos;\r
 300         fields[1].num_bits = 5;\r
 301         fields[1].out_value = field1_out;\r
 302         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);\r
 303         fields[1].out_mask = NULL;\r
 304         fields[1].in_value = NULL;\r
 305         fields[1].in_check_value = NULL;\r
 306         fields[1].in_check_mask = NULL;\r
 307         fields[1].in_handler = NULL;\r
 308         fields[1].in_handler_priv = NULL;\r
 309 \r
 310         fields[2].device = jtag_info->chain_pos;\r
 311         fields[2].num_bits = 1;\r
 312         fields[2].out_value = field2_out;\r
 313         buf_set_u32(fields[2].out_value, 0, 1, 0);\r
 314         fields[2].out_mask = NULL;\r
 315         fields[2].in_value = NULL;\r
 316         fields[2].in_check_value = NULL;\r
 317         fields[2].in_check_mask = NULL;\r
 318         fields[2].in_handler = NULL;\r
 319         fields[2].in_handler_priv = NULL;\r
 320         \r
 321         jtag_add_dr_scan(3, fields, -1);\r
 322         \r
 323         while (size > 0)\r
 324         {\r
 325                 /* when reading the last item, set the register address to the DCC control reg,\r
 326                  * to avoid reading additional data from the DCC data reg\r
 327                  */\r
 328                 if (size == 1)\r
 329                         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);\r
 330                 \r
 331                 fields[0].in_handler = arm_jtag_buf_to_u32;\r
 332                 fields[0].in_handler_priv = data;\r
 333                 jtag_add_dr_scan(3, fields, -1);\r
 334                 \r
 335                 data++;\r
 336                 size--;\r
 337         }\r
 338         \r
 339         return jtag_execute_queue();\r
 340 }\r
 341 \r
 342 int embeddedice_read_reg(reg_t *reg)\r
 343 {\r
 344         return embeddedice_read_reg_w_check(reg, NULL, NULL);   \r
 345 }\r
 346 \r
 347 int embeddedice_set_reg(reg_t *reg, u32 value)\r
 348 {\r
 349         if (embeddedice_write_reg(reg, value) != ERROR_OK)\r
 350         {\r
 351                 ERROR("BUG: error scheduling EmbeddedICE register write");\r
 352                 exit(-1);\r
 353         }\r
 354         \r
 355         buf_set_u32(reg->value, 0, reg->size, value);\r
 356         reg->valid = 1;\r
 357         reg->dirty = 0;\r
 358         \r
 359         return ERROR_OK;\r
 360 }\r
 361 \r
 362 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)\r
 363 {\r
 364         embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));\r
 365         \r
 366         if (jtag_execute_queue() != ERROR_OK)\r
 367         {\r
 368                 ERROR("register write failed");\r
 369                 exit(-1);\r
 370         }\r
 371         return ERROR_OK;\r
 372 }\r
 373 \r
 374 int embeddedice_write_reg(reg_t *reg, u32 value)\r
 375 {\r
 376         embeddedice_reg_t *ice_reg = reg->arch_info;\r
 377         u8 reg_addr = ice_reg->addr & 0x1f;\r
 378         scan_field_t fields[3];\r
 379         u8 field0_out[4];\r
 380         u8 field1_out[1];\r
 381         u8 field2_out[1];\r
 382 \r
 383         DEBUG("%i: 0x%8.8x", ice_reg->addr, value);\r
 384         \r
 385         jtag_add_end_state(TAP_RTI);\r
 386         arm_jtag_scann(ice_reg->jtag_info, 0x2);\r
 387         \r
 388         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);\r
 389         \r
 390         fields[0].device = ice_reg->jtag_info->chain_pos;\r
 391         fields[0].num_bits = 32;\r
 392         fields[0].out_value = field0_out;\r
 393         buf_set_u32(fields[0].out_value, 0, 32, value);\r
 394         fields[0].out_mask = NULL;\r
 395         fields[0].in_value = NULL;\r
 396         fields[0].in_check_value = NULL;\r
 397         fields[0].in_check_mask = NULL;\r
 398         fields[0].in_handler = NULL;\r
 399         fields[0].in_handler_priv = NULL;\r
 400         \r
 401         fields[1].device = ice_reg->jtag_info->chain_pos;\r
 402         fields[1].num_bits = 5;\r
 403         fields[1].out_value = field1_out;\r
 404         buf_set_u32(fields[1].out_value, 0, 5, reg_addr);\r
 405         fields[1].out_mask = NULL;\r
 406         fields[1].in_value = NULL;\r
 407         fields[1].in_check_value = NULL;\r
 408         fields[1].in_check_mask = NULL;\r
 409         fields[1].in_handler = NULL;\r
 410         fields[1].in_handler_priv = NULL;\r
 411 \r
 412         fields[2].device = ice_reg->jtag_info->chain_pos;\r
 413         fields[2].num_bits = 1;\r
 414         fields[2].out_value = field2_out;\r
 415         buf_set_u32(fields[2].out_value, 0, 1, 1);\r
 416         fields[2].out_mask = NULL;\r
 417         fields[2].in_value = NULL;\r
 418         fields[2].in_check_value = NULL;\r
 419         fields[2].in_check_mask = NULL;\r
 420         fields[2].in_handler = NULL;\r
 421         fields[2].in_handler_priv = NULL;\r
 422         \r
 423         jtag_add_dr_scan(3, fields, -1);\r
 424         \r
 425         return ERROR_OK;\r
 426 }\r
 427 \r
 428 int embeddedice_store_reg(reg_t *reg)\r
 429 {\r
 430         return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));\r
 431 }\r
 432 \r
 433 /* send <size> words of 32 bit to the DCC\r
 434  * we pretend the target is always going to be fast enough\r
 435  * (relative to the JTAG clock), so we don't need to handshake\r
 436  */\r
 437 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)\r
 438 {\r
 439         scan_field_t fields[3];\r
 440         u8 field0_out[4];\r
 441         u8 field1_out[1];\r
 442         u8 field2_out[1];\r
 443 \r
 444         jtag_add_end_state(TAP_RTI);\r
 445         arm_jtag_scann(jtag_info, 0x2);\r
 446         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
 447 \r
 448         fields[0].device = jtag_info->chain_pos;\r
 449         fields[0].num_bits = 32;\r
 450         fields[0].out_value = field0_out;\r
 451         fields[0].out_mask = NULL;\r
 452         fields[0].in_value = NULL;\r
 453         fields[0].in_check_value = NULL;\r
 454         fields[0].in_check_mask = NULL;\r
 455         fields[0].in_handler = NULL;\r
 456         fields[0].in_handler_priv = NULL;\r
 457 \r
 458         fields[1].device = jtag_info->chain_pos;\r
 459         fields[1].num_bits = 5;\r
 460         fields[1].out_value = field1_out;\r
 461         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);\r
 462         fields[1].out_mask = NULL;\r
 463         fields[1].in_value = NULL;\r
 464         fields[1].in_check_value = NULL;\r
 465         fields[1].in_check_mask = NULL;\r
 466         fields[1].in_handler = NULL;\r
 467         fields[1].in_handler_priv = NULL;\r
 468 \r
 469         fields[2].device = jtag_info->chain_pos;\r
 470         fields[2].num_bits = 1;\r
 471         fields[2].out_value = field2_out;\r
 472         buf_set_u32(fields[2].out_value, 0, 1, 1);\r
 473         fields[2].out_mask = NULL;\r
 474         fields[2].in_value = NULL;\r
 475         fields[2].in_check_value = NULL;\r
 476         fields[2].in_check_mask = NULL;\r
 477         fields[2].in_handler = NULL;\r
 478         fields[2].in_handler_priv = NULL;\r
 479 \r
 480         while (size > 0)\r
 481         {\r
 482                 buf_set_u32(fields[0].out_value, 0, 32, *data);\r
 483                 jtag_add_dr_scan(3, fields, -1);\r
 484 \r
 485                 data++;\r
 486                 size--;\r
 487         }\r
 488 \r
 489         /* call to jtag_execute_queue() intentionally omitted */\r
 490         return ERROR_OK;\r
 491 }\r
 492 \r
 493 /* wait for DCC control register R/W handshake bit to become active\r
 494  */\r
 495 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)\r
 496 {\r
 497         scan_field_t fields[3];\r
 498         u8 field0_in[4];\r
 499         u8 field1_out[1];\r
 500         u8 field2_out[1];\r
 501         int retval;\r
 502         int hsact;\r
 503         struct timeval lap;\r
 504         struct timeval now;\r
 505 \r
 506         if (hsbit == EICE_COMM_CTRL_WBIT)\r
 507                 hsact = 1;\r
 508         else if (hsbit == EICE_COMM_CTRL_RBIT)\r
 509                 hsact = 0;\r
 510         else\r
 511                 return ERROR_INVALID_ARGUMENTS;\r
 512 \r
 513         jtag_add_end_state(TAP_RTI);\r
 514         arm_jtag_scann(jtag_info, 0x2);\r
 515         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
 516 \r
 517         fields[0].device = jtag_info->chain_pos;\r
 518         fields[0].num_bits = 32;\r
 519         fields[0].out_value = NULL;\r
 520         fields[0].out_mask = NULL;\r
 521         fields[0].in_value = field0_in;\r
 522         fields[0].in_check_value = NULL;\r
 523         fields[0].in_check_mask = NULL;\r
 524         fields[0].in_handler = NULL;\r
 525         fields[0].in_handler_priv = NULL;\r
 526 \r
 527         fields[1].device = jtag_info->chain_pos;\r
 528         fields[1].num_bits = 5;\r
 529         fields[1].out_value = field1_out;\r
 530         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);\r
 531         fields[1].out_mask = NULL;\r
 532         fields[1].in_value = NULL;\r
 533         fields[1].in_check_value = NULL;\r
 534         fields[1].in_check_mask = NULL;\r
 535         fields[1].in_handler = NULL;\r
 536         fields[1].in_handler_priv = NULL;\r
 537 \r
 538         fields[2].device = jtag_info->chain_pos;\r
 539         fields[2].num_bits = 1;\r
 540         fields[2].out_value = field2_out;\r
 541         buf_set_u32(fields[2].out_value, 0, 1, 0);\r
 542         fields[2].out_mask = NULL;\r
 543         fields[2].in_value = NULL;\r
 544         fields[2].in_check_value = NULL;\r
 545         fields[2].in_check_mask = NULL;\r
 546         fields[2].in_handler = NULL;\r
 547         fields[2].in_handler_priv = NULL;\r
 548 \r
 549         jtag_add_dr_scan(3, fields, -1);\r
 550         gettimeofday(&lap, NULL);\r
 551         do\r
 552         {\r
 553                 jtag_add_dr_scan(3, fields, -1);\r
 554                 if ((retval = jtag_execute_queue()) != ERROR_OK)\r
 555                         return retval;\r
 556 \r
 557                 if (buf_get_u32(field0_in, hsbit, 1) == hsact)\r
 558                         return ERROR_OK;\r
 559 \r
 560                 gettimeofday(&now, NULL);\r
 561         }\r
 562         while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout);\r
 563 \r
 564         return ERROR_TARGET_TIMEOUT;\r
 565 }\r