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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "embeddedice.h"
  31
  32
  33 #if 0
  34 static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
  35 {
  36         {"R", 1},
  37         {"W", 1},
  38         {"reserved", 26},
  39         {"version", 4}
  40 };
  41 #endif
  42
  43 static int embeddedice_reg_arch_info[] =
  44 {
  45         0x0, 0x1, 0x4, 0x5,
  46         0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
  47         0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
  48         0x2
  49 };
  50
  51 static char* embeddedice_reg_list[] =
  52 {
  53         "debug_ctrl",
  54         "debug_status",
  55
  56         "comms_ctrl",
  57         "comms_data",
  58
  59         "watch 0 addr value",
  60         "watch 0 addr mask",
  61         "watch 0 data value",
  62         "watch 0 data mask",
  63         "watch 0 control value",
  64         "watch 0 control mask",
  65
  66         "watch 1 addr value",
  67         "watch 1 addr mask",
  68         "watch 1 data value",
  69         "watch 1 data mask",
  70         "watch 1 control value",
  71         "watch 1 control mask",
  72
  73         "vector catch"
  74 };
  75
  76 static int embeddedice_reg_arch_type = -1;
  77
  78 static int embeddedice_get_reg(reg_t *reg);
  79
  80 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
  81 {
  82         int retval;
  83         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
  84         reg_t *reg_list = NULL;
  85         embeddedice_reg_t *arch_info = NULL;
  86         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  87         int num_regs;
  88         int i;
  89         int eice_version = 0;
  90
  91         /* register a register arch-type for EmbeddedICE registers only once */
  92         if (embeddedice_reg_arch_type == -1)
  93                 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
  94
  95         if (arm7_9->has_vector_catch)
  96                 num_regs = 17;
  97         else
  98                 num_regs = 16;
  99
 100         /* the actual registers are kept in two arrays */
 101         reg_list = calloc(num_regs, sizeof(reg_t));
 102         arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
 103
 104         /* fill in values for the reg cache */
 105         reg_cache->name = "EmbeddedICE registers";
 106         reg_cache->next = NULL;
 107         reg_cache->reg_list = reg_list;
 108         reg_cache->num_regs = num_regs;
 109
 110         /* set up registers */
 111         for (i = 0; i < num_regs; i++)
 112         {
 113                 reg_list[i].name = embeddedice_reg_list[i];
 114                 reg_list[i].size = 32;
 115                 reg_list[i].dirty = 0;
 116                 reg_list[i].valid = 0;
 117                 reg_list[i].bitfield_desc = NULL;
 118                 reg_list[i].num_bitfields = 0;
 119                 reg_list[i].value = calloc(1, 4);
 120                 reg_list[i].arch_info = &arch_info[i];
 121                 reg_list[i].arch_type = embeddedice_reg_arch_type;
 122                 arch_info[i].addr = embeddedice_reg_arch_info[i];
 123                 arch_info[i].jtag_info = jtag_info;
 124         }
 125
 126         /* identify EmbeddedICE version by reading DCC control register */
 127         embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
 128         if ((retval=jtag_execute_queue())!=ERROR_OK)
 129         {
 130                 for (i = 0; i < num_regs; i++)
 131                 {
 132                         free(reg_list[i].value);
 133                 }
 134                 free(reg_list);
 135                 free(arch_info);
 136                 return NULL;
 137         }
 138
 139         eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
 140
 141         switch (eice_version)
 142         {
 143                 case 1:
 144                         reg_list[EICE_DBG_CTRL].size = 3;
 145                         reg_list[EICE_DBG_STAT].size = 5;
 146                         break;
 147                 case 2:
 148                         reg_list[EICE_DBG_CTRL].size = 4;
 149                         reg_list[EICE_DBG_STAT].size = 5;
 150                         arm7_9->has_single_step = 1;
 151                         break;
 152                 case 3:
 153                         LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
 154                         reg_list[EICE_DBG_CTRL].size = 6;
 155                         reg_list[EICE_DBG_STAT].size = 5;
 156                         arm7_9->has_single_step = 1;
 157                         arm7_9->has_monitor_mode = 1;
 158                         break;
 159                 case 4:
 160                         reg_list[EICE_DBG_CTRL].size = 6;
 161                         reg_list[EICE_DBG_STAT].size = 5;
 162                         arm7_9->has_monitor_mode = 1;
 163                         break;
 164                 case 5:
 165                         reg_list[EICE_DBG_CTRL].size = 6;
 166                         reg_list[EICE_DBG_STAT].size = 5;
 167                         arm7_9->has_single_step = 1;
 168                         arm7_9->has_monitor_mode = 1;
 169                         break;
 170                 case 6:
 171                         reg_list[EICE_DBG_CTRL].size = 6;
 172                         reg_list[EICE_DBG_STAT].size = 10;
 173                         arm7_9->has_monitor_mode = 1;
 174                         break;
 175                 case 7:
 176                         LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
 177                         reg_list[EICE_DBG_CTRL].size = 6;
 178                         reg_list[EICE_DBG_STAT].size = 5;
 179                         arm7_9->has_monitor_mode = 1;
 180                         break;
 181                 default:
 182                         LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 183         }
 184
 185         return reg_cache;
 186 }
 187
 188 int embeddedice_setup(target_t *target)
 189 {
 190         int retval;
 191         armv4_5_common_t *armv4_5 = target->arch_info;
 192         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 193
 194         /* explicitly disable monitor mode */
 195         if (arm7_9->has_monitor_mode)
 196         {
 197                 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 198
 199                 embeddedice_read_reg(dbg_ctrl);
 200                 if ((retval=jtag_execute_queue())!=ERROR_OK)
 201                         return retval;
 202                 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
 203                 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
 204         }
 205         return jtag_execute_queue();
 206 }
 207
 208 static int embeddedice_get_reg(reg_t *reg)
 209 {
 210         int retval;
 211         if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
 212         {
 213                 LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
 214                 return retval;
 215         }
 216
 217         if ((retval = jtag_execute_queue()) != ERROR_OK)
 218         {
 219                 LOG_ERROR("register read failed");
 220                 return retval;
 221         }
 222
 223         return ERROR_OK;
 224 }
 225
 226 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 227 {
 228         embeddedice_reg_t *ice_reg = reg->arch_info;
 229         u8 reg_addr = ice_reg->addr & 0x1f;
 230         scan_field_t fields[3];
 231         u8 field1_out[1];
 232         u8 field2_out[1];
 233
 234         jtag_add_end_state(TAP_IDLE);
 235         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 236
 237         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 238
 239         fields[0].tap = ice_reg->jtag_info->tap;
 240         fields[0].num_bits = 32;
 241         fields[0].out_value = reg->value;
 242         fields[0].in_value = NULL;
 243         fields[0].check_value = NULL;
 244         fields[0].check_mask = NULL;
 245
 246         fields[1].tap = ice_reg->jtag_info->tap;
 247         fields[1].num_bits = 5;
 248         fields[1].out_value = field1_out;
 249         buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
 250         fields[1].in_value = NULL;
 251         fields[1].check_value = NULL;
 252         fields[1].check_mask = NULL;
 253
 254         fields[2].tap = ice_reg->jtag_info->tap;
 255         fields[2].num_bits = 1;
 256         fields[2].out_value = field2_out;
 257         buf_set_u32(fields[2].out_value, 0, 1, 0);
 258         fields[2].in_value = NULL;
 259         fields[2].check_value = NULL;
 260         fields[2].check_mask = NULL;
 261
 262         jtag_add_dr_scan(3, fields, TAP_INVALID);
 263
 264         fields[0].in_value = reg->value;
 265         fields[0].check_value = check_value;
 266         fields[0].check_mask = check_mask;
 267
 268         /* when reading the DCC data register, leaving the address field set to
 269          * EICE_COMMS_DATA would read the register twice
 270          * reading the control register is safe
 271          */
 272         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 273
 274         jtag_add_dr_scan_check(3, fields, TAP_INVALID);
 275
 276         return ERROR_OK;
 277 }
 278
 279 /* receive <size> words of 32 bit from the DCC
 280  * we pretend the target is always going to be fast enough
 281  * (relative to the JTAG clock), so we don't need to handshake
 282  */
 283 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
 284 {
 285         scan_field_t fields[3];
 286         u8 field1_out[1];
 287         u8 field2_out[1];
 288
 289         jtag_add_end_state(TAP_IDLE);
 290         arm_jtag_scann(jtag_info, 0x2);
 291         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 292
 293         fields[0].tap = jtag_info->tap;
 294         fields[0].num_bits = 32;
 295         fields[0].out_value = NULL;
 296         fields[0].in_value = NULL;
 297
 298         fields[1].tap = jtag_info->tap;
 299         fields[1].num_bits = 5;
 300         fields[1].out_value = field1_out;
 301         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
 302         fields[1].in_value = NULL;
 303
 304         fields[2].tap = jtag_info->tap;
 305         fields[2].num_bits = 1;
 306         fields[2].out_value = field2_out;
 307         buf_set_u32(fields[2].out_value, 0, 1, 0);
 308         fields[2].in_value = NULL;
 309
 310         jtag_add_dr_scan(3, fields, TAP_INVALID);
 311
 312         while (size > 0)
 313         {
 314                 /* when reading the last item, set the register address to the DCC control reg,
 315                  * to avoid reading additional data from the DCC data reg
 316                  */
 317                 if (size == 1)
 318                         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 319
 320                 fields[0].in_value = (u8 *)data;
 321                 jtag_add_dr_scan(3, fields, TAP_INVALID);
 322                 jtag_add_callback(arm_le_to_h_u32, (u8 *)data);
 323
 324                 data++;
 325                 size--;
 326         }
 327
 328         return jtag_execute_queue();
 329 }
 330
 331 int embeddedice_read_reg(reg_t *reg)
 332 {
 333         return embeddedice_read_reg_w_check(reg, NULL, NULL);
 334 }
 335
 336 void embeddedice_set_reg(reg_t *reg, u32 value)
 337 {
 338         embeddedice_write_reg(reg, value);
 339
 340         buf_set_u32(reg->value, 0, reg->size, value);
 341         reg->valid = 1;
 342         reg->dirty = 0;
 343
 344 }
 345
 346 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
 347 {
 348         int retval;
 349         embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 350
 351         if ((retval = jtag_execute_queue()) != ERROR_OK)
 352         {
 353                 LOG_ERROR("register write failed");
 354                 return retval;
 355         }
 356         return ERROR_OK;
 357 }
 358
 359 void embeddedice_write_reg(reg_t *reg, u32 value)
 360 {
 361         embeddedice_reg_t *ice_reg = reg->arch_info;
 362
 363         LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
 364
 365         jtag_add_end_state(TAP_IDLE);
 366         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 367
 368         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 369
 370         u8 reg_addr = ice_reg->addr & 0x1f;
 371         embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
 372
 373 }
 374
 375 void embeddedice_store_reg(reg_t *reg)
 376 {
 377         embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 378 }
 379
 380 /* send <size> words of 32 bit to the DCC
 381  * we pretend the target is always going to be fast enough
 382  * (relative to the JTAG clock), so we don't need to handshake
 383  */
 384 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
 385 {
 386         scan_field_t fields[3];
 387         u8 field0_out[4];
 388         u8 field1_out[1];
 389         u8 field2_out[1];
 390
 391         jtag_add_end_state(TAP_IDLE);
 392         arm_jtag_scann(jtag_info, 0x2);
 393         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 394
 395         fields[0].tap = jtag_info->tap;
 396         fields[0].num_bits = 32;
 397         fields[0].out_value = field0_out;
 398         fields[0].in_value = NULL;
 399
 400         fields[1].tap = jtag_info->tap;
 401         fields[1].num_bits = 5;
 402         fields[1].out_value = field1_out;
 403         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
 404         fields[1].in_value = NULL;
 405
 406         fields[2].tap = jtag_info->tap;
 407         fields[2].num_bits = 1;
 408         fields[2].out_value = field2_out;
 409         buf_set_u32(fields[2].out_value, 0, 1, 1);
 410
 411         fields[2].in_value = NULL;
 412
 413         while (size > 0)
 414         {
 415                 buf_set_u32(fields[0].out_value, 0, 32, *data);
 416                 jtag_add_dr_scan(3, fields, TAP_INVALID);
 417
 418                 data++;
 419                 size--;
 420         }
 421
 422         /* call to jtag_execute_queue() intentionally omitted */
 423         return ERROR_OK;
 424 }
 425
 426 /* wait for DCC control register R/W handshake bit to become active
 427  */
 428 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
 429 {
 430         scan_field_t fields[3];
 431         u8 field0_in[4];
 432         u8 field1_out[1];
 433         u8 field2_out[1];
 434         int retval;
 435         u32 hsact;
 436         struct timeval lap;
 437         struct timeval now;
 438
 439         if (hsbit == EICE_COMM_CTRL_WBIT)
 440                 hsact = 1;
 441         else if (hsbit == EICE_COMM_CTRL_RBIT)
 442                 hsact = 0;
 443         else
 444                 return ERROR_INVALID_ARGUMENTS;
 445
 446         jtag_add_end_state(TAP_IDLE);
 447         arm_jtag_scann(jtag_info, 0x2);
 448         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 449
 450         fields[0].tap = jtag_info->tap;
 451         fields[0].num_bits = 32;
 452         fields[0].out_value = NULL;
 453         fields[0].in_value = field0_in;
 454
 455         fields[1].tap = jtag_info->tap;
 456         fields[1].num_bits = 5;
 457         fields[1].out_value = field1_out;
 458         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 459         fields[1].in_value = NULL;
 460
 461         fields[2].tap = jtag_info->tap;
 462         fields[2].num_bits = 1;
 463         fields[2].out_value = field2_out;
 464         buf_set_u32(fields[2].out_value, 0, 1, 0);
 465         fields[2].in_value = NULL;
 466
 467         jtag_add_dr_scan(3, fields, TAP_INVALID);
 468         gettimeofday(&lap, NULL);
 469         do
 470         {
 471                 jtag_add_dr_scan(3, fields, TAP_INVALID);
 472                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 473                         return retval;
 474
 475                 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
 476                         return ERROR_OK;
 477
 478                 gettimeofday(&now, NULL);
 479         }
 480         while ((u32)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout);
 481
 482         return ERROR_TARGET_TIMEOUT;
 483 }
 484
 485 /* this is the inner loop of the open loop DCC write of data to target */
 486 void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
 487 {
 488         int i;
 489         for (i = 0; i < count; i++)
 490         {
 491                 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
 492                 buffer += 4;
 493         }
 494 }