git.gag.com Git - fw/openocd/blob - src/target/embeddedice.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "embeddedice.h"
  25
  26 #include "armv4_5.h"
  27 #include "arm7_9_common.h"
  28
  29 #include "log.h"
  30 #include "arm_jtag.h"
  31 #include "types.h"
  32 #include "binarybuffer.h"
  33 #include "target.h"
  34 #include "register.h"
  35 #include "jtag.h"
  36
  37 #include <stdlib.h>
  38
  39 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
  40 {
  41         {"R", 1},
  42         {"W", 1},
  43         {"reserved", 26},
  44         {"version", 4}
  45 };
  46
  47 int embeddedice_reg_arch_info[] =
  48 {
  49         0x0, 0x1, 0x4, 0x5,
  50         0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
  51         0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
  52         0x2
  53 };
  54
  55 char* embeddedice_reg_list[] =
  56 {
  57         "debug_ctrl",
  58         "debug_status",
  59
  60         "comms_ctrl",
  61         "comms_data",
  62
  63         "watch 0 addr value",
  64         "watch 0 addr mask",
  65         "watch 0 data value",
  66         "watch 0 data mask",
  67         "watch 0 control value",
  68         "watch 0 control mask",
  69
  70         "watch 1 addr value",
  71         "watch 1 addr mask",
  72         "watch 1 data value",
  73         "watch 1 data mask",
  74         "watch 1 control value",
  75         "watch 1 control mask",
  76
  77         "vector catch"
  78 };
  79
  80 int embeddedice_reg_arch_type = -1;
  81
  82 int embeddedice_get_reg(reg_t *reg);
  83 int embeddedice_set_reg(reg_t *reg, u32 value);
  84 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
  85
  86 int embeddedice_write_reg(reg_t *reg, u32 value);
  87 int embeddedice_read_reg(reg_t *reg);
  88
  89 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
  90 {
  91         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
  92         reg_t *reg_list = NULL;
  93         embeddedice_reg_t *arch_info = NULL;
  94         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  95         int num_regs;
  96         int i;
  97         int eice_version = 0;
  98
  99         /* register a register arch-type for EmbeddedICE registers only once */
 100         if (embeddedice_reg_arch_type == -1)
 101                 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
 102
 103         if (arm7_9->has_vector_catch)
 104                 num_regs = 17;
 105         else
 106                 num_regs = 16;
 107
 108         /* the actual registers are kept in two arrays */
 109         reg_list = calloc(num_regs, sizeof(reg_t));
 110         arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
 111
 112         /* fill in values for the reg cache */
 113         reg_cache->name = "EmbeddedICE registers";
 114         reg_cache->next = NULL;
 115         reg_cache->reg_list = reg_list;
 116         reg_cache->num_regs = num_regs;
 117
 118         /* set up registers */
 119         for (i = 0; i < num_regs; i++)
 120         {
 121                 reg_list[i].name = embeddedice_reg_list[i];
 122                 reg_list[i].size = 32;
 123                 reg_list[i].dirty = 0;
 124                 reg_list[i].valid = 0;
 125                 reg_list[i].bitfield_desc = NULL;
 126                 reg_list[i].num_bitfields = 0;
 127                 reg_list[i].value = calloc(1, 4);
 128                 reg_list[i].arch_info = &arch_info[i];
 129                 reg_list[i].arch_type = embeddedice_reg_arch_type;
 130                 arch_info[i].addr = embeddedice_reg_arch_info[i];
 131                 arch_info[i].jtag_info = jtag_info;
 132         }
 133
 134         /* identify EmbeddedICE version by reading DCC control register */
 135         embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
 136         jtag_execute_queue();
 137
 138         eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
 139
 140         switch (eice_version)
 141         {
 142                 case 1:
 143                         reg_list[EICE_DBG_CTRL].size = 3;
 144                         reg_list[EICE_DBG_STAT].size = 5;
 145                         break;
 146                 case 2:
 147                         reg_list[EICE_DBG_CTRL].size = 4;
 148                         reg_list[EICE_DBG_STAT].size = 5;
 149                         arm7_9->has_single_step = 1;
 150                         break;
 151                 case 3:
 152                         ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
 153                         reg_list[EICE_DBG_CTRL].size = 6;
 154                         reg_list[EICE_DBG_STAT].size = 5;
 155                         arm7_9->has_single_step = 1;
 156                         arm7_9->has_monitor_mode = 1;
 157                         break;
 158                 case 4:
 159                         reg_list[EICE_DBG_CTRL].size = 6;
 160                         reg_list[EICE_DBG_STAT].size = 5;
 161                         arm7_9->has_monitor_mode = 1;
 162                         break;
 163                 case 5:
 164                         reg_list[EICE_DBG_CTRL].size = 6;
 165                         reg_list[EICE_DBG_STAT].size = 5;
 166                         arm7_9->has_single_step = 1;
 167                         arm7_9->has_monitor_mode = 1;
 168                         break;
 169                 case 6:
 170                         reg_list[EICE_DBG_CTRL].size = 6;
 171                         reg_list[EICE_DBG_STAT].size = 10;
 172                         arm7_9->has_single_step = 1;
 173                         arm7_9->has_monitor_mode = 1;
 174                         break;
 175                 default:
 176                         ERROR("unknown EmbeddedICE version (comms ctrl: 0x%4.4x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 177         }
 178
 179         return reg_cache;
 180 }
 181
 182 int embeddedice_get_reg(reg_t *reg)
 183 {
 184         if (embeddedice_read_reg(reg) != ERROR_OK)
 185         {
 186                 ERROR("BUG: error scheduling EmbeddedICE register read");
 187                 exit(-1);
 188         }
 189
 190         if (jtag_execute_queue() != ERROR_OK)
 191         {
 192                 ERROR("register read failed");
 193         }
 194
 195         return ERROR_OK;
 196 }
 197
 198 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 199 {
 200         embeddedice_reg_t *ice_reg = reg->arch_info;
 201         u8 reg_addr = ice_reg->addr & 0x1f;
 202         scan_field_t fields[3];
 203
 204         DEBUG("%i", ice_reg->addr);
 205
 206         jtag_add_end_state(TAP_RTI);
 207         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 208         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr);
 209
 210         fields[0].device = ice_reg->jtag_info->chain_pos;
 211         fields[0].num_bits = 32;
 212         fields[0].out_value = reg->value;
 213         fields[0].out_mask = NULL;
 214         fields[0].in_value = NULL;
 215         fields[0].in_check_value = NULL;
 216         fields[0].in_check_mask = NULL;
 217         fields[0].in_handler = NULL;
 218         fields[0].in_handler_priv = NULL;
 219
 220         fields[1].device = ice_reg->jtag_info->chain_pos;
 221         fields[1].num_bits = 5;
 222         fields[1].out_value = malloc(1);
 223         buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
 224         fields[1].out_mask = NULL;
 225         fields[1].in_value = NULL;
 226         fields[1].in_check_value = NULL;
 227         fields[1].in_check_mask = NULL;
 228         fields[1].in_handler = NULL;
 229         fields[1].in_handler_priv = NULL;
 230
 231         fields[2].device = ice_reg->jtag_info->chain_pos;
 232         fields[2].num_bits = 1;
 233         fields[2].out_value = malloc(1);
 234         buf_set_u32(fields[2].out_value, 0, 1, 0);
 235         fields[2].out_mask = NULL;
 236         fields[2].in_value = NULL;
 237         fields[2].in_check_value = NULL;
 238         fields[2].in_check_mask = NULL;
 239         fields[2].in_handler = NULL;
 240         fields[2].in_handler_priv = NULL;
 241
 242         jtag_add_dr_scan(3, fields, -1);
 243
 244         fields[0].in_value = reg->value;
 245         fields[0].in_check_value = check_value;
 246         fields[0].in_check_mask = check_mask;
 247
 248         /* when reading the DCC data register, leaving the address field set to
 249          * EICE_COMMS_DATA would read the register twice
 250          * reading the control register is safe
 251          */
 252         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 253
 254         jtag_add_dr_scan(3, fields, -1);
 255
 256         free(fields[1].out_value);
 257         free(fields[2].out_value);
 258
 259         return ERROR_OK;
 260 }
 261
 262 int embeddedice_read_reg(reg_t *reg)
 263 {
 264         return embeddedice_read_reg_w_check(reg, NULL, NULL);
 265 }
 266
 267 int embeddedice_set_reg(reg_t *reg, u32 value)
 268 {
 269         if (embeddedice_write_reg(reg, value) != ERROR_OK)
 270         {
 271                 ERROR("BUG: error scheduling EmbeddedICE register write");
 272                 exit(-1);
 273         }
 274
 275         buf_set_u32(reg->value, 0, reg->size, value);
 276         reg->valid = 1;
 277         reg->dirty = 0;
 278
 279         return ERROR_OK;
 280 }
 281
 282 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
 283 {
 284         embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 285
 286         if (jtag_execute_queue() != ERROR_OK)
 287         {
 288                 ERROR("register write failed");
 289                 exit(-1);
 290         }
 291         return ERROR_OK;
 292 }
 293
 294 int embeddedice_write_reg(reg_t *reg, u32 value)
 295 {
 296         embeddedice_reg_t *ice_reg = reg->arch_info;
 297         u8 reg_addr = ice_reg->addr & 0x1f;
 298         scan_field_t fields[3];
 299
 300         DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
 301
 302         jtag_add_end_state(TAP_RTI);
 303         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 304         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr);
 305
 306         fields[0].device = ice_reg->jtag_info->chain_pos;
 307         fields[0].num_bits = 32;
 308         fields[0].out_value = malloc(4);
 309         buf_set_u32(fields[0].out_value, 0, 32, value);
 310         fields[0].out_mask = NULL;
 311         fields[0].in_value = NULL;
 312         fields[0].in_check_value = NULL;
 313         fields[0].in_check_mask = NULL;
 314         fields[0].in_handler = NULL;
 315         fields[0].in_handler_priv = NULL;
 316
 317         fields[1].device = ice_reg->jtag_info->chain_pos;
 318         fields[1].num_bits = 5;
 319         fields[1].out_value = malloc(1);
 320         buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
 321         fields[1].out_mask = NULL;
 322         fields[1].in_value = NULL;
 323         fields[1].in_check_value = NULL;
 324         fields[1].in_check_mask = NULL;
 325         fields[1].in_handler = NULL;
 326         fields[1].in_handler_priv = NULL;
 327
 328         fields[2].device = ice_reg->jtag_info->chain_pos;
 329         fields[2].num_bits = 1;
 330         fields[2].out_value = malloc(1);
 331         buf_set_u32(fields[2].out_value, 0, 1, 1);
 332         fields[2].out_mask = NULL;
 333         fields[2].in_value = NULL;
 334         fields[2].in_check_value = NULL;
 335         fields[2].in_check_mask = NULL;
 336         fields[2].in_handler = NULL;
 337         fields[2].in_handler_priv = NULL;
 338
 339         jtag_add_dr_scan(3, fields, -1);
 340
 341         free(fields[0].out_value);
 342         free(fields[1].out_value);
 343         free(fields[2].out_value);
 344
 345         return ERROR_OK;
 346 }
 347
 348 int embeddedice_store_reg(reg_t *reg)
 349 {
 350         return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 351 }
 352