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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008,2009 Øyvind Harboe                            *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "embeddedice.h"
  31 #include "register.h"
  32
  33 /**
  34  * @file
  35  *
  36  * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT)
  37  * module found on scan chain 2 in ARM7, ARM9, and some other families
  38  * of ARM cores.  The module is called "EmbeddedICE-RT" if it has
  39  * monitor mode support.
  40  *
  41  * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug
  42  * Communications Channel (DCC) used to read or write 32-bit words to
  43  * OpenOCD-aware code running on the target CPU.
  44  * Newer modules also include vector catch hardware.  Some versions
  45  * support hardware single-stepping, "monitor mode" debug (which is not
  46  * currently supported by OpenOCD), or extended reporting on why the
  47  * core entered debug mode.
  48  */
  49
  50 /*
  51  * From:  ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
  52  */
  53 static const struct {
  54         char            *name;
  55         unsigned short  addr;
  56         unsigned short  width;
  57 } eice_regs[] = {
  58         [EICE_DBG_CTRL] = {
  59                 .name =         "debug_ctrl",
  60                 .addr =         0,
  61                 /* width is assigned based on EICE version */
  62         },
  63         [EICE_DBG_STAT] = {
  64                 .name =         "debug_status",
  65                 .addr =         1,
  66                 /* width is assigned based on EICE version */
  67         },
  68         [EICE_COMMS_CTRL] = {
  69                 .name =         "comms_ctrl",
  70                 .addr =         4,
  71                 .width =        6,
  72         },
  73         [EICE_COMMS_DATA] = {
  74                 .name =         "comms_data",
  75                 .addr =         5,
  76                 .width =        32,
  77         },
  78         [EICE_W0_ADDR_VALUE] = {
  79                 .name =         "watch_0_addr_value",
  80                 .addr =         8,
  81                 .width =        32,
  82         },
  83         [EICE_W0_ADDR_MASK] = {
  84                 .name =         "watch_0_addr_mask",
  85                 .addr =         9,
  86                 .width =        32,
  87         },
  88         [EICE_W0_DATA_VALUE ] = {
  89                 .name =         "watch_0_data_value",
  90                 .addr =         10,
  91                 .width =        32,
  92         },
  93         [EICE_W0_DATA_MASK] = {
  94                 .name =         "watch_0_data_mask",
  95                 .addr =         11,
  96                 .width =        32,
  97         },
  98         [EICE_W0_CONTROL_VALUE] = {
  99                 .name =         "watch_0_control_value",
 100                 .addr =         12,
 101                 .width =        9,
 102         },
 103         [EICE_W0_CONTROL_MASK] = {
 104                 .name =         "watch_0_control_mask",
 105                 .addr =         13,
 106                 .width =        8,
 107         },
 108         [EICE_W1_ADDR_VALUE] = {
 109                 .name =         "watch_1_addr_value",
 110                 .addr =         16,
 111                 .width =        32,
 112         },
 113         [EICE_W1_ADDR_MASK] = {
 114                 .name =         "watch_1_addr_mask",
 115                 .addr =         17,
 116                 .width =        32,
 117         },
 118         [EICE_W1_DATA_VALUE] = {
 119                 .name =         "watch_1_data_value",
 120                 .addr =         18,
 121                 .width =        32,
 122         },
 123         [EICE_W1_DATA_MASK] = {
 124                 .name =         "watch_1_data_mask",
 125                 .addr =         19,
 126                 .width =        32,
 127         },
 128         [EICE_W1_CONTROL_VALUE] = {
 129                 .name =         "watch_1_control_value",
 130                 .addr =         20,
 131                 .width =        9,
 132         },
 133         [EICE_W1_CONTROL_MASK] = {
 134                 .name =         "watch_1_control_mask",
 135                 .addr =         21,
 136                 .width =        8,
 137         },
 138         /* vector_catch isn't always present */
 139         [EICE_VEC_CATCH] = {
 140                 .name =         "vector_catch",
 141                 .addr =         2,
 142                 .width =        8,
 143         },
 144 };
 145
 146
 147 static int embeddedice_get_reg(struct reg *reg)
 148 {
 149         int retval;
 150
 151         if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
 152                 LOG_ERROR("error queueing EmbeddedICE register read");
 153         else if ((retval = jtag_execute_queue()) != ERROR_OK)
 154                 LOG_ERROR("EmbeddedICE register read failed");
 155
 156         return retval;
 157 }
 158
 159 static const struct reg_arch_type eice_reg_type = {
 160         .get = embeddedice_get_reg,
 161         .set = embeddedice_set_reg_w_exec,
 162 };
 163
 164 /**
 165  * Probe EmbeddedICE module and set up local records of its registers.
 166  * Different versions of the modules have different capabilities, such as
 167  * hardware support for vector_catch, single stepping, and monitor mode.
 168  */
 169 struct reg_cache *
 170 embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
 171 {
 172         int retval;
 173         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 174         struct reg *reg_list = NULL;
 175         struct embeddedice_reg *arch_info = NULL;
 176         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 177         int num_regs = ARRAY_SIZE(eice_regs);
 178         int i;
 179         int eice_version = 0;
 180
 181         /* vector_catch isn't always present */
 182         if (!arm7_9->has_vector_catch)
 183                 num_regs--;
 184
 185         /* the actual registers are kept in two arrays */
 186         reg_list = calloc(num_regs, sizeof(struct reg));
 187         arch_info = calloc(num_regs, sizeof(struct embeddedice_reg));
 188
 189         /* fill in values for the reg cache */
 190         reg_cache->name = "EmbeddedICE registers";
 191         reg_cache->next = NULL;
 192         reg_cache->reg_list = reg_list;
 193         reg_cache->num_regs = num_regs;
 194
 195         /* set up registers */
 196         for (i = 0; i < num_regs; i++)
 197         {
 198                 reg_list[i].name = eice_regs[i].name;
 199                 reg_list[i].size = eice_regs[i].width;
 200                 reg_list[i].dirty = 0;
 201                 reg_list[i].valid = 0;
 202                 reg_list[i].value = calloc(1, 4);
 203                 reg_list[i].arch_info = &arch_info[i];
 204                 reg_list[i].type = &eice_reg_type;
 205                 arch_info[i].addr = eice_regs[i].addr;
 206                 arch_info[i].jtag_info = jtag_info;
 207         }
 208
 209         /* identify EmbeddedICE version by reading DCC control register */
 210         embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
 211         if ((retval = jtag_execute_queue()) != ERROR_OK)
 212         {
 213                 for (i = 0; i < num_regs; i++)
 214                 {
 215                         free(reg_list[i].value);
 216                 }
 217                 free(reg_list);
 218                 free(reg_cache);
 219                 free(arch_info);
 220                 return NULL;
 221         }
 222
 223         eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
 224         LOG_INFO("Embedded ICE version %d", eice_version);
 225
 226         switch (eice_version)
 227         {
 228                 case 1:
 229                         /* ARM7TDMI r3, ARM7TDMI-S r3
 230                          *
 231                          * REVISIT docs say ARM7TDMI-S r4 uses version 1 but
 232                          * that it has 6-bit CTRL and 5-bit STAT... doc bug?
 233                          * ARM7TDMI r4 docs say EICE v4.
 234                          */
 235                         reg_list[EICE_DBG_CTRL].size = 3;
 236                         reg_list[EICE_DBG_STAT].size = 5;
 237                         break;
 238                 case 2:
 239                         /* ARM9TDMI */
 240                         reg_list[EICE_DBG_CTRL].size = 4;
 241                         reg_list[EICE_DBG_STAT].size = 5;
 242                         arm7_9->has_single_step = 1;
 243                         break;
 244                 case 3:
 245                         LOG_ERROR("EmbeddedICE v%d handling might be broken",
 246                                         eice_version);
 247                         reg_list[EICE_DBG_CTRL].size = 6;
 248                         reg_list[EICE_DBG_STAT].size = 5;
 249                         arm7_9->has_single_step = 1;
 250                         arm7_9->has_monitor_mode = 1;
 251                         break;
 252                 case 4:
 253                         /* ARM7TDMI r4 */
 254                         reg_list[EICE_DBG_CTRL].size = 6;
 255                         reg_list[EICE_DBG_STAT].size = 5;
 256                         arm7_9->has_monitor_mode = 1;
 257                         break;
 258                 case 5:
 259                         /* ARM9E-S rev 1 */
 260                         reg_list[EICE_DBG_CTRL].size = 6;
 261                         reg_list[EICE_DBG_STAT].size = 5;
 262                         arm7_9->has_single_step = 1;
 263                         arm7_9->has_monitor_mode = 1;
 264                         break;
 265                 case 6:
 266                         /* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */
 267                         reg_list[EICE_DBG_CTRL].size = 6;
 268                         reg_list[EICE_DBG_STAT].size = 10;
 269                         /* DBG_STAT has MOE bits */
 270                         arm7_9->has_monitor_mode = 1;
 271                         break;
 272                 case 7:
 273                         LOG_ERROR("EmbeddedICE v%d handling might be broken",
 274                                         eice_version);
 275                         reg_list[EICE_DBG_CTRL].size = 6;
 276                         reg_list[EICE_DBG_STAT].size = 5;
 277                         arm7_9->has_monitor_mode = 1;
 278                         break;
 279                 default:
 280                         /*
 281                          * The Feroceon implementation has the version number
 282                          * in some unusual bits.  Let feroceon.c validate it
 283                          * and do the appropriate setup itself.
 284                          */
 285                         if (strcmp(target_type_name(target), "feroceon") == 0 ||
 286                             strcmp(target_type_name(target), "dragonite") == 0)
 287                                 break;
 288                         LOG_ERROR("unknown EmbeddedICE version "
 289                                 "(comms ctrl: 0x%8.8" PRIx32 ")",
 290                                 buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 291         }
 292
 293         LOG_INFO("%s: hardware has 2 breakpoints or watchpoints",
 294                         target_name(target));
 295
 296         return reg_cache;
 297 }
 298
 299 /**
 300  * Initialize EmbeddedICE module, if needed.
 301  */
 302 int embeddedice_setup(struct target *target)
 303 {
 304         int retval;
 305         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 306
 307         /* Explicitly disable monitor mode.  For now we only support halting
 308          * debug ... we don't know how to talk with a resident debug monitor
 309          * that manages break requests.  ARM's "Angel Debug Monitor" is one
 310          * common example of such code.
 311          */
 312         if (arm7_9->has_monitor_mode)
 313         {
 314                 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 315
 316                 embeddedice_read_reg(dbg_ctrl);
 317                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 318                         return retval;
 319                 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
 320                 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
 321         }
 322         return jtag_execute_queue();
 323 }
 324
 325 /**
 326  * Queue a read for an EmbeddedICE register into the register cache,
 327  * optionally checking the value read.
 328  * Note that at this level, all registers are 32 bits wide.
 329  */
 330 int embeddedice_read_reg_w_check(struct reg *reg,
 331                 uint8_t *check_value, uint8_t *check_mask)
 332 {
 333         struct embeddedice_reg *ice_reg = reg->arch_info;
 334         uint8_t reg_addr = ice_reg->addr & 0x1f;
 335         struct scan_field fields[3];
 336         uint8_t field1_out[1];
 337         uint8_t field2_out[1];
 338
 339         jtag_set_end_state(TAP_IDLE);
 340         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 341
 342         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 343
 344         /* bits 31:0 -- data (ignored here) */
 345         fields[0].tap = ice_reg->jtag_info->tap;
 346         fields[0].num_bits = 32;
 347         fields[0].out_value = reg->value;
 348         fields[0].in_value = NULL;
 349         fields[0].check_value = NULL;
 350         fields[0].check_mask = NULL;
 351
 352         /* bits 36:32 -- register */
 353         fields[1].tap = ice_reg->jtag_info->tap;
 354         fields[1].num_bits = 5;
 355         fields[1].out_value = field1_out;
 356         fields[1].out_value[0] = reg_addr;
 357         fields[1].in_value = NULL;
 358         fields[1].check_value = NULL;
 359         fields[1].check_mask = NULL;
 360
 361         /* bit 37 -- 0/read */
 362         fields[2].tap = ice_reg->jtag_info->tap;
 363         fields[2].num_bits = 1;
 364         fields[2].out_value = field2_out;
 365         fields[2].out_value[0] = 0;
 366         fields[2].in_value = NULL;
 367         fields[2].check_value = NULL;
 368         fields[2].check_mask = NULL;
 369
 370         /* traverse Update-DR, setting address for the next read */
 371         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 372
 373         /* bits 31:0 -- the data we're reading (and maybe checking) */
 374         fields[0].in_value = reg->value;
 375         fields[0].check_value = check_value;
 376         fields[0].check_mask = check_mask;
 377
 378         /* when reading the DCC data register, leaving the address field set to
 379          * EICE_COMMS_DATA would read the register twice
 380          * reading the control register is safe
 381          */
 382         fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
 383
 384         /* traverse Update-DR, reading but with no other side effects */
 385         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 386
 387         return ERROR_OK;
 388 }
 389
 390 /**
 391  * Receive a block of size 32-bit words from the DCC.
 392  * We assume the target is always going to be fast enough (relative to
 393  * the JTAG clock) that the debugger won't need to poll the handshake
 394  * bit.  The JTAG clock is usually at least six times slower than the
 395  * functional clock, so the 50+ JTAG clocks needed to receive the word
 396  * allow hundreds of instruction cycles (per word) in the target.
 397  */
 398 int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 399 {
 400         struct scan_field fields[3];
 401         uint8_t field1_out[1];
 402         uint8_t field2_out[1];
 403
 404         jtag_set_end_state(TAP_IDLE);
 405         arm_jtag_scann(jtag_info, 0x2);
 406         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 407
 408         fields[0].tap = jtag_info->tap;
 409         fields[0].num_bits = 32;
 410         fields[0].out_value = NULL;
 411         fields[0].in_value = NULL;
 412
 413         fields[1].tap = jtag_info->tap;
 414         fields[1].num_bits = 5;
 415         fields[1].out_value = field1_out;
 416         fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
 417         fields[1].in_value = NULL;
 418
 419         fields[2].tap = jtag_info->tap;
 420         fields[2].num_bits = 1;
 421         fields[2].out_value = field2_out;
 422         fields[2].out_value[0] = 0;
 423         fields[2].in_value = NULL;
 424
 425         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 426
 427         while (size > 0)
 428         {
 429                 /* when reading the last item, set the register address to the DCC control reg,
 430                  * to avoid reading additional data from the DCC data reg
 431                  */
 432                 if (size == 1)
 433                         fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
 434
 435                 fields[0].in_value = (uint8_t *)data;
 436                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 437                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data);
 438
 439                 data++;
 440                 size--;
 441         }
 442
 443         return jtag_execute_queue();
 444 }
 445
 446 /**
 447  * Queue a read for an EmbeddedICE register into the register cache,
 448  * not checking the value read.
 449  */
 450 int embeddedice_read_reg(struct reg *reg)
 451 {
 452         return embeddedice_read_reg_w_check(reg, NULL, NULL);
 453 }
 454
 455 /**
 456  * Queue a write for an EmbeddedICE register, updating the register cache.
 457  * Uses embeddedice_write_reg().
 458  */
 459 void embeddedice_set_reg(struct reg *reg, uint32_t value)
 460 {
 461         embeddedice_write_reg(reg, value);
 462
 463         buf_set_u32(reg->value, 0, reg->size, value);
 464         reg->valid = 1;
 465         reg->dirty = 0;
 466
 467 }
 468
 469 /**
 470  * Write an EmbeddedICE register, updating the register cache.
 471  * Uses embeddedice_set_reg(); not queued.
 472  */
 473 int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 474 {
 475         int retval;
 476
 477         embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 478         if ((retval = jtag_execute_queue()) != ERROR_OK)
 479                 LOG_ERROR("register write failed");
 480         return retval;
 481 }
 482
 483 /**
 484  * Queue a write for an EmbeddedICE register, bypassing the register cache.
 485  */
 486 void embeddedice_write_reg(struct reg *reg, uint32_t value)
 487 {
 488         struct embeddedice_reg *ice_reg = reg->arch_info;
 489
 490         LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 491
 492         jtag_set_end_state(TAP_IDLE);
 493         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 494
 495         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 496
 497         uint8_t reg_addr = ice_reg->addr & 0x1f;
 498         embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
 499 }
 500
 501 /**
 502  * Queue a write for an EmbeddedICE register, using cached value.
 503  * Uses embeddedice_write_reg().
 504  */
 505 void embeddedice_store_reg(struct reg *reg)
 506 {
 507         embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 508 }
 509
 510 /**
 511  * Send a block of size 32-bit words to the DCC.
 512  * We assume the target is always going to be fast enough (relative to
 513  * the JTAG clock) that the debugger won't need to poll the handshake
 514  * bit.  The JTAG clock is usually at least six times slower than the
 515  * functional clock, so the 50+ JTAG clocks needed to receive the word
 516  * allow hundreds of instruction cycles (per word) in the target.
 517  */
 518 int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 519 {
 520         struct scan_field fields[3];
 521         uint8_t field0_out[4];
 522         uint8_t field1_out[1];
 523         uint8_t field2_out[1];
 524
 525         jtag_set_end_state(TAP_IDLE);
 526         arm_jtag_scann(jtag_info, 0x2);
 527         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 528
 529         fields[0].tap = jtag_info->tap;
 530         fields[0].num_bits = 32;
 531         fields[0].out_value = field0_out;
 532         fields[0].in_value = NULL;
 533
 534         fields[1].tap = jtag_info->tap;
 535         fields[1].num_bits = 5;
 536         fields[1].out_value = field1_out;
 537         fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
 538         fields[1].in_value = NULL;
 539
 540         fields[2].tap = jtag_info->tap;
 541         fields[2].num_bits = 1;
 542         fields[2].out_value = field2_out;
 543         fields[2].out_value[0] = 1;
 544
 545         fields[2].in_value = NULL;
 546
 547         while (size > 0)
 548         {
 549                 buf_set_u32(fields[0].out_value, 0, 32, *data);
 550                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 551
 552                 data++;
 553                 size--;
 554         }
 555
 556         /* call to jtag_execute_queue() intentionally omitted */
 557         return ERROR_OK;
 558 }
 559
 560 /**
 561  * Poll DCC control register until read or write handshake completes.
 562  */
 563 int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout)
 564 {
 565         struct scan_field fields[3];
 566         uint8_t field0_in[4];
 567         uint8_t field1_out[1];
 568         uint8_t field2_out[1];
 569         int retval;
 570         uint32_t hsact;
 571         struct timeval lap;
 572         struct timeval now;
 573
 574         if (hsbit == EICE_COMM_CTRL_WBIT)
 575                 hsact = 1;
 576         else if (hsbit == EICE_COMM_CTRL_RBIT)
 577                 hsact = 0;
 578         else
 579                 return ERROR_INVALID_ARGUMENTS;
 580
 581         jtag_set_end_state(TAP_IDLE);
 582         arm_jtag_scann(jtag_info, 0x2);
 583         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 584
 585         fields[0].tap = jtag_info->tap;
 586         fields[0].num_bits = 32;
 587         fields[0].out_value = NULL;
 588         fields[0].in_value = field0_in;
 589
 590         fields[1].tap = jtag_info->tap;
 591         fields[1].num_bits = 5;
 592         fields[1].out_value = field1_out;
 593         fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
 594         fields[1].in_value = NULL;
 595
 596         fields[2].tap = jtag_info->tap;
 597         fields[2].num_bits = 1;
 598         fields[2].out_value = field2_out;
 599         fields[2].out_value[0] = 0;
 600         fields[2].in_value = NULL;
 601
 602         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 603         gettimeofday(&lap, NULL);
 604         do {
 605                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 606                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 607                         return retval;
 608
 609                 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
 610                         return ERROR_OK;
 611
 612                 gettimeofday(&now, NULL);
 613         } while ((uint32_t)((now.tv_sec - lap.tv_sec) * 1000
 614                         + (now.tv_usec - lap.tv_usec) / 1000) <= timeout);
 615
 616         return ERROR_TARGET_TIMEOUT;
 617 }
 618
 619 #ifndef HAVE_JTAG_MINIDRIVER_H
 620 /**
 621  * This is an inner loop of the open loop DCC write of data to target
 622  */
 623 void embeddedice_write_dcc(struct jtag_tap *tap,
 624                 int reg_addr, uint8_t *buffer, int little, int count)
 625 {
 626         int i;
 627
 628         for (i = 0; i < count; i++)
 629         {
 630                 embeddedice_write_reg_inner(tap, reg_addr,
 631                                 fast_target_buffer_get_u32(buffer, little));
 632                 buffer += 4;
 633         }
 634 }
 635 #else
 636 /* provided by minidriver */
 637 #endif