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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "embeddedice.h"
  31
  32
  33 #if 0
  34 static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
  35 {
  36         {"R", 1},
  37         {"W", 1},
  38         {"reserved", 26},
  39         {"version", 4}
  40 };
  41 #endif
  42
  43 static int embeddedice_reg_arch_info[] =
  44 {
  45         0x0, 0x1, 0x4, 0x5,
  46         0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
  47         0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
  48         0x2
  49 };
  50
  51 static char* embeddedice_reg_list[] =
  52 {
  53         "debug_ctrl",
  54         "debug_status",
  55
  56         "comms_ctrl",
  57         "comms_data",
  58
  59         "watch 0 addr value",
  60         "watch 0 addr mask",
  61         "watch 0 data value",
  62         "watch 0 data mask",
  63         "watch 0 control value",
  64         "watch 0 control mask",
  65
  66         "watch 1 addr value",
  67         "watch 1 addr mask",
  68         "watch 1 data value",
  69         "watch 1 data mask",
  70         "watch 1 control value",
  71         "watch 1 control mask",
  72
  73         "vector catch"
  74 };
  75
  76 static int embeddedice_reg_arch_type = -1;
  77
  78 static int embeddedice_get_reg(reg_t *reg);
  79
  80 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
  81 {
  82         int retval;
  83         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
  84         reg_t *reg_list = NULL;
  85         embeddedice_reg_t *arch_info = NULL;
  86         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  87         int num_regs;
  88         int i;
  89         int eice_version = 0;
  90
  91         /* register a register arch-type for EmbeddedICE registers only once */
  92         if (embeddedice_reg_arch_type == -1)
  93                 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
  94
  95         if (arm7_9->has_vector_catch)
  96                 num_regs = 17;
  97         else
  98                 num_regs = 16;
  99
 100         /* the actual registers are kept in two arrays */
 101         reg_list = calloc(num_regs, sizeof(reg_t));
 102         arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
 103
 104         /* fill in values for the reg cache */
 105         reg_cache->name = "EmbeddedICE registers";
 106         reg_cache->next = NULL;
 107         reg_cache->reg_list = reg_list;
 108         reg_cache->num_regs = num_regs;
 109
 110         /* set up registers */
 111         for (i = 0; i < num_regs; i++)
 112         {
 113                 reg_list[i].name = embeddedice_reg_list[i];
 114                 reg_list[i].size = 32;
 115                 reg_list[i].dirty = 0;
 116                 reg_list[i].valid = 0;
 117                 reg_list[i].bitfield_desc = NULL;
 118                 reg_list[i].num_bitfields = 0;
 119                 reg_list[i].value = calloc(1, 4);
 120                 reg_list[i].arch_info = &arch_info[i];
 121                 reg_list[i].arch_type = embeddedice_reg_arch_type;
 122                 arch_info[i].addr = embeddedice_reg_arch_info[i];
 123                 arch_info[i].jtag_info = jtag_info;
 124         }
 125
 126         /* identify EmbeddedICE version by reading DCC control register */
 127         embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
 128         if ((retval=jtag_execute_queue())!=ERROR_OK)
 129         {
 130                 for (i = 0; i < num_regs; i++)
 131                 {
 132                         free(reg_list[i].value);
 133                 }
 134                 free(reg_list);
 135                 free(arch_info);
 136                 return NULL;
 137         }
 138
 139         eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
 140
 141         switch (eice_version)
 142         {
 143                 case 1:
 144                         reg_list[EICE_DBG_CTRL].size = 3;
 145                         reg_list[EICE_DBG_STAT].size = 5;
 146                         break;
 147                 case 2:
 148                         reg_list[EICE_DBG_CTRL].size = 4;
 149                         reg_list[EICE_DBG_STAT].size = 5;
 150                         arm7_9->has_single_step = 1;
 151                         break;
 152                 case 3:
 153                         LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
 154                         reg_list[EICE_DBG_CTRL].size = 6;
 155                         reg_list[EICE_DBG_STAT].size = 5;
 156                         arm7_9->has_single_step = 1;
 157                         arm7_9->has_monitor_mode = 1;
 158                         break;
 159                 case 4:
 160                         reg_list[EICE_DBG_CTRL].size = 6;
 161                         reg_list[EICE_DBG_STAT].size = 5;
 162                         arm7_9->has_monitor_mode = 1;
 163                         break;
 164                 case 5:
 165                         reg_list[EICE_DBG_CTRL].size = 6;
 166                         reg_list[EICE_DBG_STAT].size = 5;
 167                         arm7_9->has_single_step = 1;
 168                         arm7_9->has_monitor_mode = 1;
 169                         break;
 170                 case 6:
 171                         reg_list[EICE_DBG_CTRL].size = 6;
 172                         reg_list[EICE_DBG_STAT].size = 10;
 173                         arm7_9->has_monitor_mode = 1;
 174                         break;
 175                 case 7:
 176                         LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
 177                         reg_list[EICE_DBG_CTRL].size = 6;
 178                         reg_list[EICE_DBG_STAT].size = 5;
 179                         arm7_9->has_monitor_mode = 1;
 180                         break;
 181                 default:
 182                         /*
 183                          * The Feroceon implementation has the version number
 184                          * in some unusual bits.  Let feroceon.c validate it
 185                          * and do the appropriate setup itself.
 186                          */
 187                         if (strcmp(target_get_name(target), "feroceon") == 0)
 188                                 break;
 189                         LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 190         }
 191
 192         return reg_cache;
 193 }
 194
 195 int embeddedice_setup(target_t *target)
 196 {
 197         int retval;
 198         armv4_5_common_t *armv4_5 = target->arch_info;
 199         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 200
 201         /* explicitly disable monitor mode */
 202         if (arm7_9->has_monitor_mode)
 203         {
 204                 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 205
 206                 embeddedice_read_reg(dbg_ctrl);
 207                 if ((retval=jtag_execute_queue())!=ERROR_OK)
 208                         return retval;
 209                 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
 210                 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
 211         }
 212         return jtag_execute_queue();
 213 }
 214
 215 static int embeddedice_get_reg(reg_t *reg)
 216 {
 217         int retval;
 218         if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
 219         {
 220                 LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
 221                 return retval;
 222         }
 223
 224         if ((retval = jtag_execute_queue()) != ERROR_OK)
 225         {
 226                 LOG_ERROR("register read failed");
 227                 return retval;
 228         }
 229
 230         return ERROR_OK;
 231 }
 232
 233 int embeddedice_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask)
 234 {
 235         embeddedice_reg_t *ice_reg = reg->arch_info;
 236         uint8_t reg_addr = ice_reg->addr & 0x1f;
 237         scan_field_t fields[3];
 238         uint8_t field1_out[1];
 239         uint8_t field2_out[1];
 240
 241         jtag_set_end_state(TAP_IDLE);
 242         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 243
 244         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 245
 246         fields[0].tap = ice_reg->jtag_info->tap;
 247         fields[0].num_bits = 32;
 248         fields[0].out_value = reg->value;
 249         fields[0].in_value = NULL;
 250         fields[0].check_value = NULL;
 251         fields[0].check_mask = NULL;
 252
 253         fields[1].tap = ice_reg->jtag_info->tap;
 254         fields[1].num_bits = 5;
 255         fields[1].out_value = field1_out;
 256         buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
 257         fields[1].in_value = NULL;
 258         fields[1].check_value = NULL;
 259         fields[1].check_mask = NULL;
 260
 261         fields[2].tap = ice_reg->jtag_info->tap;
 262         fields[2].num_bits = 1;
 263         fields[2].out_value = field2_out;
 264         buf_set_u32(fields[2].out_value, 0, 1, 0);
 265         fields[2].in_value = NULL;
 266         fields[2].check_value = NULL;
 267         fields[2].check_mask = NULL;
 268
 269         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 270
 271         fields[0].in_value = reg->value;
 272         fields[0].check_value = check_value;
 273         fields[0].check_mask = check_mask;
 274
 275         /* when reading the DCC data register, leaving the address field set to
 276          * EICE_COMMS_DATA would read the register twice
 277          * reading the control register is safe
 278          */
 279         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 280
 281         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 282
 283         return ERROR_OK;
 284 }
 285
 286 /* receive <size> words of 32 bit from the DCC
 287  * we pretend the target is always going to be fast enough
 288  * (relative to the JTAG clock), so we don't need to handshake
 289  */
 290 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
 291 {
 292         scan_field_t fields[3];
 293         uint8_t field1_out[1];
 294         uint8_t field2_out[1];
 295
 296         jtag_set_end_state(TAP_IDLE);
 297         arm_jtag_scann(jtag_info, 0x2);
 298         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 299
 300         fields[0].tap = jtag_info->tap;
 301         fields[0].num_bits = 32;
 302         fields[0].out_value = NULL;
 303         fields[0].in_value = NULL;
 304
 305         fields[1].tap = jtag_info->tap;
 306         fields[1].num_bits = 5;
 307         fields[1].out_value = field1_out;
 308         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
 309         fields[1].in_value = NULL;
 310
 311         fields[2].tap = jtag_info->tap;
 312         fields[2].num_bits = 1;
 313         fields[2].out_value = field2_out;
 314         buf_set_u32(fields[2].out_value, 0, 1, 0);
 315         fields[2].in_value = NULL;
 316
 317         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 318
 319         while (size > 0)
 320         {
 321                 /* when reading the last item, set the register address to the DCC control reg,
 322                  * to avoid reading additional data from the DCC data reg
 323                  */
 324                 if (size == 1)
 325                         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 326
 327                 fields[0].in_value = (uint8_t *)data;
 328                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 329                 jtag_add_callback(arm_le_to_h_u32, (uint8_t *)data);
 330
 331                 data++;
 332                 size--;
 333         }
 334
 335         return jtag_execute_queue();
 336 }
 337
 338 int embeddedice_read_reg(reg_t *reg)
 339 {
 340         return embeddedice_read_reg_w_check(reg, NULL, NULL);
 341 }
 342
 343 void embeddedice_set_reg(reg_t *reg, u32 value)
 344 {
 345         embeddedice_write_reg(reg, value);
 346
 347         buf_set_u32(reg->value, 0, reg->size, value);
 348         reg->valid = 1;
 349         reg->dirty = 0;
 350
 351 }
 352
 353 int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf)
 354 {
 355         int retval;
 356         embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 357
 358         if ((retval = jtag_execute_queue()) != ERROR_OK)
 359         {
 360                 LOG_ERROR("register write failed");
 361                 return retval;
 362         }
 363         return ERROR_OK;
 364 }
 365
 366 void embeddedice_write_reg(reg_t *reg, u32 value)
 367 {
 368         embeddedice_reg_t *ice_reg = reg->arch_info;
 369
 370         LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
 371
 372         jtag_set_end_state(TAP_IDLE);
 373         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 374
 375         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 376
 377         uint8_t reg_addr = ice_reg->addr & 0x1f;
 378         embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
 379
 380 }
 381
 382 void embeddedice_store_reg(reg_t *reg)
 383 {
 384         embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 385 }
 386
 387 /* send <size> words of 32 bit to the DCC
 388  * we pretend the target is always going to be fast enough
 389  * (relative to the JTAG clock), so we don't need to handshake
 390  */
 391 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
 392 {
 393         scan_field_t fields[3];
 394         uint8_t field0_out[4];
 395         uint8_t field1_out[1];
 396         uint8_t field2_out[1];
 397
 398         jtag_set_end_state(TAP_IDLE);
 399         arm_jtag_scann(jtag_info, 0x2);
 400         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 401
 402         fields[0].tap = jtag_info->tap;
 403         fields[0].num_bits = 32;
 404         fields[0].out_value = field0_out;
 405         fields[0].in_value = NULL;
 406
 407         fields[1].tap = jtag_info->tap;
 408         fields[1].num_bits = 5;
 409         fields[1].out_value = field1_out;
 410         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
 411         fields[1].in_value = NULL;
 412
 413         fields[2].tap = jtag_info->tap;
 414         fields[2].num_bits = 1;
 415         fields[2].out_value = field2_out;
 416         buf_set_u32(fields[2].out_value, 0, 1, 1);
 417
 418         fields[2].in_value = NULL;
 419
 420         while (size > 0)
 421         {
 422                 buf_set_u32(fields[0].out_value, 0, 32, *data);
 423                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 424
 425                 data++;
 426                 size--;
 427         }
 428
 429         /* call to jtag_execute_queue() intentionally omitted */
 430         return ERROR_OK;
 431 }
 432
 433 /* wait for DCC control register R/W handshake bit to become active
 434  */
 435 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
 436 {
 437         scan_field_t fields[3];
 438         uint8_t field0_in[4];
 439         uint8_t field1_out[1];
 440         uint8_t field2_out[1];
 441         int retval;
 442         u32 hsact;
 443         struct timeval lap;
 444         struct timeval now;
 445
 446         if (hsbit == EICE_COMM_CTRL_WBIT)
 447                 hsact = 1;
 448         else if (hsbit == EICE_COMM_CTRL_RBIT)
 449                 hsact = 0;
 450         else
 451                 return ERROR_INVALID_ARGUMENTS;
 452
 453         jtag_set_end_state(TAP_IDLE);
 454         arm_jtag_scann(jtag_info, 0x2);
 455         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 456
 457         fields[0].tap = jtag_info->tap;
 458         fields[0].num_bits = 32;
 459         fields[0].out_value = NULL;
 460         fields[0].in_value = field0_in;
 461
 462         fields[1].tap = jtag_info->tap;
 463         fields[1].num_bits = 5;
 464         fields[1].out_value = field1_out;
 465         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 466         fields[1].in_value = NULL;
 467
 468         fields[2].tap = jtag_info->tap;
 469         fields[2].num_bits = 1;
 470         fields[2].out_value = field2_out;
 471         buf_set_u32(fields[2].out_value, 0, 1, 0);
 472         fields[2].in_value = NULL;
 473
 474         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 475         gettimeofday(&lap, NULL);
 476         do
 477         {
 478                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 479                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 480                         return retval;
 481
 482                 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
 483                         return ERROR_OK;
 484
 485                 gettimeofday(&now, NULL);
 486         }
 487         while ((u32)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout);
 488
 489         return ERROR_TARGET_TIMEOUT;
 490 }
 491
 492 #ifndef HAVE_JTAG_MINIDRIVER_H
 493 /* this is the inner loop of the open loop DCC write of data to target */
 494 void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, uint8_t *buffer, int little, int count)
 495 {
 496         int i;
 497         for (i = 0; i < count; i++)
 498         {
 499                 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
 500                 buffer += 4;
 501         }
 502 }
 503 #else
 504 /* provided by minidriver */
 505 #endif