1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 /***************************************************************************
28 * CoreSight (Light?) SerialWireJtagDebugPort *
30 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
31 * Cortex-M3(tm) TRM, ARM DDI 0337C *
33 ***************************************************************************/
38 #include "replacements.h"
40 #include "cortex_m3.h"
41 #include "cortex_swjdp.h"
44 #include "time_support.h"
49 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
50 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
51 * result checking until swjdp_end_transaction()
52 * This must be done before using or deallocating any return variables.
53 * swjdp->trans_mode == TRANS_MODE_ATOMIC
54 * All reads and writes to the AHB bus are checked for valid completion, and return values
55 * are immediatley available.
58 /***************************************************************************
60 * DPACC and APACC scanchain access through JTAG-DR *
62 ***************************************************************************/
64 /* Scan out and in from target ordered u8 buffers */
65 int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
67 scan_field_t fields[2];
70 jtag_add_end_state(TAP_IDLE);
71 arm_jtag_set_instr(jtag_info, instr, NULL);
73 fields[0].tap = jtag_info->tap;
74 fields[0].num_bits = 3;
75 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
76 fields[0].out_value = &out_addr_buf;
77 fields[0].out_mask = NULL;
78 fields[0].in_value = ack;
79 fields[0].in_check_value = NULL;
80 fields[0].in_check_mask = NULL;
81 fields[0].in_handler = NULL;
82 fields[0].in_handler_priv = NULL;
84 fields[1].tap = jtag_info->tap;
85 fields[1].num_bits = 32;
86 fields[1].out_value = outvalue;
87 fields[1].out_mask = NULL;
88 fields[1].in_value = invalue;
89 fields[1].in_handler = NULL;
90 fields[1].in_handler_priv = NULL;
91 fields[1].in_check_value = NULL;
92 fields[1].in_check_mask = NULL;
94 jtag_add_dr_scan(2, fields, -1);
99 /* Scan out and in from host ordered u32 variables */
100 int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
102 scan_field_t fields[2];
106 jtag_add_end_state(TAP_IDLE);
107 arm_jtag_set_instr(jtag_info, instr, NULL);
109 fields[0].tap = jtag_info->tap;
110 fields[0].num_bits = 3;
111 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
112 fields[0].out_value = &out_addr_buf;
113 fields[0].out_mask = NULL;
114 fields[0].in_value = ack;
115 fields[0].in_check_value = NULL;
116 fields[0].in_check_mask = NULL;
117 fields[0].in_handler = NULL;
118 fields[0].in_handler_priv = NULL;
120 fields[1].tap = jtag_info->tap;
121 fields[1].num_bits = 32;
122 buf_set_u32(out_value_buf, 0, 32, outvalue);
123 fields[1].out_value = out_value_buf;
124 fields[1].out_mask = NULL;
125 fields[1].in_value = NULL;
128 fields[1].in_handler = arm_jtag_buf_to_u32;
129 fields[1].in_handler_priv = invalue;
133 fields[1].in_handler = NULL;
134 fields[1].in_handler_priv = NULL;
136 fields[1].in_check_value = NULL;
137 fields[1].in_check_mask = NULL;
139 jtag_add_dr_scan(2, fields, -1);
144 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
145 int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
147 swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
148 if ((RnW == DPAP_READ) && (invalue != NULL))
150 swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
153 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
154 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
156 return swjdp_transaction_endcheck(swjdp);
162 int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
164 swjdp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
165 if ((RnW==DPAP_READ) && (invalue != NULL))
167 swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
170 /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
171 if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
173 return swjdp_transaction_endcheck(swjdp);
179 int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
184 /* too expensive to call keep_alive() here */
186 /* Danger!!!! BROKEN!!!! */
187 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
188 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
189 R956 introduced the check on return value here and now Michael Schwingen reports
190 that this code no longer works....
192 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
194 if ((retval=jtag_execute_queue())!=ERROR_OK)
196 LOG_ERROR("BUG: Why does this fail the first time????");
198 /* Why??? second time it works??? */
199 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
200 if ((retval=jtag_execute_queue())!=ERROR_OK)
203 swjdp->ack = swjdp->ack & 0x7;
207 long long then=timeval_ms();
208 while (swjdp->ack != 2)
212 if ((timeval_ms()-then) > 1000)
214 LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
215 return ERROR_JTAG_DEVICE_ERROR;
220 LOG_WARNING("Invalid ACK in SWJDP transaction");
221 return ERROR_JTAG_DEVICE_ERROR;
224 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
225 if ((retval=jtag_execute_queue())!=ERROR_OK)
227 swjdp->ack = swjdp->ack & 0x7;
231 /* common code path avoids fn to timeval_ms() */
234 /* Check for STICKYERR and STICKYORUN */
235 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
237 LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
238 /* Check power to debug regions */
239 if ((ctrlstat & 0xf0000000) != 0xf0000000)
241 ahbap_debugport_init(swjdp);
245 u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr;
247 if (ctrlstat & SSTICKYORUN)
248 LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
250 if (ctrlstat & SSTICKYERR)
251 LOG_ERROR("SWJ-DP STICKY ERROR");
253 /* Clear Sticky Error Bits */
254 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
255 scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
256 if ((retval=jtag_execute_queue())!=ERROR_OK)
259 LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
261 /* Can we find out the reason for the error ?? */
262 ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
263 ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr);
264 ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr);
265 ahbap_read_system_atomic_u32(swjdp, NVIC_BFAR, &nvic_bfar);
266 LOG_ERROR("dcb_dhcsr 0x%x, nvic_shcsr 0x%x, nvic_cfsr 0x%x, nvic_bfar 0x%x", dcb_dhcsr, nvic_shcsr, nvic_cfsr, nvic_bfar);
268 if ((retval=jtag_execute_queue())!=ERROR_OK)
270 return ERROR_JTAG_DEVICE_ERROR;
276 /***************************************************************************
278 * DP and AHB-AP register access through APACC and DPACC *
280 ***************************************************************************/
282 int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
284 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
287 int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
289 return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
292 int swjdp_bankselect_apacc(swjdp_common_t *swjdp,u32 reg_addr)
295 select = (reg_addr & 0xFF0000F0);
297 if (select != swjdp->dp_select_value)
299 swjdp_write_dpacc(swjdp, select, DP_SELECT);
300 swjdp->dp_select_value = select;
306 int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
308 swjdp_bankselect_apacc(swjdp, reg_addr);
309 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
314 int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
316 swjdp_bankselect_apacc(swjdp, reg_addr);
317 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
321 int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
325 buf_set_u32(out_value_buf, 0, 32, value);
326 swjdp_bankselect_apacc(swjdp, reg_addr);
327 scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
332 int ahbap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
334 swjdp_bankselect_apacc(swjdp, reg_addr);
335 scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
340 /***************************************************************************
342 * AHB-AP access to memory and system registers on AHB bus *
344 ***************************************************************************/
346 int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
348 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
349 if (csw != swjdp->ap_csw_value)
351 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
352 ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw );
353 swjdp->ap_csw_value = csw;
355 if (tar != swjdp->ap_tar_value)
357 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
358 ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
359 swjdp->ap_tar_value = tar;
361 if (csw & CSW_ADDRINC_MASK)
363 /* Do not cache TAR value when autoincrementing */
364 swjdp->ap_tar_value = -1;
369 /*****************************************************************************
371 * ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
373 * Read a u32 value from memory or system register *
374 * Functionally equivalent to target_read_u32(target, address, u32 *value), *
375 * but with less overhead *
376 *****************************************************************************/
377 int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
379 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
381 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
382 ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
387 int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
389 ahbap_read_system_u32(swjdp, address, value);
391 return swjdp_transaction_endcheck(swjdp);
394 /*****************************************************************************
396 * ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
398 * Write a u32 value to memory or system register *
400 *****************************************************************************/
401 int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value)
403 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
405 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
406 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
411 int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
413 ahbap_write_system_u32(swjdp, address, value);
415 return swjdp_transaction_endcheck(swjdp);
418 /*****************************************************************************
420 * ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
422 * Write a buffer in target order (little endian) *
424 *****************************************************************************/
425 int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
428 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
430 u8* pBuffer = buffer;
432 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
437 /* if we have an unaligned access - reorder data */
440 for (writecount = 0; writecount < count; writecount++)
443 outvalue = *((u32*)pBuffer);
445 for (i = 0; i < 4; i++ )
447 *((u8*)pBuffer + (adr & 0x3)) = outvalue;
457 /* Adjust to write blocks within 4K aligned boundaries */
458 blocksize = (0x1000 - (0xFFF & address)) >> 2;
459 if (wcount < blocksize)
462 /* handle unaligned data at 4k boundary */
466 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
468 for (writecount = 0; writecount < blocksize; writecount++)
470 ahbap_write_reg(swjdp, AHBAP_DRW, buffer + 4 * writecount );
473 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
475 wcount = wcount - blocksize;
476 address = address + 4 * blocksize;
477 buffer = buffer + 4 * blocksize;
486 LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
487 return ERROR_JTAG_DEVICE_ERROR;
494 int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
497 int retval = ERROR_OK;
498 int wcount, blocksize, writecount, i;
500 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
508 /* Adjust to read within 4K block boundaries */
509 blocksize = (0x1000 - (0xFFF & address)) >> 1;
511 if (wcount < blocksize)
514 /* handle unaligned data at 4k boundary */
518 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
519 writecount = blocksize;
523 nbytes = MIN((writecount << 1), 4);
527 if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
529 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
530 return ERROR_JTAG_DEVICE_ERROR;
533 address += nbytes >> 1;
537 outvalue = *((u32*)buffer);
539 for (i = 0; i < nbytes; i++ )
541 *((u8*)buffer + (address & 0x3)) = outvalue;
546 outvalue = *((u32*)buffer);
547 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
548 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
550 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
551 return ERROR_JTAG_DEVICE_ERROR;
555 buffer += nbytes >> 1;
556 writecount -= nbytes >> 1;
558 } while (writecount);
565 int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
568 int retval = ERROR_OK;
571 return ahbap_write_buf_packed_u16(swjdp, buffer, count, address);
573 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
577 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
578 outvalue = *((u16*)buffer) << 8 * (address & 0x3);
579 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
580 retval = swjdp_transaction_endcheck(swjdp);
589 int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
592 int retval = ERROR_OK;
593 int wcount, blocksize, writecount, i;
595 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
603 /* Adjust to read within 4K block boundaries */
604 blocksize = (0x1000 - (0xFFF & address));
606 if (wcount < blocksize)
609 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
610 writecount = blocksize;
614 nbytes = MIN(writecount, 4);
618 if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
620 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
621 return ERROR_JTAG_DEVICE_ERROR;
628 outvalue = *((u32*)buffer);
630 for (i = 0; i < nbytes; i++ )
632 *((u8*)buffer + (address & 0x3)) = outvalue;
637 outvalue = *((u32*)buffer);
638 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
639 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
641 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
642 return ERROR_JTAG_DEVICE_ERROR;
647 writecount -= nbytes;
649 } while (writecount);
656 int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
659 int retval = ERROR_OK;
662 return ahbap_write_buf_packed_u8(swjdp, buffer, count, address);
664 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
668 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
669 outvalue = *((u8*)buffer) << 8 * (address & 0x3);
670 ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
671 retval = swjdp_transaction_endcheck(swjdp);
680 /*********************************************************************************
682 * ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
684 * Read block fast in target order (little endian) into a buffer *
686 **********************************************************************************/
687 int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
689 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
691 u8* pBuffer = buffer;
693 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
700 /* Adjust to read within 4K block boundaries */
701 blocksize = (0x1000 - (0xFFF & address)) >> 2;
702 if (wcount < blocksize)
705 /* handle unaligned data at 4k boundary */
709 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
711 /* Scan out first read */
712 swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL);
713 for (readcount = 0; readcount < blocksize - 1; readcount++)
715 /* Scan out read instruction and scan in previous value */
716 swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
719 /* Scan in last value */
720 swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
721 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
723 wcount = wcount - blocksize;
724 address += 4 * blocksize;
725 buffer += 4 * blocksize;
734 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
735 return ERROR_JTAG_DEVICE_ERROR;
739 /* if we have an unaligned access - reorder data */
742 for (readcount = 0; readcount < count; readcount++)
745 u32 data = *((u32*)pBuffer);
747 for (i = 0; i < 4; i++ )
749 *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
759 int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
762 int retval = ERROR_OK;
763 int wcount, blocksize, readcount, i;
765 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
773 /* Adjust to read within 4K block boundaries */
774 blocksize = (0x1000 - (0xFFF & address)) >> 1;
775 if (wcount < blocksize)
778 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
780 /* handle unaligned data at 4k boundary */
783 readcount = blocksize;
787 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
788 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
790 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
791 return ERROR_JTAG_DEVICE_ERROR;
794 nbytes = MIN((readcount << 1), 4);
796 for (i = 0; i < nbytes; i++ )
798 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
803 readcount -= (nbytes >> 1);
811 int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
814 int retval = ERROR_OK;
817 return ahbap_read_buf_packed_u16(swjdp, buffer, count, address);
819 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
823 ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
824 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
825 retval = swjdp_transaction_endcheck(swjdp);
828 for (i = 0; i < 2; i++ )
830 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
837 *((u16*)buffer) = (invalue >> 8 * (address & 0x3));
847 int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
850 int retval = ERROR_OK;
851 int wcount, blocksize, readcount, i;
853 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
861 /* Adjust to read within 4K block boundaries */
862 blocksize = (0x1000 - (0xFFF & address));
864 if (wcount < blocksize)
867 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
868 readcount = blocksize;
872 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
873 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
875 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
876 return ERROR_JTAG_DEVICE_ERROR;
879 nbytes = MIN(readcount, 4);
881 for (i = 0; i < nbytes; i++ )
883 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
896 int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
899 int retval = ERROR_OK;
902 return ahbap_read_buf_packed_u8(swjdp, buffer, count, address);
904 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
908 ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
909 ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
910 retval = swjdp_transaction_endcheck(swjdp);
911 *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
920 int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
925 /* because the DCB_DCRDR is used for the emulated dcc channel
926 * we gave to save/restore the DCB_DCRDR when used */
928 ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
930 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
932 /* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
933 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
934 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum );
936 /* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */
937 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
938 ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
940 retval = swjdp_transaction_endcheck(swjdp);
941 ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
945 int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
950 /* because the DCB_DCRDR is used for the emulated dcc channel
951 * we gave to save/restore the DCB_DCRDR when used */
953 ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
955 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
957 /* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
958 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
959 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
961 /* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
962 ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
963 ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
965 retval = swjdp_transaction_endcheck(swjdp);
966 ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
970 int ahbap_debugport_init(swjdp_common_t *swjdp)
972 u32 idreg, romaddr, dummy;
979 swjdp->ap_csw_value = -1;
980 swjdp->ap_tar_value = -1;
981 swjdp->trans_mode = TRANS_MODE_ATOMIC;
982 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
983 swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT);
984 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
986 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
988 swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
989 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
990 if ((retval=jtag_execute_queue())!=ERROR_OK)
993 /* Check that we have debug power domains activated */
994 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
996 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
997 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
998 if ((retval=jtag_execute_queue())!=ERROR_OK)
1003 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1005 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
1006 swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
1007 if ((retval=jtag_execute_queue())!=ERROR_OK)
1012 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
1013 /* With debug power on we can activate OVERRUN checking */
1014 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1015 swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1016 swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
1018 ahbap_read_reg_u32(swjdp, 0xFC, &idreg);
1019 ahbap_read_reg_u32(swjdp, 0xF8, &romaddr);
1021 LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);