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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "breakpoints.h"
  35 #include "cortex_m3.h"
  36 #include "target_request.h"
  37 #include "target_type.h"
  38 #include "arm_disassembler.h"
  39 #include "register.h"
  40 #include "arm_opcodes.h"
  41 #include "arm_semihosting.h"
  42
  43 /* NOTE:  most of this should work fine for the Cortex-M1 and
  44  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  45  * Some differences:  M0/M1 doesn't have FBP remapping or the
  46  * DWT tracing/profiling support.  (So the cycle counter will
  47  * not be usable; the other stuff isn't currently used here.)
  48  *
  49  * Although there are some workarounds for errata seen only in r0p0
  50  * silicon, such old parts are hard to find and thus not much tested
  51  * any longer.
  52  */
  53
  54
  55 /* forward declarations */
  56 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
  57 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
  58 static void cortex_m3_enable_watchpoints(struct target *target);
  59 static int cortex_m3_store_core_reg_u32(struct target *target,
  60                 enum armv7m_regtype type, uint32_t num, uint32_t value);
  61
  62 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
  63                 uint32_t *value, int regnum)
  64 {
  65         int retval;
  66         uint32_t dcrdr;
  67
  68         /* because the DCB_DCRDR is used for the emulated dcc channel
  69          * we have to save/restore the DCB_DCRDR when used */
  70
  71         retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  72         if (retval != ERROR_OK)
  73                 return retval;
  74
  75         /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  76         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  77         if (retval != ERROR_OK)
  78                 return retval;
  79         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  80         if (retval != ERROR_OK)
  81                 return retval;
  82
  83         /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  84         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  85         if (retval != ERROR_OK)
  86                 return retval;
  87         retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  88         if (retval != ERROR_OK)
  89                 return retval;
  90
  91         retval = dap_run(swjdp);
  92         if (retval != ERROR_OK)
  93                 return retval;
  94
  95         /* restore DCB_DCRDR - this needs to be in a seperate
  96          * transaction otherwise the emulated DCC channel breaks */
  97         if (retval == ERROR_OK)
  98                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  99
 100         return retval;
 101 }
 102
 103 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
 104                 uint32_t value, int regnum)
 105 {
 106         int retval;
 107         uint32_t dcrdr;
 108
 109         /* because the DCB_DCRDR is used for the emulated dcc channel
 110          * we have to save/restore the DCB_DCRDR when used */
 111
 112         retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 113         if (retval != ERROR_OK)
 114                 return retval;
 115
 116         /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
 117         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 118         if (retval != ERROR_OK)
 119                 return retval;
 120         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 121         // XXX check retval
 122
 123         /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
 124         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 125         if (retval != ERROR_OK)
 126                 return retval;
 127         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 128         // XXX check retval
 129
 130         retval = dap_run(swjdp);
 131
 132         /* restore DCB_DCRDR - this needs to be in a seperate
 133          * transaction otherwise the emulated DCC channel breaks */
 134         if (retval == ERROR_OK)
 135                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 136
 137         return retval;
 138 }
 139
 140 static int cortex_m3_write_debug_halt_mask(struct target *target,
 141                 uint32_t mask_on, uint32_t mask_off)
 142 {
 143         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 144         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 145
 146         /* mask off status bits */
 147         cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 148         /* create new register mask */
 149         cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 150
 151         return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
 152 }
 153
 154 static int cortex_m3_clear_halt(struct target *target)
 155 {
 156         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 157         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 158         int retval;
 159
 160         /* clear step if any */
 161         cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 162
 163         /* Read Debug Fault Status Register */
 164         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 165         if (retval != ERROR_OK)
 166                 return retval;
 167
 168         /* Clear Debug Fault Status */
 169         retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
 170         if (retval != ERROR_OK)
 171                 return retval;
 172         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 173
 174         return ERROR_OK;
 175 }
 176
 177 static int cortex_m3_single_step_core(struct target *target)
 178 {
 179         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 180         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 181         uint32_t dhcsr_save;
 182         int retval;
 183
 184         /* backup dhcsr reg */
 185         dhcsr_save = cortex_m3->dcb_dhcsr;
 186
 187         /* Mask interrupts before clearing halt, if done already.  This avoids
 188          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 189          * HALT can put the core into an unknown state.
 190          */
 191         if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
 192         {
 193                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 194                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 195                 if (retval != ERROR_OK)
 196                         return retval;
 197         }
 198         retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 199                                 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 200         if (retval != ERROR_OK)
 201                 return retval;
 202         LOG_DEBUG(" ");
 203
 204         /* restore dhcsr reg */
 205         cortex_m3->dcb_dhcsr = dhcsr_save;
 206         cortex_m3_clear_halt(target);
 207
 208         return ERROR_OK;
 209 }
 210
 211 static int cortex_m3_endreset_event(struct target *target)
 212 {
 213         int i;
 214         int retval;
 215         uint32_t dcb_demcr;
 216         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 217         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 218         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 219         struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 220         struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 221
 222         /* REVISIT The four debug monitor bits are currently ignored... */
 223         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 224         if (retval != ERROR_OK)
 225                 return retval;
 226         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 227
 228         /* this register is used for emulated dcc channel */
 229         retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 230         if (retval != ERROR_OK)
 231                 return retval;
 232
 233         /* Enable debug requests */
 234         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 235         if (retval != ERROR_OK)
 236                 return retval;
 237         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 238         {
 239                 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 240                 if (retval != ERROR_OK)
 241                         return retval;
 242         }
 243
 244         /* clear any interrupt masking */
 245         cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
 246
 247         /* Enable features controlled by ITM and DWT blocks, and catch only
 248          * the vectors we were told to pay attention to.
 249          *
 250          * Target firmware is responsible for all fault handling policy
 251          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 252          * or manual updates to the NVIC SHCSR and CCR registers.
 253          */
 254         retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
 255         if (retval != ERROR_OK)
 256                 return retval;
 257
 258         /* Paranoia: evidently some (early?) chips don't preserve all the
 259          * debug state (including FBP, DWT, etc) across reset...
 260          */
 261
 262         /* Enable FPB */
 263         retval = target_write_u32(target, FP_CTRL, 3);
 264         if (retval != ERROR_OK)
 265                 return retval;
 266
 267         cortex_m3->fpb_enabled = 1;
 268
 269         /* Restore FPB registers */
 270         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
 271         {
 272                 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 273                 if (retval != ERROR_OK)
 274                         return retval;
 275         }
 276
 277         /* Restore DWT registers */
 278         for (i = 0; i < cortex_m3->dwt_num_comp; i++)
 279         {
 280                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 281                                 dwt_list[i].comp);
 282                 if (retval != ERROR_OK)
 283                         return retval;
 284                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 285                                 dwt_list[i].mask);
 286                 if (retval != ERROR_OK)
 287                         return retval;
 288                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 289                                 dwt_list[i].function);
 290                 if (retval != ERROR_OK)
 291                         return retval;
 292         }
 293         retval = dap_run(swjdp);
 294         if (retval != ERROR_OK)
 295                 return retval;
 296
 297         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 298
 299         /* make sure we have latest dhcsr flags */
 300         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 301
 302         return retval;
 303 }
 304
 305 static int cortex_m3_examine_debug_reason(struct target *target)
 306 {
 307         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 308
 309         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
 310         /* only check the debug reason if we don't know it already */
 311
 312         if ((target->debug_reason != DBG_REASON_DBGRQ)
 313                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 314         {
 315                 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 316                 {
 317                         target->debug_reason = DBG_REASON_BREAKPOINT;
 318                         if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 319                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 320                 }
 321                 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 322                         target->debug_reason = DBG_REASON_WATCHPOINT;
 323                 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
 324                         target->debug_reason = DBG_REASON_BREAKPOINT;
 325                 else /* EXTERNAL, HALTED */
 326                         target->debug_reason = DBG_REASON_UNDEFINED;
 327         }
 328
 329         return ERROR_OK;
 330 }
 331
 332 static int cortex_m3_examine_exception_reason(struct target *target)
 333 {
 334         uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
 335         struct armv7m_common *armv7m = target_to_armv7m(target);
 336         struct adiv5_dap *swjdp = &armv7m->dap;
 337         int retval;
 338
 339         retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 340         if (retval != ERROR_OK)
 341                 return retval;
 342         switch (armv7m->exception_number)
 343         {
 344                 case 2: /* NMI */
 345                         break;
 346                 case 3: /* Hard Fault */
 347                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 348                         if (retval != ERROR_OK)
 349                                 return retval;
 350                         if (except_sr & 0x40000000)
 351                         {
 352                                 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
 353                                 if (retval != ERROR_OK)
 354                                         return retval;
 355                         }
 356                         break;
 357                 case 4: /* Memory Management */
 358                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 359                         if (retval != ERROR_OK)
 360                                 return retval;
 361                         retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
 362                         if (retval != ERROR_OK)
 363                                 return retval;
 364                         break;
 365                 case 5: /* Bus Fault */
 366                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 367                         if (retval != ERROR_OK)
 368                                 return retval;
 369                         retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
 370                         if (retval != ERROR_OK)
 371                                 return retval;
 372                         break;
 373                 case 6: /* Usage Fault */
 374                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 375                         if (retval != ERROR_OK)
 376                                 return retval;
 377                         break;
 378                 case 11:        /* SVCall */
 379                         break;
 380                 case 12:        /* Debug Monitor */
 381                         retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
 382                         if (retval != ERROR_OK)
 383                                 return retval;
 384                         break;
 385                 case 14:        /* PendSV */
 386                         break;
 387                 case 15:        /* SysTick */
 388                         break;
 389                 default:
 390                         except_sr = 0;
 391                         break;
 392         }
 393         retval = dap_run(swjdp);
 394         if (retval == ERROR_OK)
 395                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 396                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 397                         armv7m_exception_string(armv7m->exception_number),
 398                         shcsr, except_sr, cfsr, except_ar);
 399         return retval;
 400 }
 401
 402 /* PSP is used in some thread modes */
 403 static const int armv7m_psp_reg_map[17] = {
 404         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 405         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 406         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 407         ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
 408         ARMV7M_xPSR,
 409 };
 410
 411 /* MSP is used in handler and some thread modes */
 412 static const int armv7m_msp_reg_map[17] = {
 413         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 414         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 415         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 416         ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
 417         ARMV7M_xPSR,
 418 };
 419
 420 static int cortex_m3_debug_entry(struct target *target)
 421 {
 422         int i;
 423         uint32_t xPSR;
 424         int retval;
 425         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 426         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 427         struct arm *arm = &armv7m->arm;
 428         struct adiv5_dap *swjdp = &armv7m->dap;
 429         struct reg *r;
 430
 431         LOG_DEBUG(" ");
 432
 433         cortex_m3_clear_halt(target);
 434         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 435         if (retval != ERROR_OK)
 436                 return retval;
 437
 438         if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
 439                 return retval;
 440
 441         /* Examine target state and mode */
 442         /* First load register acessible through core debug port*/
 443         int num_regs = armv7m->core_cache->num_regs;
 444
 445         for (i = 0; i < num_regs; i++)
 446         {
 447                 if (!armv7m->core_cache->reg_list[i].valid)
 448                         armv7m->read_core_reg(target, i);
 449         }
 450
 451         r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 452         xPSR = buf_get_u32(r->value, 0, 32);
 453
 454 #ifdef ARMV7_GDB_HACKS
 455         /* FIXME this breaks on scan chains with more than one Cortex-M3.
 456          * Instead, each CM3 should have its own dummy value...
 457          */
 458         /* copy real xpsr reg for gdb, setting thumb bit */
 459         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
 460         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
 461         armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
 462         armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
 463 #endif
 464
 465         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 466         if (xPSR & 0xf00)
 467         {
 468                 r->dirty = r->valid;
 469                 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 470         }
 471
 472         /* Are we in an exception handler */
 473         if (xPSR & 0x1FF)
 474         {
 475                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 476                 armv7m->exception_number = (xPSR & 0x1FF);
 477
 478                 arm->core_mode = ARM_MODE_HANDLER;
 479                 arm->map = armv7m_msp_reg_map;
 480         }
 481         else
 482         {
 483                 unsigned control = buf_get_u32(armv7m->core_cache
 484                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 485
 486                 /* is this thread privileged? */
 487                 armv7m->core_mode = control & 1;
 488                 arm->core_mode = armv7m->core_mode
 489                                 ? ARM_MODE_USER_THREAD
 490                                 : ARM_MODE_THREAD;
 491
 492                 /* which stack is it using? */
 493                 if (control & 2)
 494                         arm->map = armv7m_psp_reg_map;
 495                 else
 496                         arm->map = armv7m_msp_reg_map;
 497
 498                 armv7m->exception_number = 0;
 499         }
 500
 501         if (armv7m->exception_number)
 502         {
 503                 cortex_m3_examine_exception_reason(target);
 504         }
 505
 506         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 507                 armv7m_mode_strings[armv7m->core_mode],
 508                 *(uint32_t*)(arm->pc->value),
 509                 target_state_name(target));
 510
 511         if (armv7m->post_debug_entry)
 512         {
 513                 retval = armv7m->post_debug_entry(target);
 514                 if (retval != ERROR_OK)
 515                         return retval;
 516         }
 517
 518         return ERROR_OK;
 519 }
 520
 521 static int cortex_m3_poll(struct target *target)
 522 {
 523         int detected_failure = ERROR_OK;
 524         int retval = ERROR_OK;
 525         enum target_state prev_target_state = target->state;
 526         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 527         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 528
 529         /* Read from Debug Halting Control and Status Register */
 530         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 531         if (retval != ERROR_OK)
 532         {
 533                 target->state = TARGET_UNKNOWN;
 534                 return retval;
 535         }
 536
 537         /* Recover from lockup.  See ARMv7-M architecture spec,
 538          * section B1.5.15 "Unrecoverable exception cases".
 539          */
 540         if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
 541                 LOG_ERROR("%s -- clearing lockup after double fault",
 542                                 target_name(target));
 543                 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 544                 target->debug_reason = DBG_REASON_DBGRQ;
 545
 546                 /* We have to execute the rest (the "finally" equivalent, but
 547                  * still throw this exception again).
 548                  */
 549                 detected_failure = ERROR_FAIL;
 550
 551                 /* refresh status bits */
 552                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 553                 if (retval != ERROR_OK)
 554                         return retval;
 555         }
 556
 557         if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 558         {
 559                 /* check if still in reset */
 560                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 561                 if (retval != ERROR_OK)
 562                         return retval;
 563
 564                 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 565                 {
 566                         target->state = TARGET_RESET;
 567                         return ERROR_OK;
 568                 }
 569         }
 570
 571         if (target->state == TARGET_RESET)
 572         {
 573                 /* Cannot switch context while running so endreset is
 574                  * called with target->state == TARGET_RESET
 575                  */
 576                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 577                                 cortex_m3->dcb_dhcsr);
 578                 cortex_m3_endreset_event(target);
 579                 target->state = TARGET_RUNNING;
 580                 prev_target_state = TARGET_RUNNING;
 581         }
 582
 583         if (cortex_m3->dcb_dhcsr & S_HALT)
 584         {
 585                 target->state = TARGET_HALTED;
 586
 587                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 588                 {
 589                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 590                                 return retval;
 591
 592                         if (arm_semihosting(target, &retval) != 0)
 593                                 return retval;
 594
 595                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 596                 }
 597                 if (prev_target_state == TARGET_DEBUG_RUNNING)
 598                 {
 599                         LOG_DEBUG(" ");
 600                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 601                                 return retval;
 602
 603                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 604                 }
 605         }
 606
 607         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 608          * How best to model low power modes?
 609          */
 610
 611         if (target->state == TARGET_UNKNOWN)
 612         {
 613                 /* check if processor is retiring instructions */
 614                 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
 615                 {
 616                         target->state = TARGET_RUNNING;
 617                         retval = ERROR_OK;
 618                 }
 619         }
 620
 621         /* Did we detect a failure condition that we cleared? */
 622         if (detected_failure != ERROR_OK)
 623                 retval = detected_failure;
 624         return retval;
 625 }
 626
 627 static int cortex_m3_halt(struct target *target)
 628 {
 629         LOG_DEBUG("target->state: %s",
 630                 target_state_name(target));
 631
 632         if (target->state == TARGET_HALTED)
 633         {
 634                 LOG_DEBUG("target was already halted");
 635                 return ERROR_OK;
 636         }
 637
 638         if (target->state == TARGET_UNKNOWN)
 639         {
 640                 LOG_WARNING("target was in unknown state when halt was requested");
 641         }
 642
 643         if (target->state == TARGET_RESET)
 644         {
 645                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
 646                 {
 647                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 648                         return ERROR_TARGET_FAILURE;
 649                 }
 650                 else
 651                 {
 652                         /* we came here in a reset_halt or reset_init sequence
 653                          * debug entry was already prepared in cortex_m3_prepare_reset_halt()
 654                          */
 655                         target->debug_reason = DBG_REASON_DBGRQ;
 656
 657                         return ERROR_OK;
 658                 }
 659         }
 660
 661         /* Write to Debug Halting Control and Status Register */
 662         cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 663
 664         target->debug_reason = DBG_REASON_DBGRQ;
 665
 666         return ERROR_OK;
 667 }
 668
 669 static int cortex_m3_soft_reset_halt(struct target *target)
 670 {
 671         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 672         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 673         uint32_t dcb_dhcsr = 0;
 674         int retval, timeout = 0;
 675
 676         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 677         retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
 678                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 679         if (retval != ERROR_OK)
 680                 return retval;
 681
 682         /* Request a core-only reset */
 683         retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 684                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 685         if (retval != ERROR_OK)
 686                 return retval;
 687         target->state = TARGET_RESET;
 688
 689         /* registers are now invalid */
 690         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 691
 692         while (timeout < 100)
 693         {
 694                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 695                 if (retval == ERROR_OK)
 696                 {
 697                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
 698                                         &cortex_m3->nvic_dfsr);
 699                         if (retval != ERROR_OK)
 700                                 return retval;
 701                         if ((dcb_dhcsr & S_HALT)
 702                                         && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 703                         {
 704                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 705                                         "DFSR 0x%08x",
 706                                         (unsigned) dcb_dhcsr,
 707                                         (unsigned) cortex_m3->nvic_dfsr);
 708                                 cortex_m3_poll(target);
 709                                 /* FIXME restore user's vector catch config */
 710                                 return ERROR_OK;
 711                         }
 712                         else
 713                                 LOG_DEBUG("waiting for system reset-halt, "
 714                                         "DHCSR 0x%08x, %d ms",
 715                                         (unsigned) dcb_dhcsr, timeout);
 716                 }
 717                 timeout++;
 718                 alive_sleep(1);
 719         }
 720
 721         return ERROR_OK;
 722 }
 723
 724 static void cortex_m3_enable_breakpoints(struct target *target)
 725 {
 726         struct breakpoint *breakpoint = target->breakpoints;
 727
 728         /* set any pending breakpoints */
 729         while (breakpoint)
 730         {
 731                 if (!breakpoint->set)
 732                         cortex_m3_set_breakpoint(target, breakpoint);
 733                 breakpoint = breakpoint->next;
 734         }
 735 }
 736
 737 static int cortex_m3_resume(struct target *target, int current,
 738                 uint32_t address, int handle_breakpoints, int debug_execution)
 739 {
 740         struct armv7m_common *armv7m = target_to_armv7m(target);
 741         struct breakpoint *breakpoint = NULL;
 742         uint32_t resume_pc;
 743         struct reg *r;
 744
 745         if (target->state != TARGET_HALTED)
 746         {
 747                 LOG_WARNING("target not halted");
 748                 return ERROR_TARGET_NOT_HALTED;
 749         }
 750
 751         if (!debug_execution)
 752         {
 753                 target_free_all_working_areas(target);
 754                 cortex_m3_enable_breakpoints(target);
 755                 cortex_m3_enable_watchpoints(target);
 756         }
 757
 758         if (debug_execution)
 759         {
 760                 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
 761
 762                 /* Disable interrupts */
 763                 /* We disable interrupts in the PRIMASK register instead of
 764                  * masking with C_MASKINTS.  This is probably the same issue
 765                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 766                  * in parallel with disabled interrupts can cause local faults
 767                  * to not be taken.
 768                  *
 769                  * REVISIT this clearly breaks non-debug execution, since the
 770                  * PRIMASK register state isn't saved/restored...  workaround
 771                  * by never resuming app code after debug execution.
 772                  */
 773                 buf_set_u32(r->value, 0, 1, 1);
 774                 r->dirty = true;
 775                 r->valid = true;
 776
 777                 /* Make sure we are in Thumb mode */
 778                 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 779                 buf_set_u32(r->value, 24, 1, 1);
 780                 r->dirty = true;
 781                 r->valid = true;
 782         }
 783
 784         /* current = 1: continue on current pc, otherwise continue at <address> */
 785         r = armv7m->arm.pc;
 786         if (!current)
 787         {
 788                 buf_set_u32(r->value, 0, 32, address);
 789                 r->dirty = true;
 790                 r->valid = true;
 791         }
 792
 793         /* if we halted last time due to a bkpt instruction
 794          * then we have to manually step over it, otherwise
 795          * the core will break again */
 796
 797         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 798                         && !debug_execution)
 799         {
 800                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 801         }
 802
 803         resume_pc = buf_get_u32(r->value, 0, 32);
 804
 805         armv7m_restore_context(target);
 806
 807         /* the front-end may request us not to handle breakpoints */
 808         if (handle_breakpoints)
 809         {
 810                 /* Single step past breakpoint at current address */
 811                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 812                 {
 813                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 814                                           breakpoint->address,
 815                                           breakpoint->unique_id);
 816                         cortex_m3_unset_breakpoint(target, breakpoint);
 817                         cortex_m3_single_step_core(target);
 818                         cortex_m3_set_breakpoint(target, breakpoint);
 819                 }
 820         }
 821
 822         /* Restart core */
 823         cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 824
 825         target->debug_reason = DBG_REASON_NOTHALTED;
 826
 827         /* registers are now invalid */
 828         register_cache_invalidate(armv7m->core_cache);
 829
 830         if (!debug_execution)
 831         {
 832                 target->state = TARGET_RUNNING;
 833                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 834                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 835         }
 836         else
 837         {
 838                 target->state = TARGET_DEBUG_RUNNING;
 839                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 840                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 841         }
 842
 843         return ERROR_OK;
 844 }
 845
 846 /* int irqstepcount = 0; */
 847 static int cortex_m3_step(struct target *target, int current,
 848                 uint32_t address, int handle_breakpoints)
 849 {
 850         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 851         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 852         struct adiv5_dap *swjdp = &armv7m->dap;
 853         struct breakpoint *breakpoint = NULL;
 854         struct reg *pc = armv7m->arm.pc;
 855         bool bkpt_inst_found = false;
 856
 857         if (target->state != TARGET_HALTED)
 858         {
 859                 LOG_WARNING("target not halted");
 860                 return ERROR_TARGET_NOT_HALTED;
 861         }
 862
 863         /* current = 1: continue on current pc, otherwise continue at <address> */
 864         if (!current)
 865                 buf_set_u32(pc->value, 0, 32, address);
 866
 867         /* the front-end may request us not to handle breakpoints */
 868         if (handle_breakpoints) {
 869                 breakpoint = breakpoint_find(target,
 870                                 buf_get_u32(pc->value, 0, 32));
 871                 if (breakpoint)
 872                         cortex_m3_unset_breakpoint(target, breakpoint);
 873         }
 874
 875         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 876
 877         target->debug_reason = DBG_REASON_SINGLESTEP;
 878
 879         armv7m_restore_context(target);
 880
 881         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 882
 883         /* if no bkpt instruction is found at pc then we can perform
 884          * a normal step, otherwise we have to manually step over the bkpt
 885          * instruction - as such simulate a step */
 886         if (bkpt_inst_found == false)
 887         {
 888                 /* set step and clear halt */
 889                 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 890         }
 891
 892         int retval;
 893         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 894         if (retval != ERROR_OK)
 895                 return retval;
 896
 897         /* registers are now invalid */
 898         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 899
 900         if (breakpoint)
 901                 cortex_m3_set_breakpoint(target, breakpoint);
 902
 903         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 904                         " nvic_icsr = 0x%" PRIx32,
 905                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 906
 907         retval = cortex_m3_debug_entry(target);
 908         if (retval != ERROR_OK)
 909                 return retval;
 910         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 911
 912         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 913                         " nvic_icsr = 0x%" PRIx32,
 914                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 915
 916         return ERROR_OK;
 917 }
 918
 919 static int cortex_m3_assert_reset(struct target *target)
 920 {
 921         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 922         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 923         enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
 924
 925         LOG_DEBUG("target->state: %s",
 926                 target_state_name(target));
 927
 928         enum reset_types jtag_reset_config = jtag_get_reset_config();
 929
 930         /* Enable debug requests */
 931         int retval;
 932         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 933         if (retval != ERROR_OK)
 934                 return retval;
 935         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 936         {
 937                 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 938                 if (retval != ERROR_OK)
 939                         return retval;
 940         }
 941
 942         retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 943         if (retval != ERROR_OK)
 944                 return retval;
 945
 946         if (!target->reset_halt)
 947         {
 948                 /* Set/Clear C_MASKINTS in a separate operation */
 949                 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
 950                 {
 951                         retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 952                                         DBGKEY | C_DEBUGEN | C_HALT);
 953                         if (retval != ERROR_OK)
 954                                 return retval;
 955                 }
 956
 957                 /* clear any debug flags before resuming */
 958                 cortex_m3_clear_halt(target);
 959
 960                 /* clear C_HALT in dhcsr reg */
 961                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 962         }
 963         else
 964         {
 965                 /* Halt in debug on reset; endreset_event() restores DEMCR.
 966                  *
 967                  * REVISIT catching BUSERR presumably helps to defend against
 968                  * bad vector table entries.  Should this include MMERR or
 969                  * other flags too?
 970                  */
 971                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
 972                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 973                 if (retval != ERROR_OK)
 974                         return retval;
 975         }
 976
 977         if (jtag_reset_config & RESET_HAS_SRST)
 978         {
 979                 /* default to asserting srst */
 980                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 981                 {
 982                         jtag_add_reset(1, 1);
 983                 }
 984                 else
 985                 {
 986                         jtag_add_reset(0, 1);
 987                 }
 988         }
 989         else
 990         {
 991                 /* Use a standard Cortex-M3 software reset mechanism.
 992                  * We default to using VECRESET as it is supported on all current cores.
 993                  * This has the disadvantage of not resetting the peripherals, so a
 994                  * reset-init event handler is needed to perform any peripheral resets.
 995                  */
 996                 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 997                                 AIRCR_VECTKEY | ((reset_config == CORTEX_M3_RESET_SYSRESETREQ)
 998                                 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
 999                 if (retval != ERROR_OK)
1000                         return retval;
1001
1002                 LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
1003                                 ? "SYSRESETREQ" : "VECTRESET");
1004
1005                 if (reset_config == CORTEX_M3_RESET_VECTRESET) {
1006                         LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
1007                                         "handler to reset any peripherals");
1008                 }
1009
1010                 {
1011                         /* I do not know why this is necessary, but it
1012                          * fixes strange effects (step/resume cause NMI
1013                          * after reset) on LM3S6918 -- Michael Schwingen
1014                          */
1015                         uint32_t tmp;
1016                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
1017                         if (retval != ERROR_OK)
1018                                 return retval;
1019                 }
1020         }
1021
1022         target->state = TARGET_RESET;
1023         jtag_add_sleep(50000);
1024
1025         register_cache_invalidate(cortex_m3->armv7m.core_cache);
1026
1027         if (target->reset_halt)
1028         {
1029                 if ((retval = target_halt(target)) != ERROR_OK)
1030                         return retval;
1031         }
1032
1033         return ERROR_OK;
1034 }
1035
1036 static int cortex_m3_deassert_reset(struct target *target)
1037 {
1038         LOG_DEBUG("target->state: %s",
1039                 target_state_name(target));
1040
1041         /* deassert reset lines */
1042         jtag_add_reset(0, 0);
1043
1044         return ERROR_OK;
1045 }
1046
1047 static int
1048 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1049 {
1050         int retval;
1051         int fp_num = 0;
1052         uint32_t hilo;
1053         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1054         struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
1055
1056         if (breakpoint->set)
1057         {
1058                 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
1059                 return ERROR_OK;
1060         }
1061
1062         if (cortex_m3->auto_bp_type)
1063         {
1064                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1065         }
1066
1067         if (breakpoint->type == BKPT_HARD)
1068         {
1069                 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
1070                         fp_num++;
1071                 if (fp_num >= cortex_m3->fp_num_code)
1072                 {
1073                         LOG_ERROR("Can not find free FPB Comparator!");
1074                         return ERROR_FAIL;
1075                 }
1076                 breakpoint->set = fp_num + 1;
1077                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1078                 comparator_list[fp_num].used = 1;
1079                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1080                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1081                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
1082                 if (!cortex_m3->fpb_enabled)
1083                 {
1084                         LOG_DEBUG("FPB wasn't enabled, do it now");
1085                         target_write_u32(target, FP_CTRL, 3);
1086                 }
1087         }
1088         else if (breakpoint->type == BKPT_SOFT)
1089         {
1090                 uint8_t code[4];
1091
1092                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1093                  * semihosting; don't use that.  Otherwise the BKPT
1094                  * parameter is arbitrary.
1095                  */
1096                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1097                 retval = target_read_memory(target,
1098                                 breakpoint->address & 0xFFFFFFFE,
1099                                 breakpoint->length, 1,
1100                                 breakpoint->orig_instr);
1101                 if (retval != ERROR_OK)
1102                         return retval;
1103                 retval = target_write_memory(target,
1104                                 breakpoint->address & 0xFFFFFFFE,
1105                                 breakpoint->length, 1,
1106                                 code);
1107                 if (retval != ERROR_OK)
1108                         return retval;
1109                 breakpoint->set = true;
1110         }
1111
1112         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1113                           breakpoint->unique_id,
1114                           (int)(breakpoint->type),
1115                           breakpoint->address,
1116                           breakpoint->length,
1117                           breakpoint->set);
1118
1119         return ERROR_OK;
1120 }
1121
1122 static int
1123 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1124 {
1125         int retval;
1126         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1127         struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
1128
1129         if (!breakpoint->set)
1130         {
1131                 LOG_WARNING("breakpoint not set");
1132                 return ERROR_OK;
1133         }
1134
1135         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1136                           breakpoint->unique_id,
1137                           (int)(breakpoint->type),
1138                           breakpoint->address,
1139                           breakpoint->length,
1140                           breakpoint->set);
1141
1142         if (breakpoint->type == BKPT_HARD)
1143         {
1144                 int fp_num = breakpoint->set - 1;
1145                 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
1146                 {
1147                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1148                         return ERROR_OK;
1149                 }
1150                 comparator_list[fp_num].used = 0;
1151                 comparator_list[fp_num].fpcr_value = 0;
1152                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1153         }
1154         else
1155         {
1156                 /* restore original instruction (kept in target endianness) */
1157                 if (breakpoint->length == 4)
1158                 {
1159                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1160                         {
1161                                 return retval;
1162                         }
1163                 }
1164                 else
1165                 {
1166                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1167                         {
1168                                 return retval;
1169                         }
1170                 }
1171         }
1172         breakpoint->set = false;
1173
1174         return ERROR_OK;
1175 }
1176
1177 static int
1178 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1179 {
1180         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1181
1182         if (cortex_m3->auto_bp_type)
1183         {
1184                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1185 #ifdef ARMV7_GDB_HACKS
1186                 if (breakpoint->length != 2) {
1187                         /* XXX Hack: Replace all breakpoints with length != 2 with
1188                          * a hardware breakpoint. */
1189                         breakpoint->type = BKPT_HARD;
1190                         breakpoint->length = 2;
1191                 }
1192 #endif
1193         }
1194
1195         if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
1196         {
1197                 LOG_INFO("flash patch comparator requested outside code memory region");
1198                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1199         }
1200
1201         if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
1202         {
1203                 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1204                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1205         }
1206
1207         if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1208         {
1209                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1210                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1211         }
1212
1213         if ((breakpoint->length != 2))
1214         {
1215                 LOG_INFO("only breakpoints of two bytes length supported");
1216                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1217         }
1218
1219         if (breakpoint->type == BKPT_HARD)
1220                 cortex_m3->fp_code_available--;
1221
1222         return cortex_m3_set_breakpoint(target, breakpoint);
1223 }
1224
1225 static int
1226 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1227 {
1228         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1229
1230         /* REVISIT why check? FBP can be updated with core running ... */
1231         if (target->state != TARGET_HALTED)
1232         {
1233                 LOG_WARNING("target not halted");
1234                 return ERROR_TARGET_NOT_HALTED;
1235         }
1236
1237         if (cortex_m3->auto_bp_type)
1238         {
1239                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1240         }
1241
1242         if (breakpoint->set)
1243         {
1244                 cortex_m3_unset_breakpoint(target, breakpoint);
1245         }
1246
1247         if (breakpoint->type == BKPT_HARD)
1248                 cortex_m3->fp_code_available++;
1249
1250         return ERROR_OK;
1251 }
1252
1253 static int
1254 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1255 {
1256         int dwt_num = 0;
1257         uint32_t mask, temp;
1258         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1259
1260         /* watchpoint params were validated earlier */
1261         mask = 0;
1262         temp = watchpoint->length;
1263         while (temp) {
1264                 temp >>= 1;
1265                 mask++;
1266         }
1267         mask--;
1268
1269         /* REVISIT Don't fully trust these "not used" records ... users
1270          * may set up breakpoints by hand, e.g. dual-address data value
1271          * watchpoint using comparator #1; comparator #0 matching cycle
1272          * count; send data trace info through ITM and TPIU; etc
1273          */
1274         struct cortex_m3_dwt_comparator *comparator;
1275
1276         for (comparator = cortex_m3->dwt_comparator_list;
1277                         comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1278                         comparator++, dwt_num++)
1279                 continue;
1280         if (dwt_num >= cortex_m3->dwt_num_comp)
1281         {
1282                 LOG_ERROR("Can not find free DWT Comparator");
1283                 return ERROR_FAIL;
1284         }
1285         comparator->used = 1;
1286         watchpoint->set = dwt_num + 1;
1287
1288         comparator->comp = watchpoint->address;
1289         target_write_u32(target, comparator->dwt_comparator_address + 0,
1290                         comparator->comp);
1291
1292         comparator->mask = mask;
1293         target_write_u32(target, comparator->dwt_comparator_address + 4,
1294                         comparator->mask);
1295
1296         switch (watchpoint->rw) {
1297         case WPT_READ:
1298                 comparator->function = 5;
1299                 break;
1300         case WPT_WRITE:
1301                 comparator->function = 6;
1302                 break;
1303         case WPT_ACCESS:
1304                 comparator->function = 7;
1305                 break;
1306         }
1307         target_write_u32(target, comparator->dwt_comparator_address + 8,
1308                         comparator->function);
1309
1310         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1311                         watchpoint->unique_id, dwt_num,
1312                         (unsigned) comparator->comp,
1313                         (unsigned) comparator->mask,
1314                         (unsigned) comparator->function);
1315         return ERROR_OK;
1316 }
1317
1318 static int
1319 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1320 {
1321         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1322         struct cortex_m3_dwt_comparator *comparator;
1323         int dwt_num;
1324
1325         if (!watchpoint->set)
1326         {
1327                 LOG_WARNING("watchpoint (wpid: %d) not set",
1328                                 watchpoint->unique_id);
1329                 return ERROR_OK;
1330         }
1331
1332         dwt_num = watchpoint->set - 1;
1333
1334         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1335                         watchpoint->unique_id, dwt_num,
1336                         (unsigned) watchpoint->address);
1337
1338         if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1339         {
1340                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1341                 return ERROR_OK;
1342         }
1343
1344         comparator = cortex_m3->dwt_comparator_list + dwt_num;
1345         comparator->used = 0;
1346         comparator->function = 0;
1347         target_write_u32(target, comparator->dwt_comparator_address + 8,
1348                         comparator->function);
1349
1350         watchpoint->set = false;
1351
1352         return ERROR_OK;
1353 }
1354
1355 static int
1356 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1357 {
1358         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1359
1360         if (cortex_m3->dwt_comp_available < 1)
1361         {
1362                 LOG_DEBUG("no comparators?");
1363                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1364         }
1365
1366         /* hardware doesn't support data value masking */
1367         if (watchpoint->mask != ~(uint32_t)0) {
1368                 LOG_DEBUG("watchpoint value masks not supported");
1369                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1370         }
1371
1372         /* hardware allows address masks of up to 32K */
1373         unsigned mask;
1374
1375         for (mask = 0; mask < 16; mask++) {
1376                 if ((1u << mask) == watchpoint->length)
1377                         break;
1378         }
1379         if (mask == 16) {
1380                 LOG_DEBUG("unsupported watchpoint length");
1381                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1382         }
1383         if (watchpoint->address & ((1 << mask) - 1)) {
1384                 LOG_DEBUG("watchpoint address is unaligned");
1385                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1386         }
1387
1388         /* Caller doesn't seem to be able to describe watching for data
1389          * values of zero; that flags "no value".
1390          *
1391          * REVISIT This DWT may well be able to watch for specific data
1392          * values.  Requires comparator #1 to set DATAVMATCH and match
1393          * the data, and another comparator (DATAVADDR0) matching addr.
1394          */
1395         if (watchpoint->value) {
1396                 LOG_DEBUG("data value watchpoint not YET supported");
1397                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1398         }
1399
1400         cortex_m3->dwt_comp_available--;
1401         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1402
1403         return ERROR_OK;
1404 }
1405
1406 static int
1407 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1408 {
1409         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1410
1411         /* REVISIT why check? DWT can be updated with core running ... */
1412         if (target->state != TARGET_HALTED)
1413         {
1414                 LOG_WARNING("target not halted");
1415                 return ERROR_TARGET_NOT_HALTED;
1416         }
1417
1418         if (watchpoint->set)
1419         {
1420                 cortex_m3_unset_watchpoint(target, watchpoint);
1421         }
1422
1423         cortex_m3->dwt_comp_available++;
1424         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1425
1426         return ERROR_OK;
1427 }
1428
1429 static void cortex_m3_enable_watchpoints(struct target *target)
1430 {
1431         struct watchpoint *watchpoint = target->watchpoints;
1432
1433         /* set any pending watchpoints */
1434         while (watchpoint)
1435         {
1436                 if (!watchpoint->set)
1437                         cortex_m3_set_watchpoint(target, watchpoint);
1438                 watchpoint = watchpoint->next;
1439         }
1440 }
1441
1442 static int cortex_m3_load_core_reg_u32(struct target *target,
1443                 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1444 {
1445         int retval;
1446         struct armv7m_common *armv7m = target_to_armv7m(target);
1447         struct adiv5_dap *swjdp = &armv7m->dap;
1448
1449         /* NOTE:  we "know" here that the register identifiers used
1450          * in the v7m header match the Cortex-M3 Debug Core Register
1451          * Selector values for R0..R15, xPSR, MSP, and PSP.
1452          */
1453         switch (num) {
1454         case 0 ... 18:
1455                 /* read a normal core register */
1456                 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1457
1458                 if (retval != ERROR_OK)
1459                 {
1460                         LOG_ERROR("JTAG failure %i",retval);
1461                         return ERROR_JTAG_DEVICE_ERROR;
1462                 }
1463                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",(int)num,*value);
1464                 break;
1465
1466         case ARMV7M_PRIMASK:
1467         case ARMV7M_BASEPRI:
1468         case ARMV7M_FAULTMASK:
1469         case ARMV7M_CONTROL:
1470                 /* Cortex-M3 packages these four registers as bitfields
1471                  * in one Debug Core register.  So say r0 and r2 docs;
1472                  * it was removed from r1 docs, but still works.
1473                  */
1474                 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1475
1476                 switch (num)
1477                 {
1478                         case ARMV7M_PRIMASK:
1479                                 *value = buf_get_u32((uint8_t*)value, 0, 1);
1480                                 break;
1481
1482                         case ARMV7M_BASEPRI:
1483                                 *value = buf_get_u32((uint8_t*)value, 8, 8);
1484                                 break;
1485
1486                         case ARMV7M_FAULTMASK:
1487                                 *value = buf_get_u32((uint8_t*)value, 16, 1);
1488                                 break;
1489
1490                         case ARMV7M_CONTROL:
1491                                 *value = buf_get_u32((uint8_t*)value, 24, 2);
1492                                 break;
1493                 }
1494
1495                 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1496                 break;
1497
1498         default:
1499                 return ERROR_INVALID_ARGUMENTS;
1500         }
1501
1502         return ERROR_OK;
1503 }
1504
1505 static int cortex_m3_store_core_reg_u32(struct target *target,
1506                 enum armv7m_regtype type, uint32_t num, uint32_t value)
1507 {
1508         int retval;
1509         uint32_t reg;
1510         struct armv7m_common *armv7m = target_to_armv7m(target);
1511         struct adiv5_dap *swjdp = &armv7m->dap;
1512
1513 #ifdef ARMV7_GDB_HACKS
1514         /* If the LR register is being modified, make sure it will put us
1515          * in "thumb" mode, or an INVSTATE exception will occur. This is a
1516          * hack to deal with the fact that gdb will sometimes "forge"
1517          * return addresses, and doesn't set the LSB correctly (i.e., when
1518          * printing expressions containing function calls, it sets LR = 0.)
1519          * Valid exception return codes have bit 0 set too.
1520          */
1521         if (num == ARMV7M_R14)
1522                 value |= 0x01;
1523 #endif
1524
1525         /* NOTE:  we "know" here that the register identifiers used
1526          * in the v7m header match the Cortex-M3 Debug Core Register
1527          * Selector values for R0..R15, xPSR, MSP, and PSP.
1528          */
1529         switch (num) {
1530         case 0 ... 18:
1531                 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1532                 if (retval != ERROR_OK)
1533                 {
1534                         struct reg *r;
1535
1536                         LOG_ERROR("JTAG failure %i", retval);
1537                         r = armv7m->core_cache->reg_list + num;
1538                         r->dirty = r->valid;
1539                         return ERROR_JTAG_DEVICE_ERROR;
1540                 }
1541                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1542                 break;
1543
1544         case ARMV7M_PRIMASK:
1545         case ARMV7M_BASEPRI:
1546         case ARMV7M_FAULTMASK:
1547         case ARMV7M_CONTROL:
1548                 /* Cortex-M3 packages these four registers as bitfields
1549                  * in one Debug Core register.  So say r0 and r2 docs;
1550                  * it was removed from r1 docs, but still works.
1551                  */
1552                 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1553
1554                 switch (num)
1555                 {
1556                         case ARMV7M_PRIMASK:
1557                                 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1558                                 break;
1559
1560                         case ARMV7M_BASEPRI:
1561                                 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1562                                 break;
1563
1564                         case ARMV7M_FAULTMASK:
1565                                 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1566                                 break;
1567
1568                         case ARMV7M_CONTROL:
1569                                 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1570                                 break;
1571                 }
1572
1573                 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1574
1575                 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1576                 break;
1577
1578         default:
1579                 return ERROR_INVALID_ARGUMENTS;
1580         }
1581
1582         return ERROR_OK;
1583 }
1584
1585 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1586                 uint32_t size, uint32_t count, uint8_t *buffer)
1587 {
1588         struct armv7m_common *armv7m = target_to_armv7m(target);
1589         struct adiv5_dap *swjdp = &armv7m->dap;
1590         int retval = ERROR_INVALID_ARGUMENTS;
1591
1592         /* cortex_m3 handles unaligned memory access */
1593         if (count && buffer) {
1594                 switch (size) {
1595                 case 4:
1596                         retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1597                         break;
1598                 case 2:
1599                         retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1600                         break;
1601                 case 1:
1602                         retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1603                         break;
1604                 }
1605         }
1606
1607         return retval;
1608 }
1609
1610 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1611                 uint32_t size, uint32_t count, uint8_t *buffer)
1612 {
1613         struct armv7m_common *armv7m = target_to_armv7m(target);
1614         struct adiv5_dap *swjdp = &armv7m->dap;
1615         int retval = ERROR_INVALID_ARGUMENTS;
1616
1617         if (count && buffer) {
1618                 switch (size) {
1619                 case 4:
1620                         retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1621                         break;
1622                 case 2:
1623                         retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1624                         break;
1625                 case 1:
1626                         retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1627                         break;
1628                 }
1629         }
1630
1631         return retval;
1632 }
1633
1634 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1635                 uint32_t count, uint8_t *buffer)
1636 {
1637         return cortex_m3_write_memory(target, address, 4, count, buffer);
1638 }
1639
1640 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1641                 struct target *target)
1642 {
1643         armv7m_build_reg_cache(target);
1644         return ERROR_OK;
1645 }
1646
1647 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1648  * on r/w if the core is not running, and clear on resume or reset ... or
1649  * at least, in a post_restore_context() method.
1650  */
1651
1652 struct dwt_reg_state {
1653         struct target   *target;
1654         uint32_t        addr;
1655         uint32_t        value;  /* scratch/cache */
1656 };
1657
1658 static int cortex_m3_dwt_get_reg(struct reg *reg)
1659 {
1660         struct dwt_reg_state *state = reg->arch_info;
1661
1662         return target_read_u32(state->target, state->addr, &state->value);
1663 }
1664
1665 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1666 {
1667         struct dwt_reg_state *state = reg->arch_info;
1668
1669         return target_write_u32(state->target, state->addr,
1670                         buf_get_u32(buf, 0, reg->size));
1671 }
1672
1673 struct dwt_reg {
1674         uint32_t        addr;
1675         char            *name;
1676         unsigned        size;
1677 };
1678
1679 static struct dwt_reg dwt_base_regs[] = {
1680         { DWT_CTRL, "dwt_ctrl", 32, },
1681         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1682          * increments while the core is asleep.
1683          */
1684         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1685         /* plus some 8 bit counters, useful for profiling with TPIU */
1686 };
1687
1688 static struct dwt_reg dwt_comp[] = {
1689 #define DWT_COMPARATOR(i) \
1690                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1691                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1692                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1693         DWT_COMPARATOR(0),
1694         DWT_COMPARATOR(1),
1695         DWT_COMPARATOR(2),
1696         DWT_COMPARATOR(3),
1697 #undef DWT_COMPARATOR
1698 };
1699
1700 static const struct reg_arch_type dwt_reg_type = {
1701         .get = cortex_m3_dwt_get_reg,
1702         .set = cortex_m3_dwt_set_reg,
1703 };
1704
1705 static void
1706 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1707 {
1708         struct dwt_reg_state *state;
1709
1710         state = calloc(1, sizeof *state);
1711         if (!state)
1712                 return;
1713         state->addr = d->addr;
1714         state->target = t;
1715
1716         r->name = d->name;
1717         r->size = d->size;
1718         r->value = &state->value;
1719         r->arch_info = state;
1720         r->type = &dwt_reg_type;
1721 }
1722
1723 static void
1724 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1725 {
1726         uint32_t dwtcr;
1727         struct reg_cache *cache;
1728         struct cortex_m3_dwt_comparator *comparator;
1729         int reg, i;
1730
1731         target_read_u32(target, DWT_CTRL, &dwtcr);
1732         if (!dwtcr) {
1733                 LOG_DEBUG("no DWT");
1734                 return;
1735         }
1736
1737         cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1738         cm3->dwt_comp_available = cm3->dwt_num_comp;
1739         cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1740                         sizeof(struct cortex_m3_dwt_comparator));
1741         if (!cm3->dwt_comparator_list) {
1742 fail0:
1743                 cm3->dwt_num_comp = 0;
1744                 LOG_ERROR("out of mem");
1745                 return;
1746         }
1747
1748         cache = calloc(1, sizeof *cache);
1749         if (!cache) {
1750 fail1:
1751                 free(cm3->dwt_comparator_list);
1752                 goto fail0;
1753         }
1754         cache->name = "cortex-m3 dwt registers";
1755         cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1756         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1757         if (!cache->reg_list) {
1758                 free(cache);
1759                 goto fail1;
1760         }
1761
1762         for (reg = 0; reg < 2; reg++)
1763                 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1764                                 dwt_base_regs + reg);
1765
1766         comparator = cm3->dwt_comparator_list;
1767         for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1768                 int j;
1769
1770                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1771                 for (j = 0; j < 3; j++, reg++)
1772                         cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1773                                         dwt_comp + 3 * i + j);
1774         }
1775
1776         *register_get_last_cache_p(&target->reg_cache) = cache;
1777         cm3->dwt_cache = cache;
1778
1779         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1780                         dwtcr, cm3->dwt_num_comp,
1781                         (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1782
1783         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1784          * implement single-address data value watchpoints ... so we
1785          * won't need to check it later, when asked to set one up.
1786          */
1787 }
1788
1789 static int cortex_m3_examine(struct target *target)
1790 {
1791         int retval;
1792         uint32_t cpuid, fpcr;
1793         int i;
1794         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1795         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
1796
1797         if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1798                 return retval;
1799
1800         if (!target_was_examined(target))
1801         {
1802                 target_set_examined(target);
1803
1804                 /* Read from Device Identification Registers */
1805                 retval = target_read_u32(target, CPUID, &cpuid);
1806                 if (retval != ERROR_OK)
1807                         return retval;
1808
1809                 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1810                         LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
1811                                 (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1812                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1813
1814                 /* NOTE: FPB and DWT are both optional. */
1815
1816                 /* Setup FPB */
1817                 target_read_u32(target, FP_CTRL, &fpcr);
1818                 cortex_m3->auto_bp_type = 1;
1819                 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1820                 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1821                 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1822                 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1823                 cortex_m3->fpb_enabled = fpcr & 1;
1824                 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1825                 {
1826                         cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1827                         cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1828                 }
1829                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1830
1831                 /* Setup DWT */
1832                 cortex_m3_dwt_setup(cortex_m3, target);
1833
1834                 /* These hardware breakpoints only work for code in flash! */
1835                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1836                                 target_name(target),
1837                                 cortex_m3->fp_num_code,
1838                                 cortex_m3->dwt_num_comp);
1839         }
1840
1841         return ERROR_OK;
1842 }
1843
1844 static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
1845 {
1846         uint16_t dcrdr;
1847         int retval;
1848
1849         mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1850         *ctrl = (uint8_t)dcrdr;
1851         *value = (uint8_t)(dcrdr >> 8);
1852
1853         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1854
1855         /* write ack back to software dcc register
1856          * signify we have read data */
1857         if (dcrdr & (1 << 0))
1858         {
1859                 dcrdr = 0;
1860                 retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1861                 if (retval != ERROR_OK)
1862                         return retval;
1863         }
1864
1865         return ERROR_OK;
1866 }
1867
1868 static int cortex_m3_target_request_data(struct target *target,
1869                 uint32_t size, uint8_t *buffer)
1870 {
1871         struct armv7m_common *armv7m = target_to_armv7m(target);
1872         struct adiv5_dap *swjdp = &armv7m->dap;
1873         uint8_t data;
1874         uint8_t ctrl;
1875         uint32_t i;
1876
1877         for (i = 0; i < (size * 4); i++)
1878         {
1879                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1880                 buffer[i] = data;
1881         }
1882
1883         return ERROR_OK;
1884 }
1885
1886 static int cortex_m3_handle_target_request(void *priv)
1887 {
1888         struct target *target = priv;
1889         if (!target_was_examined(target))
1890                 return ERROR_OK;
1891         struct armv7m_common *armv7m = target_to_armv7m(target);
1892         struct adiv5_dap *swjdp = &armv7m->dap;
1893
1894         if (!target->dbg_msg_enabled)
1895                 return ERROR_OK;
1896
1897         if (target->state == TARGET_RUNNING)
1898         {
1899                 uint8_t data;
1900                 uint8_t ctrl;
1901
1902                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1903
1904                 /* check if we have data */
1905                 if (ctrl & (1 << 0))
1906                 {
1907                         uint32_t request;
1908
1909                         /* we assume target is quick enough */
1910                         request = data;
1911                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1912                         request |= (data << 8);
1913                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1914                         request |= (data << 16);
1915                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1916                         request |= (data << 24);
1917                         target_request(target, request);
1918                 }
1919         }
1920
1921         return ERROR_OK;
1922 }
1923
1924 static int cortex_m3_init_arch_info(struct target *target,
1925                 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1926 {
1927         int retval;
1928         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1929
1930         armv7m_init_arch_info(target, armv7m);
1931
1932         /* prepare JTAG information for the new target */
1933         cortex_m3->jtag_info.tap = tap;
1934         cortex_m3->jtag_info.scann_size = 4;
1935
1936         /* default reset mode is to use srst if fitted
1937          * if not it will use CORTEX_M3_RESET_VECTRESET */
1938         cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
1939
1940         armv7m->arm.dap = &armv7m->dap;
1941
1942         /* Leave (only) generic DAP stuff for debugport_init(); */
1943         armv7m->dap.jtag_info = &cortex_m3->jtag_info;
1944         armv7m->dap.memaccess_tck = 8;
1945         /* Cortex-M3 has 4096 bytes autoincrement range */
1946         armv7m->dap.tar_autoincr_block = (1 << 12);
1947
1948         /* register arch-specific functions */
1949         armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1950
1951         armv7m->post_debug_entry = NULL;
1952
1953         armv7m->pre_restore_context = NULL;
1954
1955         armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1956         armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1957
1958         target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1959
1960         if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1961         {
1962                 return retval;
1963         }
1964
1965         return ERROR_OK;
1966 }
1967
1968 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1969 {
1970         struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1971
1972         cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1973         cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1974
1975         return ERROR_OK;
1976 }
1977
1978 /*--------------------------------------------------------------------------*/
1979
1980 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1981                 struct cortex_m3_common *cm3)
1982 {
1983         if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1984                 command_print(cmd_ctx, "target is not a Cortex-M3");
1985                 return ERROR_TARGET_INVALID;
1986         }
1987         return ERROR_OK;
1988 }
1989
1990 /*
1991  * Only stuff below this line should need to verify that its target
1992  * is a Cortex-M3.  Everything else should have indirected through the
1993  * cortexm3_target structure, which is only used with CM3 targets.
1994  */
1995
1996 static const struct {
1997         char name[10];
1998         unsigned mask;
1999 } vec_ids[] = {
2000         { "hard_err",   VC_HARDERR, },
2001         { "int_err",    VC_INTERR, },
2002         { "bus_err",    VC_BUSERR, },
2003         { "state_err",  VC_STATERR, },
2004         { "chk_err",    VC_CHKERR, },
2005         { "nocp_err",   VC_NOCPERR, },
2006         { "mm_err",     VC_MMERR, },
2007         { "reset",      VC_CORERESET, },
2008 };
2009
2010 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
2011 {
2012         struct target *target = get_current_target(CMD_CTX);
2013         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2014         struct armv7m_common *armv7m = &cortex_m3->armv7m;
2015         struct adiv5_dap *swjdp = &armv7m->dap;
2016         uint32_t demcr = 0;
2017         int retval;
2018
2019         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2020         if (retval != ERROR_OK)
2021                 return retval;
2022
2023         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2024         if (retval != ERROR_OK)
2025                 return retval;
2026
2027         if (CMD_ARGC > 0) {
2028                 unsigned catch = 0;
2029
2030                 if (CMD_ARGC == 1) {
2031                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2032                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2033                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2034                                         | VC_MMERR | VC_CORERESET;
2035                                 goto write;
2036                         } else if (strcmp(CMD_ARGV[0], "none") == 0) {
2037                                 goto write;
2038                         }
2039                 }
2040                 while (CMD_ARGC-- > 0) {
2041                         unsigned i;
2042                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2043                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2044                                         continue;
2045                                 catch |= vec_ids[i].mask;
2046                                 break;
2047                         }
2048                         if (i == ARRAY_SIZE(vec_ids)) {
2049                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2050                                 return ERROR_INVALID_ARGUMENTS;
2051                         }
2052                 }
2053 write:
2054                 /* For now, armv7m->demcr only stores vector catch flags. */
2055                 armv7m->demcr = catch;
2056
2057                 demcr &= ~0xffff;
2058                 demcr |= catch;
2059
2060                 /* write, but don't assume it stuck (why not??) */
2061                 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2062                 if (retval != ERROR_OK)
2063                         return retval;
2064                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2065                 if (retval != ERROR_OK)
2066                         return retval;
2067
2068                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2069                  * Otherwise the vector catch hardware could fire when there's
2070                  * no debugger hooked up, causing much confusion...
2071                  */
2072         }
2073
2074         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
2075         {
2076                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2077                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2078         }
2079
2080         return ERROR_OK;
2081 }
2082
2083 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
2084 {
2085         struct target *target = get_current_target(CMD_CTX);
2086         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2087         int retval;
2088
2089         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2090         if (retval != ERROR_OK)
2091                 return retval;
2092
2093         if (target->state != TARGET_HALTED)
2094         {
2095                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2096                 return ERROR_OK;
2097         }
2098
2099         if (CMD_ARGC > 0)
2100         {
2101                 bool enable;
2102                 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
2103                 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
2104                 uint32_t mask_off = enable ? 0 : C_MASKINTS;
2105                 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
2106         }
2107
2108         command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
2109                         (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
2110
2111         return ERROR_OK;
2112 }
2113
2114 COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
2115 {
2116         struct target *target = get_current_target(CMD_CTX);
2117         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2118         int retval;
2119         char *reset_config;
2120
2121         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2122         if (retval != ERROR_OK)
2123                 return retval;
2124
2125         if (CMD_ARGC > 0)
2126         {
2127                 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2128                         cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
2129                 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2130                         cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
2131         }
2132
2133         switch (cortex_m3->soft_reset_config)
2134         {
2135                 case CORTEX_M3_RESET_SYSRESETREQ:
2136                         reset_config = "sysresetreq";
2137                         break;
2138
2139                 case CORTEX_M3_RESET_VECTRESET:
2140                         reset_config = "vectreset";
2141                         break;
2142
2143                 default:
2144                         reset_config = "unknown";
2145                         break;
2146         }
2147
2148         command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
2149
2150         return ERROR_OK;
2151 }
2152
2153 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2154         {
2155                 .name = "maskisr",
2156                 .handler = handle_cortex_m3_mask_interrupts_command,
2157                 .mode = COMMAND_EXEC,
2158                 .help = "mask cortex_m3 interrupts",
2159                 .usage = "['on'|'off']",
2160         },
2161         {
2162                 .name = "vector_catch",
2163                 .handler = handle_cortex_m3_vector_catch_command,
2164                 .mode = COMMAND_EXEC,
2165                 .help = "configure hardware vectors to trigger debug entry",
2166                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2167         },
2168         {
2169                 .name = "reset_config",
2170                 .handler = handle_cortex_m3_reset_config_command,
2171                 .mode = COMMAND_ANY,
2172                 .help = "configure software reset handling",
2173                 .usage = "['srst'|'sysresetreq'|'vectreset']",
2174         },
2175         COMMAND_REGISTRATION_DONE
2176 };
2177 static const struct command_registration cortex_m3_command_handlers[] = {
2178         {
2179                 .chain = armv7m_command_handlers,
2180         },
2181         {
2182                 .name = "cortex_m3",
2183                 .mode = COMMAND_EXEC,
2184                 .help = "Cortex-M3 command group",
2185                 .chain = cortex_m3_exec_command_handlers,
2186         },
2187         COMMAND_REGISTRATION_DONE
2188 };
2189
2190 struct target_type cortexm3_target =
2191 {
2192         .name = "cortex_m3",
2193
2194         .poll = cortex_m3_poll,
2195         .arch_state = armv7m_arch_state,
2196
2197         .target_request_data = cortex_m3_target_request_data,
2198
2199         .halt = cortex_m3_halt,
2200         .resume = cortex_m3_resume,
2201         .step = cortex_m3_step,
2202
2203         .assert_reset = cortex_m3_assert_reset,
2204         .deassert_reset = cortex_m3_deassert_reset,
2205         .soft_reset_halt = cortex_m3_soft_reset_halt,
2206
2207         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2208
2209         .read_memory = cortex_m3_read_memory,
2210         .write_memory = cortex_m3_write_memory,
2211         .bulk_write_memory = cortex_m3_bulk_write_memory,
2212         .checksum_memory = armv7m_checksum_memory,
2213         .blank_check_memory = armv7m_blank_check_memory,
2214
2215         .run_algorithm = armv7m_run_algorithm,
2216
2217         .add_breakpoint = cortex_m3_add_breakpoint,
2218         .remove_breakpoint = cortex_m3_remove_breakpoint,
2219         .add_watchpoint = cortex_m3_add_watchpoint,
2220         .remove_watchpoint = cortex_m3_remove_watchpoint,
2221
2222         .commands = cortex_m3_command_handlers,
2223         .target_create = cortex_m3_target_create,
2224         .init_target = cortex_m3_init_target,
2225         .examine = cortex_m3_examine,
2226 };