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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "breakpoints.h"
  35 #include "cortex_m3.h"
  36 #include "target_request.h"
  37 #include "target_type.h"
  38 #include "arm_disassembler.h"
  39 #include "register.h"
  40
  41
  42 /* NOTE:  most of this should work fine for the Cortex-M1 and
  43  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  44  */
  45
  46
  47 /* forward declarations */
  48 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
  49 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
  50 static void cortex_m3_enable_watchpoints(struct target *target);
  51 static int cortex_m3_store_core_reg_u32(struct target *target,
  52                 enum armv7m_regtype type, uint32_t num, uint32_t value);
  53
  54 #ifdef ARMV7_GDB_HACKS
  55 extern uint8_t armv7m_gdb_dummy_cpsr_value[];
  56 extern struct reg armv7m_gdb_dummy_cpsr_reg;
  57 #endif
  58
  59 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
  60                 uint32_t *value, int regnum)
  61 {
  62         int retval;
  63         uint32_t dcrdr;
  64
  65         /* because the DCB_DCRDR is used for the emulated dcc channel
  66          * we have to save/restore the DCB_DCRDR when used */
  67
  68         mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  69
  70         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  71
  72         /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  73         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  74         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  75
  76         /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  77         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  78         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  79
  80         retval = swjdp_transaction_endcheck(swjdp);
  81
  82         /* restore DCB_DCRDR - this needs to be in a seperate
  83          * transaction otherwise the emulated DCC channel breaks */
  84         if (retval == ERROR_OK)
  85                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  86
  87         return retval;
  88 }
  89
  90 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
  91                 uint32_t value, int regnum)
  92 {
  93         int retval;
  94         uint32_t dcrdr;
  95
  96         /* because the DCB_DCRDR is used for the emulated dcc channel
  97          * we have to save/restore the DCB_DCRDR when used */
  98
  99         mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 100
 101         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 102
 103         /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
 104         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 105         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 106
 107         /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
 108         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 109         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 110
 111         retval = swjdp_transaction_endcheck(swjdp);
 112
 113         /* restore DCB_DCRDR - this needs to be in a seperate
 114          * transaction otherwise the emulated DCC channel breaks */
 115         if (retval == ERROR_OK)
 116                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 117
 118         return retval;
 119 }
 120
 121 static int cortex_m3_write_debug_halt_mask(struct target *target,
 122                 uint32_t mask_on, uint32_t mask_off)
 123 {
 124         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 125         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 126
 127         /* mask off status bits */
 128         cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 129         /* create new register mask */
 130         cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 131
 132         return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
 133 }
 134
 135 static int cortex_m3_clear_halt(struct target *target)
 136 {
 137         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 138         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 139
 140         /* clear step if any */
 141         cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 142
 143         /* Read Debug Fault Status Register */
 144         mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 145         /* Clear Debug Fault Status */
 146         mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
 147         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 148
 149         return ERROR_OK;
 150 }
 151
 152 static int cortex_m3_single_step_core(struct target *target)
 153 {
 154         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 155         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 156         uint32_t dhcsr_save;
 157
 158         /* backup dhcsr reg */
 159         dhcsr_save = cortex_m3->dcb_dhcsr;
 160
 161         /* mask interrupts if not done already */
 162         if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
 163                 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 164         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 165         LOG_DEBUG(" ");
 166
 167         /* restore dhcsr reg */
 168         cortex_m3->dcb_dhcsr = dhcsr_save;
 169         cortex_m3_clear_halt(target);
 170
 171         return ERROR_OK;
 172 }
 173
 174 static int cortex_m3_endreset_event(struct target *target)
 175 {
 176         int i;
 177         uint32_t dcb_demcr;
 178         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 179         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 180         struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 181         struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 182
 183         mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 184         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 185
 186         /* this regsiter is used for emulated dcc channel */
 187         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 188
 189         /* Enable debug requests */
 190         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 191         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 192                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 193
 194         /* clear any interrupt masking */
 195         cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
 196
 197         /* Enable trace and dwt */
 198         mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
 199         /* Monitor bus faults */
 200         mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
 201
 202         /* Enable FPB */
 203         target_write_u32(target, FP_CTRL, 3);
 204         cortex_m3->fpb_enabled = 1;
 205
 206         /* Restore FPB registers */
 207         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
 208         {
 209                 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 210         }
 211
 212         /* Restore DWT registers */
 213         for (i = 0; i < cortex_m3->dwt_num_comp; i++)
 214         {
 215                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 216                                 dwt_list[i].comp);
 217                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 218                                 dwt_list[i].mask);
 219                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 220                                 dwt_list[i].function);
 221         }
 222         swjdp_transaction_endcheck(swjdp);
 223
 224         armv7m_invalidate_core_regs(target);
 225
 226         /* make sure we have latest dhcsr flags */
 227         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 228
 229         return ERROR_OK;
 230 }
 231
 232 static int cortex_m3_examine_debug_reason(struct target *target)
 233 {
 234         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 235
 236         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
 237         /* only check the debug reason if we don't know it already */
 238
 239         if ((target->debug_reason != DBG_REASON_DBGRQ)
 240                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 241         {
 242                 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 243                 {
 244                         target->debug_reason = DBG_REASON_BREAKPOINT;
 245                         if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 246                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 247                 }
 248                 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 249                         target->debug_reason = DBG_REASON_WATCHPOINT;
 250                 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
 251                         target->debug_reason = DBG_REASON_BREAKPOINT;
 252                 else /* EXTERNAL, HALTED */
 253                         target->debug_reason = DBG_REASON_UNDEFINED;
 254         }
 255
 256         return ERROR_OK;
 257 }
 258
 259 static int cortex_m3_examine_exception_reason(struct target *target)
 260 {
 261         uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
 262         struct armv7m_common *armv7m = target_to_armv7m(target);
 263         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 264
 265         mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 266         switch (armv7m->exception_number)
 267         {
 268                 case 2: /* NMI */
 269                         break;
 270                 case 3: /* Hard Fault */
 271                         mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 272                         if (except_sr & 0x40000000)
 273                         {
 274                                 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
 275                         }
 276                         break;
 277                 case 4: /* Memory Management */
 278                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 279                         mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
 280                         break;
 281                 case 5: /* Bus Fault */
 282                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 283                         mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
 284                         break;
 285                 case 6: /* Usage Fault */
 286                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 287                         break;
 288                 case 11:        /* SVCall */
 289                         break;
 290                 case 12:        /* Debug Monitor */
 291                         mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
 292                         break;
 293                 case 14:        /* PendSV */
 294                         break;
 295                 case 15:        /* SysTick */
 296                         break;
 297                 default:
 298                         except_sr = 0;
 299                         break;
 300         }
 301         swjdp_transaction_endcheck(swjdp);
 302         LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
 303                 shcsr, except_sr, cfsr, except_ar);
 304         return ERROR_OK;
 305 }
 306
 307 static int cortex_m3_debug_entry(struct target *target)
 308 {
 309         int i;
 310         uint32_t xPSR;
 311         int retval;
 312         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 313         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 314         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 315
 316         LOG_DEBUG(" ");
 317
 318         cortex_m3_clear_halt(target);
 319         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 320
 321         if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
 322                 return retval;
 323
 324         /* Examine target state and mode */
 325         /* First load register acessible through core debug port*/
 326         int num_regs = armv7m->core_cache->num_regs;
 327
 328         for (i = 0; i < num_regs; i++)
 329         {
 330                 if (!armv7m->core_cache->reg_list[i].valid)
 331                         armv7m->read_core_reg(target, i);
 332         }
 333
 334         xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
 335
 336 #ifdef ARMV7_GDB_HACKS
 337         /* FIXME this breaks on scan chains with more than one Cortex-M3.
 338          * Instead, each CM3 should have its own dummy value...
 339          */
 340         /* copy real xpsr reg for gdb, setting thumb bit */
 341         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
 342         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
 343         armv7m_gdb_dummy_cpsr_reg.valid = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
 344         armv7m_gdb_dummy_cpsr_reg.dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty;
 345 #endif
 346
 347         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 348         if (xPSR & 0xf00)
 349         {
 350                 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
 351                 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 352         }
 353
 354         /* Are we in an exception handler */
 355         if (xPSR & 0x1FF)
 356         {
 357                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 358                 armv7m->exception_number = (xPSR & 0x1FF);
 359         }
 360         else
 361         {
 362                 armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
 363                 armv7m->exception_number = 0;
 364         }
 365
 366         if (armv7m->exception_number)
 367         {
 368                 cortex_m3_examine_exception_reason(target);
 369         }
 370
 371         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 372                 armv7m_mode_strings[armv7m->core_mode],
 373                 *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
 374                 target_state_name(target));
 375
 376         if (armv7m->post_debug_entry)
 377                 armv7m->post_debug_entry(target);
 378
 379         return ERROR_OK;
 380 }
 381
 382 static int cortex_m3_poll(struct target *target)
 383 {
 384         int retval;
 385         enum target_state prev_target_state = target->state;
 386         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 387         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 388
 389         /* Read from Debug Halting Control and Status Register */
 390         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 391         if (retval != ERROR_OK)
 392         {
 393                 target->state = TARGET_UNKNOWN;
 394                 return retval;
 395         }
 396
 397         if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 398         {
 399                 /* check if still in reset */
 400                 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 401
 402                 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 403                 {
 404                         target->state = TARGET_RESET;
 405                         return ERROR_OK;
 406                 }
 407         }
 408
 409         if (target->state == TARGET_RESET)
 410         {
 411                 /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
 412                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32 "", cortex_m3->dcb_dhcsr);
 413                 cortex_m3_endreset_event(target);
 414                 target->state = TARGET_RUNNING;
 415                 prev_target_state = TARGET_RUNNING;
 416         }
 417
 418         if (cortex_m3->dcb_dhcsr & S_HALT)
 419         {
 420                 target->state = TARGET_HALTED;
 421
 422                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 423                 {
 424                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 425                                 return retval;
 426
 427                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 428                 }
 429                 if (prev_target_state == TARGET_DEBUG_RUNNING)
 430                 {
 431                         LOG_DEBUG(" ");
 432                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 433                                 return retval;
 434
 435                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 436                 }
 437         }
 438
 439         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 440          * How best to model low power modes?
 441          */
 442
 443         if (target->state == TARGET_UNKNOWN)
 444         {
 445                 /* check if processor is retiring instructions */
 446                 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
 447                 {
 448                         target->state = TARGET_RUNNING;
 449                         return ERROR_OK;
 450                 }
 451         }
 452
 453         return ERROR_OK;
 454 }
 455
 456 static int cortex_m3_halt(struct target *target)
 457 {
 458         LOG_DEBUG("target->state: %s",
 459                 target_state_name(target));
 460
 461         if (target->state == TARGET_HALTED)
 462         {
 463                 LOG_DEBUG("target was already halted");
 464                 return ERROR_OK;
 465         }
 466
 467         if (target->state == TARGET_UNKNOWN)
 468         {
 469                 LOG_WARNING("target was in unknown state when halt was requested");
 470         }
 471
 472         if (target->state == TARGET_RESET)
 473         {
 474                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
 475                 {
 476                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 477                         return ERROR_TARGET_FAILURE;
 478                 }
 479                 else
 480                 {
 481                         /* we came here in a reset_halt or reset_init sequence
 482                          * debug entry was already prepared in cortex_m3_prepare_reset_halt()
 483                          */
 484                         target->debug_reason = DBG_REASON_DBGRQ;
 485
 486                         return ERROR_OK;
 487                 }
 488         }
 489
 490         /* Write to Debug Halting Control and Status Register */
 491         cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 492
 493         target->debug_reason = DBG_REASON_DBGRQ;
 494
 495         return ERROR_OK;
 496 }
 497
 498 static int cortex_m3_soft_reset_halt(struct target *target)
 499 {
 500         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 501         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 502         uint32_t dcb_dhcsr = 0;
 503         int retval, timeout = 0;
 504
 505         /* Enter debug state on reset, cf. end_reset_event() */
 506         mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 507
 508         /* Request a reset */
 509         mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
 510         target->state = TARGET_RESET;
 511
 512         /* registers are now invalid */
 513         armv7m_invalidate_core_regs(target);
 514
 515         while (timeout < 100)
 516         {
 517                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 518                 if (retval == ERROR_OK)
 519                 {
 520                         mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 521                         if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 522                         {
 523                                 LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32 ", nvic_dfsr 0x%" PRIx32 "", dcb_dhcsr, cortex_m3->nvic_dfsr);
 524                                 cortex_m3_poll(target);
 525                                 return ERROR_OK;
 526                         }
 527                         else
 528                                 LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32 ", %i ms", dcb_dhcsr, timeout);
 529                 }
 530                 timeout++;
 531                 alive_sleep(1);
 532         }
 533
 534         return ERROR_OK;
 535 }
 536
 537 static void cortex_m3_enable_breakpoints(struct target *target)
 538 {
 539         struct breakpoint *breakpoint = target->breakpoints;
 540
 541         /* set any pending breakpoints */
 542         while (breakpoint)
 543         {
 544                 if (breakpoint->set == 0)
 545                         cortex_m3_set_breakpoint(target, breakpoint);
 546                 breakpoint = breakpoint->next;
 547         }
 548 }
 549
 550 static int cortex_m3_resume(struct target *target, int current,
 551                 uint32_t address, int handle_breakpoints, int debug_execution)
 552 {
 553         struct armv7m_common *armv7m = target_to_armv7m(target);
 554         struct breakpoint *breakpoint = NULL;
 555         uint32_t resume_pc;
 556
 557         if (target->state != TARGET_HALTED)
 558         {
 559                 LOG_WARNING("target not halted");
 560                 return ERROR_TARGET_NOT_HALTED;
 561         }
 562
 563         if (!debug_execution)
 564         {
 565                 target_free_all_working_areas(target);
 566                 cortex_m3_enable_breakpoints(target);
 567                 cortex_m3_enable_watchpoints(target);
 568         }
 569
 570         if (debug_execution)
 571         {
 572                 /* Disable interrupts */
 573                 /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
 574                  * This is probably the same issue as Cortex-M3 Errata  377493:
 575                  * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
 576                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
 577                 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
 578                 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
 579
 580                 /* Make sure we are in Thumb mode */
 581                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
 582                         buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
 583                 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
 584                 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
 585         }
 586
 587         /* current = 1: continue on current pc, otherwise continue at <address> */
 588         if (!current)
 589         {
 590                 buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
 591                 armv7m->core_cache->reg_list[15].dirty = 1;
 592                 armv7m->core_cache->reg_list[15].valid = 1;
 593         }
 594
 595         resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32);
 596
 597         armv7m_restore_context(target);
 598
 599         /* the front-end may request us not to handle breakpoints */
 600         if (handle_breakpoints)
 601         {
 602                 /* Single step past breakpoint at current address */
 603                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 604                 {
 605                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 606                                           breakpoint->address,
 607                                           breakpoint->unique_id);
 608                         cortex_m3_unset_breakpoint(target, breakpoint);
 609                         cortex_m3_single_step_core(target);
 610                         cortex_m3_set_breakpoint(target, breakpoint);
 611                 }
 612         }
 613
 614         /* Restart core */
 615         cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 616
 617         target->debug_reason = DBG_REASON_NOTHALTED;
 618
 619         /* registers are now invalid */
 620         armv7m_invalidate_core_regs(target);
 621         if (!debug_execution)
 622         {
 623                 target->state = TARGET_RUNNING;
 624                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 625                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 626         }
 627         else
 628         {
 629                 target->state = TARGET_DEBUG_RUNNING;
 630                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 631                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 632         }
 633
 634         return ERROR_OK;
 635 }
 636
 637 /* int irqstepcount = 0; */
 638 static int cortex_m3_step(struct target *target, int current,
 639                 uint32_t address, int handle_breakpoints)
 640 {
 641         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 642         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 643         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 644         struct breakpoint *breakpoint = NULL;
 645
 646         if (target->state != TARGET_HALTED)
 647         {
 648                 LOG_WARNING("target not halted");
 649                 return ERROR_TARGET_NOT_HALTED;
 650         }
 651
 652         /* current = 1: continue on current pc, otherwise continue at <address> */
 653         if (!current)
 654                 buf_set_u32(cortex_m3->armv7m.core_cache->reg_list[15].value,
 655                                 0, 32, address);
 656
 657         /* the front-end may request us not to handle breakpoints */
 658         if (handle_breakpoints) {
 659                 breakpoint = breakpoint_find(target, buf_get_u32(armv7m
 660                                 ->core_cache->reg_list[15].value, 0, 32));
 661                 if (breakpoint)
 662                         cortex_m3_unset_breakpoint(target, breakpoint);
 663         }
 664
 665         target->debug_reason = DBG_REASON_SINGLESTEP;
 666
 667         armv7m_restore_context(target);
 668
 669         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 670
 671         /* set step and clear halt */
 672         cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 673         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 674
 675         /* registers are now invalid */
 676         armv7m_invalidate_core_regs(target);
 677
 678         if (breakpoint)
 679                 cortex_m3_set_breakpoint(target, breakpoint);
 680
 681         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 682
 683         cortex_m3_debug_entry(target);
 684         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 685
 686         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 687         return ERROR_OK;
 688 }
 689
 690 static int cortex_m3_assert_reset(struct target *target)
 691 {
 692         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 693         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 694         int assert_srst = 1;
 695
 696         LOG_DEBUG("target->state: %s",
 697                 target_state_name(target));
 698
 699         enum reset_types jtag_reset_config = jtag_get_reset_config();
 700
 701         /*
 702          * We can reset Cortex-M3 targets using just the NVIC without
 703          * requiring SRST, getting a SoC reset (or a core-only reset)
 704          * instead of a system reset.
 705          */
 706         if (!(jtag_reset_config & RESET_HAS_SRST))
 707                 assert_srst = 0;
 708
 709         /* Enable debug requests */
 710         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 711         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 712                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 713
 714         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 715
 716         if (!target->reset_halt)
 717         {
 718                 /* Set/Clear C_MASKINTS in a separate operation */
 719                 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
 720                         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
 721
 722                 /* clear any debug flags before resuming */
 723                 cortex_m3_clear_halt(target);
 724
 725                 /* clear C_HALT in dhcsr reg */
 726                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 727
 728                 /* Enter debug state on reset, cf. end_reset_event() */
 729                 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
 730         }
 731         else
 732         {
 733                 /* Enter debug state on reset, cf. end_reset_event() */
 734                 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 735         }
 736
 737         /*
 738          * When nRST is asserted on most Stellaris devices, it clears some of
 739          * the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
 740          * and OpenOCD depends on those TRMs.  So we won't use SRST on those
 741          * chips.  (Only power-on reset should affect debug state, beyond a
 742          * few specified bits; not the chip's nRST input, wired to SRST.)
 743          *
 744          * REVISIT current errata specs don't seem to cover this issue.
 745          * Do we have more details than this email?
 746          *   https://lists.berlios.de/pipermail
 747          *      /openocd-development/2008-August/003065.html
 748          */
 749         if (strcmp(target->variant, "lm3s") == 0)
 750         {
 751                 /* Check for silicon revisions with the issue. */
 752                 uint32_t did0;
 753
 754                 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
 755                 {
 756                         switch ((did0 >> 16) & 0xff)
 757                         {
 758                                 case 0:
 759                                         /* all Sandstorm suffer issue */
 760                                         assert_srst = 0;
 761                                         break;
 762
 763                                 case 1:
 764                                 case 3:
 765                                         /* Fury and DustDevil rev A have
 766                                          * this nRST problem.  It should
 767                                          * be fixed in rev B silicon.
 768                                          */
 769                                         if (((did0 >> 8) & 0xff) == 0)
 770                                                 assert_srst = 0;
 771                                         break;
 772                                 case 4:
 773                                         /* Tempest should be fine. */
 774                                         break;
 775                         }
 776                 }
 777         }
 778
 779         if (assert_srst)
 780         {
 781                 /* default to asserting srst */
 782                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 783                 {
 784                         jtag_add_reset(1, 1);
 785                 }
 786                 else
 787                 {
 788                         jtag_add_reset(0, 1);
 789                 }
 790         }
 791         else
 792         {
 793                 /* Use a standard Cortex-M3 software reset mechanism.
 794                  * SYSRESETREQ will reset SoC peripherals outside the
 795                  * core, like watchdog timers, if the SoC wires it up
 796                  * correctly.  Else VECRESET can reset just the core.
 797                  */
 798                 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 799                                 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
 800                 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
 801
 802                 {
 803                         /* I do not know why this is necessary, but it
 804                          * fixes strange effects (step/resume cause NMI
 805                          * after reset) on LM3S6918 -- Michael Schwingen
 806                          */
 807                         uint32_t tmp;
 808                         mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
 809                 }
 810         }
 811
 812         target->state = TARGET_RESET;
 813         jtag_add_sleep(50000);
 814
 815         armv7m_invalidate_core_regs(target);
 816
 817         if (target->reset_halt)
 818         {
 819                 int retval;
 820                 if ((retval = target_halt(target)) != ERROR_OK)
 821                         return retval;
 822         }
 823
 824         return ERROR_OK;
 825 }
 826
 827 static int cortex_m3_deassert_reset(struct target *target)
 828 {
 829         LOG_DEBUG("target->state: %s",
 830                 target_state_name(target));
 831
 832         /* deassert reset lines */
 833         jtag_add_reset(0, 0);
 834
 835         return ERROR_OK;
 836 }
 837
 838 static int
 839 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
 840 {
 841         int retval;
 842         int fp_num = 0;
 843         uint32_t hilo;
 844         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 845         struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
 846
 847         if (breakpoint->set)
 848         {
 849                 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
 850                 return ERROR_OK;
 851         }
 852
 853         if (cortex_m3->auto_bp_type)
 854         {
 855                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
 856         }
 857
 858         if (breakpoint->type == BKPT_HARD)
 859         {
 860                 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
 861                         fp_num++;
 862                 if (fp_num >= cortex_m3->fp_num_code)
 863                 {
 864                         LOG_ERROR("Can not find free FPB Comparator!");
 865                         return ERROR_FAIL;
 866                 }
 867                 breakpoint->set = fp_num + 1;
 868                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
 869                 comparator_list[fp_num].used = 1;
 870                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
 871                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
 872                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
 873                 if (!cortex_m3->fpb_enabled)
 874                 {
 875                         LOG_DEBUG("FPB wasn't enabled, do it now");
 876                         target_write_u32(target, FP_CTRL, 3);
 877                 }
 878         }
 879         else if (breakpoint->type == BKPT_SOFT)
 880         {
 881                 uint8_t code[4];
 882                 buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
 883                 if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
 884                 {
 885                         return retval;
 886                 }
 887                 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
 888                 {
 889                         return retval;
 890                 }
 891                 breakpoint->set = 0x11; /* Any nice value but 0 */
 892         }
 893
 894         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
 895                           breakpoint->unique_id,
 896                           (int)(breakpoint->type),
 897                           breakpoint->address,
 898                           breakpoint->length,
 899                           breakpoint->set);
 900
 901         return ERROR_OK;
 902 }
 903
 904 static int
 905 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
 906 {
 907         int retval;
 908         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 909         struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
 910
 911         if (!breakpoint->set)
 912         {
 913                 LOG_WARNING("breakpoint not set");
 914                 return ERROR_OK;
 915         }
 916
 917         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
 918                           breakpoint->unique_id,
 919                           (int)(breakpoint->type),
 920                           breakpoint->address,
 921                           breakpoint->length,
 922                           breakpoint->set);
 923
 924         if (breakpoint->type == BKPT_HARD)
 925         {
 926                 int fp_num = breakpoint->set - 1;
 927                 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
 928                 {
 929                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
 930                         return ERROR_OK;
 931                 }
 932                 comparator_list[fp_num].used = 0;
 933                 comparator_list[fp_num].fpcr_value = 0;
 934                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
 935         }
 936         else
 937         {
 938                 /* restore original instruction (kept in target endianness) */
 939                 if (breakpoint->length == 4)
 940                 {
 941                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 942                         {
 943                                 return retval;
 944                         }
 945                 }
 946                 else
 947                 {
 948                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 949                         {
 950                                 return retval;
 951                         }
 952                 }
 953         }
 954         breakpoint->set = 0;
 955
 956         return ERROR_OK;
 957 }
 958
 959 static int
 960 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 961 {
 962         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 963
 964         if (cortex_m3->auto_bp_type)
 965         {
 966                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
 967 #ifdef ARMV7_GDB_HACKS
 968                 if (breakpoint->length != 2) {
 969                         /* XXX Hack: Replace all breakpoints with length != 2 with
 970                          * a hardware breakpoint. */
 971                         breakpoint->type = BKPT_HARD;
 972                         breakpoint->length = 2;
 973                 }
 974 #endif
 975         }
 976
 977         if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
 978         {
 979                 LOG_INFO("flash patch comparator requested outside code memory region");
 980                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 981         }
 982
 983         if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
 984         {
 985                 LOG_INFO("soft breakpoint requested in code (flash) memory region");
 986                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 987         }
 988
 989         if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
 990         {
 991                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
 992                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 993         }
 994
 995         if ((breakpoint->length != 2))
 996         {
 997                 LOG_INFO("only breakpoints of two bytes length supported");
 998                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 999         }
1000
1001         if (breakpoint->type == BKPT_HARD)
1002                 cortex_m3->fp_code_available--;
1003         cortex_m3_set_breakpoint(target, breakpoint);
1004
1005         return ERROR_OK;
1006 }
1007
1008 static int
1009 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1010 {
1011         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1012
1013         /* REVISIT why check? FBP can be updated with core running ... */
1014         if (target->state != TARGET_HALTED)
1015         {
1016                 LOG_WARNING("target not halted");
1017                 return ERROR_TARGET_NOT_HALTED;
1018         }
1019
1020         if (cortex_m3->auto_bp_type)
1021         {
1022                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1023         }
1024
1025         if (breakpoint->set)
1026         {
1027                 cortex_m3_unset_breakpoint(target, breakpoint);
1028         }
1029
1030         if (breakpoint->type == BKPT_HARD)
1031                 cortex_m3->fp_code_available++;
1032
1033         return ERROR_OK;
1034 }
1035
1036 static int
1037 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1038 {
1039         int dwt_num = 0;
1040         uint32_t mask, temp;
1041         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1042
1043         /* watchpoint params were validated earlier */
1044         mask = 0;
1045         temp = watchpoint->length;
1046         while (temp) {
1047                 temp >>= 1;
1048                 mask++;
1049         }
1050         mask--;
1051
1052         /* REVISIT Don't fully trust these "not used" records ... users
1053          * may set up breakpoints by hand, e.g. dual-address data value
1054          * watchpoint using comparator #1; comparator #0 matching cycle
1055          * count; send data trace info through ITM and TPIU; etc
1056          */
1057         struct cortex_m3_dwt_comparator *comparator;
1058
1059         for (comparator = cortex_m3->dwt_comparator_list;
1060                         comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1061                         comparator++, dwt_num++)
1062                 continue;
1063         if (dwt_num >= cortex_m3->dwt_num_comp)
1064         {
1065                 LOG_ERROR("Can not find free DWT Comparator");
1066                 return ERROR_FAIL;
1067         }
1068         comparator->used = 1;
1069         watchpoint->set = dwt_num + 1;
1070
1071         comparator->comp = watchpoint->address;
1072         target_write_u32(target, comparator->dwt_comparator_address + 0,
1073                         comparator->comp);
1074
1075         comparator->mask = mask;
1076         target_write_u32(target, comparator->dwt_comparator_address + 4,
1077                         comparator->mask);
1078
1079         switch (watchpoint->rw) {
1080         case WPT_READ:
1081                 comparator->function = 5;
1082                 break;
1083         case WPT_WRITE:
1084                 comparator->function = 6;
1085                 break;
1086         case WPT_ACCESS:
1087                 comparator->function = 7;
1088                 break;
1089         }
1090         target_write_u32(target, comparator->dwt_comparator_address + 8,
1091                         comparator->function);
1092
1093         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1094                         watchpoint->unique_id, dwt_num,
1095                         (unsigned) comparator->comp,
1096                         (unsigned) comparator->mask,
1097                         (unsigned) comparator->function);
1098         return ERROR_OK;
1099 }
1100
1101 static int
1102 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1103 {
1104         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1105         struct cortex_m3_dwt_comparator *comparator;
1106         int dwt_num;
1107
1108         if (!watchpoint->set)
1109         {
1110                 LOG_WARNING("watchpoint (wpid: %d) not set",
1111                                 watchpoint->unique_id);
1112                 return ERROR_OK;
1113         }
1114
1115         dwt_num = watchpoint->set - 1;
1116
1117         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1118                         watchpoint->unique_id, dwt_num,
1119                         (unsigned) watchpoint->address);
1120
1121         if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1122         {
1123                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1124                 return ERROR_OK;
1125         }
1126
1127         comparator = cortex_m3->dwt_comparator_list + dwt_num;
1128         comparator->used = 0;
1129         comparator->function = 0;
1130         target_write_u32(target, comparator->dwt_comparator_address + 8,
1131                         comparator->function);
1132
1133         watchpoint->set = 0;
1134
1135         return ERROR_OK;
1136 }
1137
1138 static int
1139 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1140 {
1141         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1142
1143         /* REVISIT why check? DWT can be updated with core running ... */
1144         if (target->state != TARGET_HALTED)
1145         {
1146                 LOG_WARNING("target not halted");
1147                 return ERROR_TARGET_NOT_HALTED;
1148         }
1149
1150         if (cortex_m3->dwt_comp_available < 1)
1151         {
1152                 LOG_DEBUG("no comparators?");
1153                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1154         }
1155
1156         /* hardware doesn't support data value masking */
1157         if (watchpoint->mask != ~(uint32_t)0) {
1158                 LOG_DEBUG("watchpoint value masks not supported");
1159                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1160         }
1161
1162         /* hardware allows address masks of up to 32K */
1163         unsigned mask;
1164
1165         for (mask = 0; mask < 16; mask++) {
1166                 if ((1u << mask) == watchpoint->length)
1167                         break;
1168         }
1169         if (mask == 16) {
1170                 LOG_DEBUG("unsupported watchpoint length");
1171                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1172         }
1173         if (watchpoint->address & ((1 << mask) - 1)) {
1174                 LOG_DEBUG("watchpoint address is unaligned");
1175                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1176         }
1177
1178         /* Caller doesn't seem to be able to describe watching for data
1179          * values of zero; that flags "no value".
1180          *
1181          * REVISIT This DWT may well be able to watch for specific data
1182          * values.  Requires comparator #1 to set DATAVMATCH and match
1183          * the data, and another comparator (DATAVADDR0) matching addr.
1184          */
1185         if (watchpoint->value) {
1186                 LOG_DEBUG("data value watchpoint not YET supported");
1187                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1188         }
1189
1190         cortex_m3->dwt_comp_available--;
1191         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1192
1193         return ERROR_OK;
1194 }
1195
1196 static int
1197 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1198 {
1199         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1200
1201         /* REVISIT why check? DWT can be updated with core running ... */
1202         if (target->state != TARGET_HALTED)
1203         {
1204                 LOG_WARNING("target not halted");
1205                 return ERROR_TARGET_NOT_HALTED;
1206         }
1207
1208         if (watchpoint->set)
1209         {
1210                 cortex_m3_unset_watchpoint(target, watchpoint);
1211         }
1212
1213         cortex_m3->dwt_comp_available++;
1214         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1215
1216         return ERROR_OK;
1217 }
1218
1219 static void cortex_m3_enable_watchpoints(struct target *target)
1220 {
1221         struct watchpoint *watchpoint = target->watchpoints;
1222
1223         /* set any pending watchpoints */
1224         while (watchpoint)
1225         {
1226                 if (watchpoint->set == 0)
1227                         cortex_m3_set_watchpoint(target, watchpoint);
1228                 watchpoint = watchpoint->next;
1229         }
1230 }
1231
1232 static int cortex_m3_load_core_reg_u32(struct target *target,
1233                 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1234 {
1235         int retval;
1236         struct armv7m_common *armv7m = target_to_armv7m(target);
1237         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1238
1239         /* NOTE:  we "know" here that the register identifiers used
1240          * in the v7m header match the Cortex-M3 Debug Core Register
1241          * Selector values for R0..R15, xPSR, MSP, and PSP.
1242          */
1243         switch (num) {
1244         case 0 ... 18:
1245                 /* read a normal core register */
1246                 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1247
1248                 if (retval != ERROR_OK)
1249                 {
1250                         LOG_ERROR("JTAG failure %i",retval);
1251                         return ERROR_JTAG_DEVICE_ERROR;
1252                 }
1253                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",(int)num,*value);
1254                 break;
1255
1256         case ARMV7M_PRIMASK:
1257         case ARMV7M_BASEPRI:
1258         case ARMV7M_FAULTMASK:
1259         case ARMV7M_CONTROL:
1260                 /* Cortex-M3 packages these four registers as bitfields
1261                  * in one Debug Core register.  So say r0 and r2 docs;
1262                  * it was removed from r1 docs, but still works.
1263                  */
1264                 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1265
1266                 switch (num)
1267                 {
1268                         case ARMV7M_PRIMASK:
1269                                 *value = buf_get_u32((uint8_t*)value, 0, 1);
1270                                 break;
1271
1272                         case ARMV7M_BASEPRI:
1273                                 *value = buf_get_u32((uint8_t*)value, 8, 8);
1274                                 break;
1275
1276                         case ARMV7M_FAULTMASK:
1277                                 *value = buf_get_u32((uint8_t*)value, 16, 1);
1278                                 break;
1279
1280                         case ARMV7M_CONTROL:
1281                                 *value = buf_get_u32((uint8_t*)value, 24, 2);
1282                                 break;
1283                 }
1284
1285                 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1286                 break;
1287
1288         default:
1289                 return ERROR_INVALID_ARGUMENTS;
1290         }
1291
1292         return ERROR_OK;
1293 }
1294
1295 static int cortex_m3_store_core_reg_u32(struct target *target,
1296                 enum armv7m_regtype type, uint32_t num, uint32_t value)
1297 {
1298         int retval;
1299         uint32_t reg;
1300         struct armv7m_common *armv7m = target_to_armv7m(target);
1301         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1302
1303 #ifdef ARMV7_GDB_HACKS
1304         /* If the LR register is being modified, make sure it will put us
1305          * in "thumb" mode, or an INVSTATE exception will occur. This is a
1306          * hack to deal with the fact that gdb will sometimes "forge"
1307          * return addresses, and doesn't set the LSB correctly (i.e., when
1308          * printing expressions containing function calls, it sets LR = 0.)
1309          * Valid exception return codes have bit 0 set too.
1310          */
1311         if (num == ARMV7M_R14)
1312                 value |= 0x01;
1313 #endif
1314
1315         /* NOTE:  we "know" here that the register identifiers used
1316          * in the v7m header match the Cortex-M3 Debug Core Register
1317          * Selector values for R0..R15, xPSR, MSP, and PSP.
1318          */
1319         switch (num) {
1320         case 0 ... 18:
1321                 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1322                 if (retval != ERROR_OK)
1323                 {
1324                         LOG_ERROR("JTAG failure %i", retval);
1325                         armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
1326                         return ERROR_JTAG_DEVICE_ERROR;
1327                 }
1328                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1329                 break;
1330
1331         case ARMV7M_PRIMASK:
1332         case ARMV7M_BASEPRI:
1333         case ARMV7M_FAULTMASK:
1334         case ARMV7M_CONTROL:
1335                 /* Cortex-M3 packages these four registers as bitfields
1336                  * in one Debug Core register.  So say r0 and r2 docs;
1337                  * it was removed from r1 docs, but still works.
1338                  */
1339                 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1340
1341                 switch (num)
1342                 {
1343                         case ARMV7M_PRIMASK:
1344                                 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1345                                 break;
1346
1347                         case ARMV7M_BASEPRI:
1348                                 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1349                                 break;
1350
1351                         case ARMV7M_FAULTMASK:
1352                                 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1353                                 break;
1354
1355                         case ARMV7M_CONTROL:
1356                                 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1357                                 break;
1358                 }
1359
1360                 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1361
1362                 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1363                 break;
1364
1365         default:
1366                 return ERROR_INVALID_ARGUMENTS;
1367         }
1368
1369         return ERROR_OK;
1370 }
1371
1372 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1373                 uint32_t size, uint32_t count, uint8_t *buffer)
1374 {
1375         struct armv7m_common *armv7m = target_to_armv7m(target);
1376         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1377         int retval = ERROR_INVALID_ARGUMENTS;
1378
1379         /* cortex_m3 handles unaligned memory access */
1380         if (count && buffer) {
1381                 switch (size) {
1382                 case 4:
1383                         retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1384                         break;
1385                 case 2:
1386                         retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1387                         break;
1388                 case 1:
1389                         retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1390                         break;
1391                 }
1392         }
1393
1394         return retval;
1395 }
1396
1397 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1398                 uint32_t size, uint32_t count, uint8_t *buffer)
1399 {
1400         struct armv7m_common *armv7m = target_to_armv7m(target);
1401         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1402         int retval = ERROR_INVALID_ARGUMENTS;
1403
1404         if (count && buffer) {
1405                 switch (size) {
1406                 case 4:
1407                         retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1408                         break;
1409                 case 2:
1410                         retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1411                         break;
1412                 case 1:
1413                         retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1414                         break;
1415                 }
1416         }
1417
1418         return retval;
1419 }
1420
1421 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1422                 uint32_t count, uint8_t *buffer)
1423 {
1424         return cortex_m3_write_memory(target, address, 4, count, buffer);
1425 }
1426
1427 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1428                 struct target *target)
1429 {
1430         armv7m_build_reg_cache(target);
1431         return ERROR_OK;
1432 }
1433
1434 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1435  * on r/w if the core is not running, and clear on resume or reset ... or
1436  * at least, in a post_restore_context() method.
1437  */
1438
1439 struct dwt_reg_state {
1440         struct target   *target;
1441         uint32_t        addr;
1442         uint32_t        value;  /* scratch/cache */
1443 };
1444
1445 static int cortex_m3_dwt_get_reg(struct reg *reg)
1446 {
1447         struct dwt_reg_state *state = reg->arch_info;
1448
1449         return target_read_u32(state->target, state->addr, &state->value);
1450 }
1451
1452 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1453 {
1454         struct dwt_reg_state *state = reg->arch_info;
1455
1456         return target_write_u32(state->target, state->addr,
1457                         buf_get_u32(buf, 0, reg->size));
1458 }
1459
1460 struct dwt_reg {
1461         uint32_t        addr;
1462         char            *name;
1463         unsigned        size;
1464 };
1465
1466 static struct dwt_reg dwt_base_regs[] = {
1467         { DWT_CTRL, "dwt_ctrl", 32, },
1468         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1469         /* plus some 8 bit counters, useful for profiling with TPIU */
1470 };
1471
1472 static struct dwt_reg dwt_comp[] = {
1473 #define DWT_COMPARATOR(i) \
1474                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1475                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1476                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1477         DWT_COMPARATOR(0),
1478         DWT_COMPARATOR(1),
1479         DWT_COMPARATOR(2),
1480         DWT_COMPARATOR(3),
1481 #undef DWT_COMPARATOR
1482 };
1483
1484 static const struct reg_arch_type dwt_reg_type = {
1485         .get = cortex_m3_dwt_get_reg,
1486         .set = cortex_m3_dwt_set_reg,
1487 };
1488
1489 static void
1490 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1491 {
1492         struct dwt_reg_state *state;
1493
1494         state = calloc(1, sizeof *state);
1495         if (!state)
1496                 return;
1497         state->addr = d->addr;
1498         state->target = t;
1499
1500         r->name = d->name;
1501         r->size = d->size;
1502         r->value = &state->value;
1503         r->arch_info = state;
1504         r->type = &dwt_reg_type;
1505 }
1506
1507 static void
1508 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1509 {
1510         uint32_t dwtcr;
1511         struct reg_cache *cache;
1512         struct cortex_m3_dwt_comparator *comparator;
1513         int reg, i;
1514
1515         target_read_u32(target, DWT_CTRL, &dwtcr);
1516         if (!dwtcr) {
1517                 LOG_DEBUG("no DWT");
1518                 return;
1519         }
1520
1521         cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1522         cm3->dwt_comp_available = cm3->dwt_num_comp;
1523         cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1524                         sizeof(struct cortex_m3_dwt_comparator));
1525         if (!cm3->dwt_comparator_list) {
1526 fail0:
1527                 cm3->dwt_num_comp = 0;
1528                 LOG_ERROR("out of mem");
1529                 return;
1530         }
1531
1532         cache = calloc(1, sizeof *cache);
1533         if (!cache) {
1534 fail1:
1535                 free(cm3->dwt_comparator_list);
1536                 goto fail0;
1537         }
1538         cache->name = "cortex-m3 dwt registers";
1539         cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1540         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1541         if (!cache->reg_list) {
1542                 free(cache);
1543                 goto fail1;
1544         }
1545
1546         for (reg = 0; reg < 2; reg++)
1547                 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1548                                 dwt_base_regs + reg);
1549
1550         comparator = cm3->dwt_comparator_list;
1551         for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1552                 int j;
1553
1554                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1555                 for (j = 0; j < 3; j++, reg++)
1556                         cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1557                                         dwt_comp + 3 * i + j);
1558         }
1559
1560         *register_get_last_cache_p(&target->reg_cache) = cache;
1561         cm3->dwt_cache = cache;
1562
1563         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1564                         dwtcr, cm3->dwt_num_comp,
1565                         (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1566
1567         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1568          * implement single-address data value watchpoints ... so we
1569          * won't need to check it later, when asked to set one up.
1570          */
1571 }
1572
1573 static int cortex_m3_examine(struct target *target)
1574 {
1575         int retval;
1576         uint32_t cpuid, fpcr;
1577         int i;
1578         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1579         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
1580
1581         if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1582                 return retval;
1583
1584         if (!target_was_examined(target))
1585         {
1586                 target_set_examined(target);
1587
1588                 /* Read from Device Identification Registers */
1589                 retval = target_read_u32(target, CPUID, &cpuid);
1590                 if (retval != ERROR_OK)
1591                         return retval;
1592
1593                 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1594                         LOG_DEBUG("CORTEX-M3 processor detected");
1595                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1596
1597                 /* NOTE: FPB and DWT are both optional. */
1598
1599                 /* Setup FPB */
1600                 target_read_u32(target, FP_CTRL, &fpcr);
1601                 cortex_m3->auto_bp_type = 1;
1602                 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1603                 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1604                 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1605                 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1606                 cortex_m3->fpb_enabled = fpcr & 1;
1607                 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1608                 {
1609                         cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1610                         cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1611                 }
1612                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1613
1614                 /* Setup DWT */
1615                 cortex_m3_dwt_setup(cortex_m3, target);
1616         }
1617
1618         return ERROR_OK;
1619 }
1620
1621 static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1622 {
1623         uint16_t dcrdr;
1624
1625         mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1626         *ctrl = (uint8_t)dcrdr;
1627         *value = (uint8_t)(dcrdr >> 8);
1628
1629         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1630
1631         /* write ack back to software dcc register
1632          * signify we have read data */
1633         if (dcrdr & (1 << 0))
1634         {
1635                 dcrdr = 0;
1636                 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1637         }
1638
1639         return ERROR_OK;
1640 }
1641
1642 static int cortex_m3_target_request_data(struct target *target,
1643                 uint32_t size, uint8_t *buffer)
1644 {
1645         struct armv7m_common *armv7m = target_to_armv7m(target);
1646         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1647         uint8_t data;
1648         uint8_t ctrl;
1649         uint32_t i;
1650
1651         for (i = 0; i < (size * 4); i++)
1652         {
1653                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1654                 buffer[i] = data;
1655         }
1656
1657         return ERROR_OK;
1658 }
1659
1660 static int cortex_m3_handle_target_request(void *priv)
1661 {
1662         struct target *target = priv;
1663         if (!target_was_examined(target))
1664                 return ERROR_OK;
1665         struct armv7m_common *armv7m = target_to_armv7m(target);
1666         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1667
1668         if (!target->dbg_msg_enabled)
1669                 return ERROR_OK;
1670
1671         if (target->state == TARGET_RUNNING)
1672         {
1673                 uint8_t data;
1674                 uint8_t ctrl;
1675
1676                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1677
1678                 /* check if we have data */
1679                 if (ctrl & (1 << 0))
1680                 {
1681                         uint32_t request;
1682
1683                         /* we assume target is quick enough */
1684                         request = data;
1685                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1686                         request |= (data << 8);
1687                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1688                         request |= (data << 16);
1689                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1690                         request |= (data << 24);
1691                         target_request(target, request);
1692                 }
1693         }
1694
1695         return ERROR_OK;
1696 }
1697
1698 static int cortex_m3_init_arch_info(struct target *target,
1699                 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1700 {
1701         int retval;
1702         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1703
1704         armv7m_init_arch_info(target, armv7m);
1705
1706         /* prepare JTAG information for the new target */
1707         cortex_m3->jtag_info.tap = tap;
1708         cortex_m3->jtag_info.scann_size = 4;
1709
1710         armv7m->swjdp_info.dp_select_value = -1;
1711         armv7m->swjdp_info.ap_csw_value = -1;
1712         armv7m->swjdp_info.ap_tar_value = -1;
1713         armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1714         armv7m->swjdp_info.memaccess_tck = 8;
1715         armv7m->swjdp_info.tar_autoincr_block = (1 << 12);      /* Cortex-M3 has 4096 bytes autoincrement range */
1716
1717         /* register arch-specific functions */
1718         armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1719
1720         armv7m->post_debug_entry = NULL;
1721
1722         armv7m->pre_restore_context = NULL;
1723         armv7m->post_restore_context = NULL;
1724
1725         armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1726         armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1727
1728         target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1729
1730         if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1731         {
1732                 return retval;
1733         }
1734
1735         return ERROR_OK;
1736 }
1737
1738 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1739 {
1740         struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1741
1742         cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1743         cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1744
1745         return ERROR_OK;
1746 }
1747
1748 /*--------------------------------------------------------------------------*/
1749
1750 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1751                 struct cortex_m3_common *cm3)
1752 {
1753         if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1754                 command_print(cmd_ctx, "target is not a Cortex-M3");
1755                 return ERROR_TARGET_INVALID;
1756         }
1757         return ERROR_OK;
1758 }
1759
1760 /*
1761  * Only stuff below this line should need to verify that its target
1762  * is a Cortex-M3.  Everything else should have indirected through the
1763  * cortexm3_target structure, which is only used with CM3 targets.
1764  */
1765
1766 /*
1767  * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1768  * as at least ARM-1156T2.  The interesting thing about Cortex-M is
1769  * that *only* Thumb2 disassembly matters.  There are also some small
1770  * additions to Thumb2 that are specific to ARMv7-M.
1771  */
1772 COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
1773 {
1774         int retval;
1775         struct target *target = get_current_target(CMD_CTX);
1776         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1777         uint32_t address;
1778         unsigned long count = 1;
1779         struct arm_instruction cur_instruction;
1780
1781         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1782         if (retval != ERROR_OK)
1783                 return retval;
1784
1785         errno = 0;
1786         switch (CMD_ARGC) {
1787         case 2:
1788                 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count);
1789                 /* FALL THROUGH */
1790         case 1:
1791                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1792                 break;
1793         default:
1794                 command_print(CMD_CTX,
1795                         "usage: cortex_m3 disassemble <address> [<count>]");
1796                 return ERROR_OK;
1797         }
1798
1799         while (count--) {
1800                 retval = thumb2_opcode(target, address, &cur_instruction);
1801                 if (retval != ERROR_OK)
1802                         return retval;
1803                 command_print(CMD_CTX, "%s", cur_instruction.text);
1804                 address += cur_instruction.instruction_size;
1805         }
1806
1807         return ERROR_OK;
1808 }
1809
1810 static const struct {
1811         char name[10];
1812         unsigned mask;
1813 } vec_ids[] = {
1814         { "hard_err",   VC_HARDERR, },
1815         { "int_err",    VC_INTERR, },
1816         { "bus_err",    VC_BUSERR, },
1817         { "state_err",  VC_STATERR, },
1818         { "chk_err",    VC_CHKERR, },
1819         { "nocp_err",   VC_NOCPERR, },
1820         { "mm_err",     VC_MMERR, },
1821         { "reset",      VC_CORERESET, },
1822 };
1823
1824 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1825 {
1826         struct target *target = get_current_target(CMD_CTX);
1827         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1828         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1829         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1830         uint32_t demcr = 0;
1831         int retval;
1832
1833         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1834         if (retval != ERROR_OK)
1835                 return retval;
1836
1837         mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1838
1839         if (CMD_ARGC > 0) {
1840                 unsigned catch = 0;
1841
1842                 if (CMD_ARGC == 1) {
1843                         if (strcmp(CMD_ARGV[0], "all") == 0) {
1844                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1845                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
1846                                         | VC_MMERR | VC_CORERESET;
1847                                 goto write;
1848                         } else if (strcmp(CMD_ARGV[0], "none") == 0) {
1849                                 goto write;
1850                         }
1851                 }
1852                 while (CMD_ARGC-- > 0) {
1853                         unsigned i;
1854                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1855                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
1856                                         continue;
1857                                 catch |= vec_ids[i].mask;
1858                                 break;
1859                         }
1860                         if (i == ARRAY_SIZE(vec_ids)) {
1861                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
1862                                 return ERROR_INVALID_ARGUMENTS;
1863                         }
1864                 }
1865 write:
1866                 demcr &= ~0xffff;
1867                 demcr |= catch;
1868
1869                 /* write, but don't assume it stuck */
1870                 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
1871                 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1872         }
1873
1874         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
1875         {
1876                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
1877                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
1878         }
1879
1880         return ERROR_OK;
1881 }
1882
1883 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
1884 {
1885         struct target *target = get_current_target(CMD_CTX);
1886         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1887         int retval;
1888
1889         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1890         if (retval != ERROR_OK)
1891                 return retval;
1892
1893         if (target->state != TARGET_HALTED)
1894         {
1895                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1896                 return ERROR_OK;
1897         }
1898
1899         if (CMD_ARGC > 0)
1900         {
1901                 if (!strcmp(CMD_ARGV[0], "on"))
1902                 {
1903                         cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
1904                 }
1905                 else if (!strcmp(CMD_ARGV[0], "off"))
1906                 {
1907                         cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
1908                 }
1909                 else
1910                 {
1911                         command_print(CMD_CTX, "usage: cortex_m3 maskisr ['on'|'off']");
1912                 }
1913         }
1914
1915         command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
1916                         (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
1917
1918         return ERROR_OK;
1919 }
1920
1921 static int cortex_m3_register_commands(struct command_context *cmd_ctx)
1922 {
1923         int retval;
1924         struct command *cortex_m3_cmd;
1925
1926         retval = armv7m_register_commands(cmd_ctx);
1927
1928         cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3",
1929                         NULL, COMMAND_ANY, "cortex_m3 specific commands");
1930
1931         register_command(cmd_ctx, cortex_m3_cmd, "disassemble",
1932                         handle_cortex_m3_disassemble_command, COMMAND_EXEC,
1933                         "disassemble Thumb2 instructions <address> [<count>]");
1934         register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
1935                         handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC,
1936                         "mask cortex_m3 interrupts ['on'|'off']");
1937         register_command(cmd_ctx, cortex_m3_cmd, "vector_catch",
1938                         handle_cortex_m3_vector_catch_command, COMMAND_EXEC,
1939                         "catch hardware vectors ['all'|'none'|<list>]");
1940
1941         return retval;
1942 }
1943
1944 struct target_type cortexm3_target =
1945 {
1946         .name = "cortex_m3",
1947
1948         .poll = cortex_m3_poll,
1949         .arch_state = armv7m_arch_state,
1950
1951         .target_request_data = cortex_m3_target_request_data,
1952
1953         .halt = cortex_m3_halt,
1954         .resume = cortex_m3_resume,
1955         .step = cortex_m3_step,
1956
1957         .assert_reset = cortex_m3_assert_reset,
1958         .deassert_reset = cortex_m3_deassert_reset,
1959         .soft_reset_halt = cortex_m3_soft_reset_halt,
1960
1961         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
1962
1963         .read_memory = cortex_m3_read_memory,
1964         .write_memory = cortex_m3_write_memory,
1965         .bulk_write_memory = cortex_m3_bulk_write_memory,
1966         .checksum_memory = armv7m_checksum_memory,
1967         .blank_check_memory = armv7m_blank_check_memory,
1968
1969         .run_algorithm = armv7m_run_algorithm,
1970
1971         .add_breakpoint = cortex_m3_add_breakpoint,
1972         .remove_breakpoint = cortex_m3_remove_breakpoint,
1973         .add_watchpoint = cortex_m3_add_watchpoint,
1974         .remove_watchpoint = cortex_m3_remove_watchpoint,
1975
1976         .register_commands = cortex_m3_register_commands,
1977         .target_create = cortex_m3_target_create,
1978         .init_target = cortex_m3_init_target,
1979         .examine = cortex_m3_examine,
1980 };