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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "replacements.h"
  28
  29 #include "cortex_m3.h"
  30 #include "armv7m.h"
  31
  32 #include "register.h"
  33 #include "target.h"
  34 #include "target_request.h"
  35 #include "log.h"
  36 #include "jtag.h"
  37 #include "arm_jtag.h"
  38
  39 #include <stdlib.h>
  40 #include <string.h>
  41
  42 /* cli handling */
  43 int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
  44
  45 /* forward declarations */
  46 void cortex_m3_enable_breakpoints(struct target_s *target);
  47 void cortex_m3_enable_watchpoints(struct target_s *target);
  48 int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  49 int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  50 int cortex_m3_quit();
  51 int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value);
  52 int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value);
  53 int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer);
  54 int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target);
  55
  56 #ifdef ARMV7_GDB_HACKS
  57 extern u8 armv7m_gdb_dummy_cpsr_value[];
  58 extern reg_t armv7m_gdb_dummy_cpsr_reg;
  59 #endif
  60
  61 target_type_t cortexm3_target =
  62 {
  63         .name = "cortex_m3",
  64
  65         .poll = cortex_m3_poll,
  66         .arch_state = armv7m_arch_state,
  67
  68         .target_request_data = cortex_m3_target_request_data,
  69
  70         .halt = cortex_m3_halt,
  71         .resume = cortex_m3_resume,
  72         .step = cortex_m3_step,
  73
  74         .assert_reset = cortex_m3_assert_reset,
  75         .deassert_reset = cortex_m3_deassert_reset,
  76         .soft_reset_halt = cortex_m3_soft_reset_halt,
  77
  78         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
  79
  80         .read_memory = cortex_m3_read_memory,
  81         .write_memory = cortex_m3_write_memory,
  82         .bulk_write_memory = cortex_m3_bulk_write_memory,
  83         .checksum_memory = armv7m_checksum_memory,
  84
  85         .run_algorithm = armv7m_run_algorithm,
  86
  87         .add_breakpoint = cortex_m3_add_breakpoint,
  88         .remove_breakpoint = cortex_m3_remove_breakpoint,
  89         .add_watchpoint = cortex_m3_add_watchpoint,
  90         .remove_watchpoint = cortex_m3_remove_watchpoint,
  91
  92         .register_commands = cortex_m3_register_commands,
  93         .target_command = cortex_m3_target_command,
  94         .init_target = cortex_m3_init_target,
  95         .examine = cortex_m3_examine,
  96         .quit = cortex_m3_quit
  97 };
  98
  99 int cortex_m3_clear_halt(target_t *target)
 100 {
 101         /* get pointers to arch-specific information */
 102         armv7m_common_t *armv7m = target->arch_info;
 103         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 104         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 105
 106     /* Read Debug Fault Status Register */
 107     ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 108     /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
 109     ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
 110     LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr);
 111
 112     return ERROR_OK;
 113 }
 114
 115 int cortex_m3_single_step_core(target_t *target)
 116 {
 117         /* get pointers to arch-specific information */
 118         armv7m_common_t *armv7m = target->arch_info;
 119         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 120         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 121
 122         if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
 123                 ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN );
 124         ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN );
 125         cortex_m3->dcb_dhcsr |= C_MASKINTS;
 126         LOG_DEBUG(" ");
 127         cortex_m3_clear_halt(target);
 128
 129         return ERROR_OK;
 130 }
 131
 132 int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_invalue, &r0_outvalue */ )
 133 {
 134         /* get pointers to arch-specific information */
 135         armv7m_common_t *armv7m = target->arch_info;
 136         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 137         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 138         u32 savedram;
 139         int retvalue;
 140
 141         ahbap_read_system_u32(swjdp, 0x20000000, &savedram);
 142         ahbap_write_system_u32(swjdp, 0x20000000, opcode);
 143         ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
 144         cortex_m3_single_step_core(target);
 145         armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
 146         retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram);
 147
 148         return retvalue;
 149 }
 150
 151 #if 0
 152 /* Enable interrupts */
 153 int cortex_m3_cpsie(target_t *target, u32 IF)
 154 {
 155         return cortex_m3_exec_opcode(target, ARMV7M_T_CPSIE(IF), 2);
 156 }
 157
 158 /* Disable interrupts */
 159 int cortex_m3_cpsid(target_t *target, u32 IF)
 160 {
 161         return cortex_m3_exec_opcode(target, ARMV7M_T_CPSID(IF), 2);
 162 }
 163 #endif
 164
 165 int cortex_m3_endreset_event(target_t *target)
 166 {
 167         int i;
 168         u32 dcb_demcr;
 169
 170         /* get pointers to arch-specific information */
 171         armv7m_common_t *armv7m = target->arch_info;
 172         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 173         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 174         cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
 175         cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
 176
 177         ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 178         LOG_DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
 179
 180         ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
 181
 182         /* Enable debug requests */
 183         ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 184         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 185                 ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN );
 186         /* Enable trace and dwt */
 187         ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR );
 188         /* Monitor bus faults */
 189         ahbap_write_system_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA );
 190
 191         /* Enable FPB */
 192         target_write_u32(target, FP_CTRL, 3);
 193
 194         /* Restore FPB registers */
 195         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
 196         {
 197                 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 198         }
 199
 200         /* Restore DWT registers */
 201         for (i = 0; i < cortex_m3->dwt_num_comp; i++)
 202         {
 203                 target_write_u32(target, dwt_list[i].dwt_comparator_address, dwt_list[i].comp);
 204                 target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x4, dwt_list[i].mask);
 205                 target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x8, dwt_list[i].function);
 206         }
 207         swjdp_transaction_endcheck(swjdp);
 208
 209         armv7m_invalidate_core_regs(target);
 210         return ERROR_OK;
 211 }
 212
 213 int cortex_m3_examine_debug_reason(target_t *target)
 214 {
 215         /* get pointers to arch-specific information */
 216         armv7m_common_t *armv7m = target->arch_info;
 217         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 218
 219         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
 220         /* only check the debug reason if we don't know it already */
 221
 222         if ((target->debug_reason != DBG_REASON_DBGRQ)
 223                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 224         {
 225                 /*  INCOMPLETE */
 226
 227                 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 228                 {
 229                         target->debug_reason = DBG_REASON_BREAKPOINT;
 230                         if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 231                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 232                 }
 233                 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 234                         target->debug_reason = DBG_REASON_WATCHPOINT;
 235         }
 236
 237         return ERROR_OK;
 238 }
 239
 240 int cortex_m3_examine_exception_reason(target_t *target)
 241 {
 242         u32 shcsr, except_sr, cfsr = -1, except_ar = -1;
 243
 244         /* get pointers to arch-specific information */
 245         armv7m_common_t *armv7m = target->arch_info;
 246         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 247         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 248
 249         ahbap_read_system_u32(swjdp, NVIC_SHCSR, &shcsr);
 250         switch (armv7m->exception_number)
 251         {
 252                 case 2: /* NMI */
 253                         break;
 254                 case 3: /* Hard Fault */
 255                         ahbap_read_system_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 256                         if (except_sr & 0x40000000)
 257                         {
 258                                 ahbap_read_system_u32(swjdp, NVIC_CFSR, &cfsr);
 259                         }
 260                         break;
 261                 case 4: /* Memory Management */
 262                         ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
 263                         ahbap_read_system_u32(swjdp, NVIC_MMFAR, &except_ar);
 264                         break;
 265                 case 5: /* Bus Fault */
 266                         ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
 267                         ahbap_read_system_u32(swjdp, NVIC_BFAR, &except_ar);
 268                         break;
 269                 case 6: /* Usage Fault */
 270                         ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
 271                         break;
 272                 case 11:        /* SVCall */
 273                         break;
 274                 case 12:        /* Debug Monitor */
 275                         ahbap_read_system_u32(swjdp, NVIC_DFSR, &except_sr);
 276                         break;
 277                 case 14:        /* PendSV */
 278                         break;
 279                 case 15:        /* SysTick */
 280                         break;
 281                 default:
 282                         except_sr = 0;
 283                         break;
 284         }
 285         swjdp_transaction_endcheck(swjdp);
 286     LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \
 287         shcsr, except_sr, cfsr, except_ar);
 288         return ERROR_OK;
 289 }
 290
 291 int cortex_m3_debug_entry(target_t *target)
 292 {
 293         int i;
 294         u32 xPSR;
 295         int retval;
 296
 297         /* get pointers to arch-specific information */
 298         armv7m_common_t *armv7m = target->arch_info;
 299         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 300         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 301
 302         LOG_DEBUG(" ");
 303         if (armv7m->pre_debug_entry)
 304                 armv7m->pre_debug_entry(target);
 305
 306         cortex_m3_clear_halt(target);
 307         ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 308
 309         if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
 310                 return retval;
 311
 312         /* Examine target state and mode */
 313         /* First load register acessible through core debug port*/
 314         for (i = 0; i < ARMV7M_PRIMASK; i++)
 315         {
 316                 if (!armv7m->core_cache->reg_list[i].valid)
 317                         armv7m->read_core_reg(target, i);
 318         }
 319
 320         xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
 321
 322 #ifdef ARMV7_GDB_HACKS
 323         /* copy real xpsr reg for gdb, setting thumb bit */
 324         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
 325         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
 326         armv7m_gdb_dummy_cpsr_reg.valid = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
 327         armv7m_gdb_dummy_cpsr_reg.dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty;
 328 #endif
 329
 330         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 331         if (xPSR & 0xf00)
 332         {
 333                 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
 334                 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 335         }
 336
 337         /* Now we can load SP core registers */
 338         for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++)
 339         {
 340                 if (!armv7m->core_cache->reg_list[i].valid)
 341                         armv7m->read_core_reg(target, i);
 342         }
 343
 344         /* Are we in an exception handler */
 345         if (xPSR & 0x1FF)
 346         {
 347                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 348                 armv7m->exception_number = (xPSR & 0x1FF);
 349         }
 350         else
 351         {
 352                 armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
 353                 armv7m->exception_number = 0;
 354         }
 355
 356         if (armv7m->exception_number)
 357         {
 358                 cortex_m3_examine_exception_reason(target);
 359         }
 360
 361         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", armv7m_mode_strings[armv7m->core_mode], \
 362                 *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]);
 363
 364         if (armv7m->post_debug_entry)
 365                 armv7m->post_debug_entry(target);
 366
 367         return ERROR_OK;
 368 }
 369
 370 int cortex_m3_poll(target_t *target)
 371 {
 372         int retval;
 373         u32 prev_target_state = target->state;
 374
 375         /* get pointers to arch-specific information */
 376         armv7m_common_t *armv7m = target->arch_info;
 377         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 378         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 379
 380         /* Read from Debug Halting Control and Status Register */
 381         retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 382         if (retval != ERROR_OK)
 383         {
 384                 target->state = TARGET_UNKNOWN;
 385                 return retval;
 386         }
 387
 388         if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 389         {
 390                 /* check if still in reset */
 391                 ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 392
 393                 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 394                 {
 395                         target->state = TARGET_RESET;
 396                         return ERROR_OK;
 397                 }
 398         }
 399
 400         if (target->state == TARGET_RESET)
 401         {
 402                 /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
 403                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%x", cortex_m3->dcb_dhcsr);
 404                 cortex_m3_endreset_event(target);
 405                 target->state = TARGET_RUNNING;
 406                 prev_target_state = TARGET_RUNNING;
 407         }
 408
 409         if (cortex_m3->dcb_dhcsr & S_HALT)
 410         {
 411                 target->state = TARGET_HALTED;
 412
 413                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 414                 {
 415                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 416                                 return retval;
 417
 418                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 419                 }
 420                 if (prev_target_state == TARGET_DEBUG_RUNNING)
 421                 {
 422                         LOG_DEBUG(" ");
 423                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 424                                 return retval;
 425
 426                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 427                 }
 428         }
 429
 430         /*
 431         if (cortex_m3->dcb_dhcsr & S_SLEEP)
 432                 target->state = TARGET_SLEEP;
 433         */
 434
 435 #if 0
 436     /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script  */
 437         ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 438         LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]);
 439 #endif
 440
 441         return ERROR_OK;
 442 }
 443
 444 int cortex_m3_halt(target_t *target)
 445 {
 446         /* get pointers to arch-specific information */
 447         armv7m_common_t *armv7m = target->arch_info;
 448         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 449         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 450
 451         LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
 452
 453         if (target->state == TARGET_HALTED)
 454         {
 455                 LOG_DEBUG("target was already halted");
 456                 return ERROR_OK;
 457         }
 458
 459         if (target->state == TARGET_UNKNOWN)
 460         {
 461                 LOG_WARNING("target was in unknown state when halt was requested");
 462         }
 463
 464         if (target->state == TARGET_RESET)
 465         {
 466                 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
 467                 {
 468                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 469                         return ERROR_TARGET_FAILURE;
 470                 }
 471                 else
 472                 {
 473                         /* we came here in a reset_halt or reset_init sequence
 474                          * debug entry was already prepared in cortex_m3_prepare_reset_halt()
 475                          */
 476                         target->debug_reason = DBG_REASON_DBGRQ;
 477
 478                         return ERROR_OK;
 479                 }
 480         }
 481
 482         /* Write to Debug Halting Control and Status Register */
 483         ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT );
 484
 485         target->debug_reason = DBG_REASON_DBGRQ;
 486
 487         return ERROR_OK;
 488 }
 489
 490 int cortex_m3_soft_reset_halt(struct target_s *target)
 491 {
 492         /* get pointers to arch-specific information */
 493         armv7m_common_t *armv7m = target->arch_info;
 494         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 495         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 496         u32 dcb_dhcsr = 0;
 497         int retval, timeout = 0;
 498
 499         /* Enter debug state on reset, cf. end_reset_event() */
 500         ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET );
 501
 502         /* Request a reset */
 503         ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET );
 504         target->state = TARGET_RESET;
 505
 506         /* registers are now invalid */
 507         armv7m_invalidate_core_regs(target);
 508
 509         while (timeout < 100)
 510         {
 511                 retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 512                 if (retval == ERROR_OK)
 513                 {
 514                     ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 515                         if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 516                         {
 517                                 LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr);
 518                                 cortex_m3_poll(target);
 519                                 return ERROR_OK;
 520                         }
 521                         else
 522                                 LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms", dcb_dhcsr, timeout);
 523                 }
 524                 timeout++;
 525                 usleep(1000);
 526         }
 527
 528         return ERROR_OK;
 529 }
 530
 531 int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
 532 {
 533         /* get pointers to arch-specific information */
 534         armv7m_common_t *armv7m = target->arch_info;
 535         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 536         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 537         breakpoint_t *breakpoint = NULL;
 538         u32 dcb_dhcsr, resume_pc;
 539
 540         if (target->state != TARGET_HALTED)
 541         {
 542                 LOG_WARNING("target not halted");
 543                 return ERROR_TARGET_NOT_HALTED;
 544         }
 545
 546         if (!debug_execution)
 547         {
 548                 target_free_all_working_areas(target);
 549                 cortex_m3_enable_breakpoints(target);
 550                 cortex_m3_enable_watchpoints(target);
 551
 552                 /* TODOLATER Interrupt handling/disable for debug execution, cache ... ... */
 553         }
 554
 555         dcb_dhcsr = DBGKEY | C_DEBUGEN;
 556         if (debug_execution)
 557         {
 558                 /* Disable interrupts */
 559                 /*
 560                    We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
 561                    This is probably the same inssue as Cortex-M3 Errata 377493:
 562                    C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken.
 563                 */
 564                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
 565                 /* Make sure we are in Thumb mode */
 566                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
 567                         buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24));
 568         }
 569
 570         /* current = 1: continue on current pc, otherwise continue at <address> */
 571         if (!current)
 572         {
 573                 buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
 574                 armv7m->core_cache->reg_list[15].dirty = 1;
 575                 armv7m->core_cache->reg_list[15].valid = 1;
 576         }
 577
 578         resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32);
 579
 580         armv7m_restore_context(target);
 581
 582         /* the front-end may request us not to handle breakpoints */
 583         if (handle_breakpoints)
 584         {
 585                 /* Single step past breakpoint at current address */
 586                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 587                 {
 588                         LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
 589                         cortex_m3_unset_breakpoint(target, breakpoint);
 590                         cortex_m3_single_step_core(target);
 591                         cortex_m3_set_breakpoint(target, breakpoint);
 592                 }
 593         }
 594
 595         /* Set/Clear C_MASKINTS in a separate operation */
 596         if ((cortex_m3->dcb_dhcsr & C_MASKINTS) != (dcb_dhcsr & C_MASKINTS))
 597                 ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr | C_HALT );
 598
 599         /* Restart core */
 600         ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr );
 601         target->debug_reason = DBG_REASON_NOTHALTED;
 602
 603         /* registers are now invalid */
 604         armv7m_invalidate_core_regs(target);
 605         if (!debug_execution)
 606         {
 607                 target->state = TARGET_RUNNING;
 608                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 609                 LOG_DEBUG("target resumed at 0x%x",resume_pc);
 610         }
 611         else
 612         {
 613                 target->state = TARGET_DEBUG_RUNNING;
 614                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 615                 LOG_DEBUG("target debug resumed at 0x%x",resume_pc);
 616         }
 617
 618         return ERROR_OK;
 619 }
 620
 621 /* int irqstepcount=0; */
 622 int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
 623 {
 624         /* get pointers to arch-specific information */
 625         armv7m_common_t *armv7m = target->arch_info;
 626         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 627         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 628         breakpoint_t *breakpoint = NULL;
 629
 630         if (target->state != TARGET_HALTED)
 631         {
 632                 LOG_WARNING("target not halted");
 633                 return ERROR_TARGET_NOT_HALTED;
 634         }
 635
 636         /* current = 1: continue on current pc, otherwise continue at <address> */
 637         if (!current)
 638                 buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
 639
 640         /* the front-end may request us not to handle breakpoints */
 641         if (handle_breakpoints)
 642                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32))))
 643                         cortex_m3_unset_breakpoint(target, breakpoint);
 644
 645         target->debug_reason = DBG_REASON_SINGLESTEP;
 646
 647         armv7m_restore_context(target);
 648
 649         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 650
 651         if (cortex_m3->dcb_dhcsr & C_MASKINTS)
 652                 ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN );
 653         ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY| C_STEP | C_DEBUGEN);
 654         ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 655
 656         /* registers are now invalid */
 657         armv7m_invalidate_core_regs(target);
 658
 659         if (breakpoint)
 660                 cortex_m3_set_breakpoint(target, breakpoint);
 661
 662         LOG_DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 663
 664         cortex_m3_debug_entry(target);
 665         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 666
 667         LOG_DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 668         return ERROR_OK;
 669 }
 670
 671 int cortex_m3_assert_reset(target_t *target)
 672 {
 673         armv7m_common_t *armv7m = target->arch_info;
 674         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 675         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
 676
 677         LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
 678
 679         if (!(jtag_reset_config & RESET_HAS_SRST))
 680         {
 681                 LOG_ERROR("Can't assert SRST");
 682                 return ERROR_FAIL;
 683         }
 684
 685         /* Enable debug requests */
 686         ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 687         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 688                 ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN );
 689
 690         ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
 691
 692         if (target->reset_mode == RESET_RUN)
 693         {
 694                 /* Set/Clear C_MASKINTS in a separate operation */
 695                 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
 696                         ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT );
 697
 698                 cortex_m3_clear_halt(target);
 699
 700                 /* Enter debug state on reset, cf. end_reset_event() */
 701                 ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
 702         }
 703         else
 704         {
 705                 /* Enter debug state on reset, cf. end_reset_event() */
 706                 ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET );
 707         }
 708
 709         if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 710         {
 711                 jtag_add_reset(1, 1);
 712         }
 713         else
 714         {
 715                 jtag_add_reset(0, 1);
 716         }
 717
 718         target->state = TARGET_RESET;
 719         jtag_add_sleep(50000);
 720
 721         armv7m_invalidate_core_regs(target);
 722
 723         return ERROR_OK;
 724 }
 725
 726 int cortex_m3_deassert_reset(target_t *target)
 727 {
 728         LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
 729
 730         /* deassert reset lines */
 731         jtag_add_reset(0, 0);
 732
 733         return ERROR_OK;
 734 }
 735
 736 void cortex_m3_enable_breakpoints(struct target_s *target)
 737 {
 738         breakpoint_t *breakpoint = target->breakpoints;
 739
 740         /* set any pending breakpoints */
 741         while (breakpoint)
 742         {
 743                 if (breakpoint->set == 0)
 744                         cortex_m3_set_breakpoint(target, breakpoint);
 745                 breakpoint = breakpoint->next;
 746         }
 747 }
 748
 749 int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 750 {
 751         int fp_num=0;
 752         u32 hilo;
 753
 754         /* get pointers to arch-specific information */
 755         armv7m_common_t *armv7m = target->arch_info;
 756         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 757
 758         cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list;
 759
 760         if (breakpoint->set)
 761         {
 762                 LOG_WARNING("breakpoint already set");
 763                 return ERROR_OK;
 764         }
 765
 766         if (cortex_m3->auto_bp_type)
 767         {
 768                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
 769         }
 770
 771         if (breakpoint->type == BKPT_HARD)
 772         {
 773                 while(comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
 774                         fp_num++;
 775                 if (fp_num >= cortex_m3->fp_num_code)
 776                 {
 777                         LOG_DEBUG("ERROR Can not find free FP Comparator");
 778                         LOG_WARNING("ERROR Can not find free FP Comparator");
 779                         exit(-1);
 780                 }
 781                 breakpoint->set = fp_num + 1;
 782                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
 783                 comparator_list[fp_num].used = 1;
 784                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
 785                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
 786                 LOG_DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value);
 787         }
 788         else if (breakpoint->type == BKPT_SOFT)
 789         {
 790                 u8 code[4];
 791                 buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
 792                 target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr);
 793                 target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code);
 794                 breakpoint->set = 0x11; /* Any nice value but 0 */
 795         }
 796
 797         return ERROR_OK;
 798 }
 799
 800 int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 801 {
 802         /* get pointers to arch-specific information */
 803         armv7m_common_t *armv7m = target->arch_info;
 804         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 805         cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list;
 806
 807         if (!breakpoint->set)
 808         {
 809                 LOG_WARNING("breakpoint not set");
 810                 return ERROR_OK;
 811         }
 812
 813         if (breakpoint->type == BKPT_HARD)
 814         {
 815                 int fp_num = breakpoint->set - 1;
 816                 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
 817                 {
 818                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
 819                         return ERROR_OK;
 820                 }
 821                 comparator_list[fp_num].used = 0;
 822                 comparator_list[fp_num].fpcr_value = 0;
 823                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
 824         }
 825         else
 826         {
 827                 /* restore original instruction (kept in target endianness) */
 828                 if (breakpoint->length == 4)
 829                 {
 830                         target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr);
 831                 }
 832                 else
 833                 {
 834                         target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr);
 835                 }
 836         }
 837         breakpoint->set = 0;
 838
 839         return ERROR_OK;
 840 }
 841
 842 int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 843 {
 844         /* get pointers to arch-specific information */
 845         armv7m_common_t *armv7m = target->arch_info;
 846         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 847
 848         if (cortex_m3->auto_bp_type)
 849         {
 850                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
 851 #ifdef ARMV7_GDB_HACKS
 852                 if (breakpoint->length != 2) {
 853                         /* XXX Hack: Replace all breakpoints with length != 2 with
 854                          * a hardware breakpoint. */
 855                         breakpoint->type = BKPT_HARD;
 856                         breakpoint->length = 2;
 857                 }
 858 #endif
 859         }
 860
 861         if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
 862         {
 863                 LOG_INFO("flash patch comparator requested outside code memory region");
 864                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 865         }
 866
 867         if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
 868         {
 869                 LOG_INFO("soft breakpoint requested in code (flash) memory region");
 870                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 871         }
 872
 873         if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
 874         {
 875                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
 876                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 877         }
 878
 879         if ((breakpoint->length != 2))
 880         {
 881                 LOG_INFO("only breakpoints of two bytes length supported");
 882                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 883         }
 884
 885         if (breakpoint->type == BKPT_HARD)
 886                 cortex_m3->fp_code_available--;
 887         cortex_m3_set_breakpoint(target, breakpoint);
 888
 889         return ERROR_OK;
 890 }
 891
 892 int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 893 {
 894         /* get pointers to arch-specific information */
 895         armv7m_common_t *armv7m = target->arch_info;
 896         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 897
 898         if (target->state != TARGET_HALTED)
 899         {
 900                 LOG_WARNING("target not halted");
 901                 return ERROR_TARGET_NOT_HALTED;
 902         }
 903
 904         if (cortex_m3->auto_bp_type)
 905         {
 906                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
 907         }
 908
 909         if (breakpoint->set)
 910         {
 911                 cortex_m3_unset_breakpoint(target, breakpoint);
 912         }
 913
 914         if (breakpoint->type == BKPT_HARD)
 915                 cortex_m3->fp_code_available++;
 916
 917         return ERROR_OK;
 918 }
 919
 920 int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 921 {
 922         int dwt_num=0;
 923         u32 mask, temp;
 924
 925         /* get pointers to arch-specific information */
 926         armv7m_common_t *armv7m = target->arch_info;
 927         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 928         cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list;
 929
 930         if (watchpoint->set)
 931         {
 932                 LOG_WARNING("watchpoint already set");
 933                 return ERROR_OK;
 934         }
 935
 936         if (watchpoint->mask == 0xffffffffu)
 937         {
 938                 while(comparator_list[dwt_num].used && (dwt_num < cortex_m3->dwt_num_comp))
 939                         dwt_num++;
 940                 if (dwt_num >= cortex_m3->dwt_num_comp)
 941                 {
 942                         LOG_DEBUG("ERROR Can not find free DWT Comparator");
 943                         LOG_WARNING("ERROR Can not find free DWT Comparator");
 944                         return -1;
 945                 }
 946                 watchpoint->set = dwt_num + 1;
 947                 mask = 0;
 948                 temp = watchpoint->length;
 949                 while (temp > 1)
 950                 {
 951                         temp = temp / 2;
 952                         mask++;
 953                 }
 954                 comparator_list[dwt_num].used = 1;
 955                 comparator_list[dwt_num].comp = watchpoint->address;
 956                 comparator_list[dwt_num].mask = mask;
 957                 comparator_list[dwt_num].function = watchpoint->rw + 5;
 958                 target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp);
 959                 target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x4, comparator_list[dwt_num].mask);
 960                 target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function);
 961                 LOG_DEBUG("dwt_num %i 0x%x 0x%x 0x%x", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function);
 962         }
 963         else
 964         {
 965                 LOG_WARNING("Cannot watch data values");  /* Move this test to add_watchpoint */
 966                 return ERROR_OK;
 967         }
 968
 969         return ERROR_OK;
 970
 971 }
 972
 973 int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 974 {
 975         /* get pointers to arch-specific information */
 976         armv7m_common_t *armv7m = target->arch_info;
 977         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
 978         cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list;
 979         int dwt_num;
 980
 981         if (!watchpoint->set)
 982         {
 983                 LOG_WARNING("watchpoint not set");
 984                 return ERROR_OK;
 985         }
 986
 987         dwt_num = watchpoint->set - 1;
 988
 989         if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
 990         {
 991                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
 992                 return ERROR_OK;
 993         }
 994         comparator_list[dwt_num].used = 0;
 995         comparator_list[dwt_num].function = 0;
 996         target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function);
 997
 998         watchpoint->set = 0;
 999
1000         return ERROR_OK;
1001 }
1002
1003 int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1004 {
1005         /* get pointers to arch-specific information */
1006         armv7m_common_t *armv7m = target->arch_info;
1007         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
1008
1009         if (target->state != TARGET_HALTED)
1010         {
1011                 LOG_WARNING("target not halted");
1012                 return ERROR_TARGET_NOT_HALTED;
1013         }
1014
1015         if (cortex_m3->dwt_comp_available < 1)
1016         {
1017                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1018         }
1019
1020         if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
1021         {
1022                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1023         }
1024
1025         cortex_m3->dwt_comp_available--;
1026
1027         return ERROR_OK;
1028 }
1029
1030 int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1031 {
1032         /* get pointers to arch-specific information */
1033         armv7m_common_t *armv7m = target->arch_info;
1034         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
1035
1036         if (target->state != TARGET_HALTED)
1037         {
1038                 LOG_WARNING("target not halted");
1039                 return ERROR_TARGET_NOT_HALTED;
1040         }
1041
1042         if (watchpoint->set)
1043         {
1044                 cortex_m3_unset_watchpoint(target, watchpoint);
1045         }
1046
1047         cortex_m3->dwt_comp_available++;
1048
1049         return ERROR_OK;
1050 }
1051
1052 void cortex_m3_enable_watchpoints(struct target_s *target)
1053 {
1054         watchpoint_t *watchpoint = target->watchpoints;
1055
1056         /* set any pending watchpoints */
1057         while (watchpoint)
1058         {
1059                 if (watchpoint->set == 0)
1060                         cortex_m3_set_watchpoint(target, watchpoint);
1061                 watchpoint = watchpoint->next;
1062         }
1063 }
1064
1065 int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 * value)
1066 {
1067         int retval;
1068         /* get pointers to arch-specific information */
1069         armv7m_common_t *armv7m = target->arch_info;
1070         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
1071         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
1072
1073         if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
1074         {
1075                 /* read a normal core register */
1076                 retval = ahbap_read_coreregister_u32(swjdp, value, num);
1077
1078                 if (retval != ERROR_OK)
1079                 {
1080                         LOG_ERROR("JTAG failure %i",retval);
1081                         return ERROR_JTAG_DEVICE_ERROR;
1082                 }
1083                 LOG_DEBUG("load from core reg %i  value 0x%x",num,*value);
1084         }
1085         else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
1086         {
1087                 /* read other registers */
1088                 ahbap_read_coreregister_u32(swjdp, value, 20);
1089
1090                 switch (num)
1091                 {
1092                         case 19:
1093                                 *value = buf_get_u32((u8*)value, 0, 8);
1094                                 break;
1095
1096                         case 20:
1097                                 *value = buf_get_u32((u8*)value, 8, 8);
1098                                 break;
1099
1100                         case 21:
1101                                 *value = buf_get_u32((u8*)value, 16, 8);
1102                                 break;
1103
1104                         case 22:
1105                                 *value = buf_get_u32((u8*)value, 24, 8);
1106                                 break;
1107                 }
1108
1109                 LOG_DEBUG("load from special reg %i value 0x%x", num, *value);
1110         }
1111         else
1112         {
1113                 return ERROR_INVALID_ARGUMENTS;
1114         }
1115
1116         return ERROR_OK;
1117 }
1118
1119 int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value)
1120 {
1121         int retval;
1122         u32 reg;
1123
1124         /* get pointers to arch-specific information */
1125         armv7m_common_t *armv7m = target->arch_info;
1126         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
1127         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
1128
1129 #ifdef ARMV7_GDB_HACKS
1130         /* If the LR register is being modified, make sure it will put us
1131          * in "thumb" mode, or an INVSTATE exception will occur. This is a
1132          * hack to deal with the fact that gdb will sometimes "forge"
1133          * return addresses, and doesn't set the LSB correctly (i.e., when
1134          * printing expressions containing function calls, it sets LR=0.) */
1135
1136         if (num == 14)
1137                 value |= 0x01;
1138 #endif
1139
1140         if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
1141         {
1142                 retval = ahbap_write_coreregister_u32(swjdp, value, num);
1143                 if (retval != ERROR_OK)
1144                 {
1145                         LOG_ERROR("JTAG failure %i", retval);
1146                         armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
1147                         return ERROR_JTAG_DEVICE_ERROR;
1148                 }
1149                 LOG_DEBUG("write core reg %i value 0x%x", num, value);
1150         }
1151         else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
1152         {
1153                 /* write other registers */
1154
1155                 ahbap_read_coreregister_u32(swjdp, &reg, 20);
1156
1157                 switch (num)
1158                 {
1159                         case 19:
1160                                 buf_set_u32((u8*)&reg, 0, 8, value);
1161                                 break;
1162
1163                         case 20:
1164                                 buf_set_u32((u8*)&reg, 8, 8, value);
1165                                 break;
1166
1167                         case 21:
1168                                 buf_set_u32((u8*)&reg, 16, 8, value);
1169                                 break;
1170
1171                         case 22:
1172                                 buf_set_u32((u8*)&reg, 24, 8, value);
1173                                 break;
1174                 }
1175
1176                 ahbap_write_coreregister_u32(swjdp, reg, 20);
1177
1178                 LOG_DEBUG("write special reg %i value 0x%x ", num, value);
1179         }
1180         else
1181         {
1182                 return ERROR_INVALID_ARGUMENTS;
1183         }
1184
1185         return ERROR_OK;
1186 }
1187
1188 int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1189 {
1190         /* get pointers to arch-specific information */
1191         armv7m_common_t *armv7m = target->arch_info;
1192         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
1193         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
1194         int retval;
1195
1196         /* sanitize arguments */
1197         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1198                 return ERROR_INVALID_ARGUMENTS;
1199
1200         /* cortex_m3 handles unaligned memory access */
1201
1202         switch (size)
1203         {
1204                 case 4:
1205                         retval = ahbap_read_buf_u32(swjdp, buffer, 4 * count, address);
1206                         break;
1207                 case 2:
1208                         retval = ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
1209                         break;
1210                 case 1:
1211                         retval = ahbap_read_buf_u8(swjdp, buffer, count, address);
1212                         break;
1213                 default:
1214                         LOG_ERROR("BUG: we shouldn't get here");
1215                         exit(-1);
1216         }
1217
1218         return retval;
1219 }
1220
1221 int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1222 {
1223         /* get pointers to arch-specific information */
1224         armv7m_common_t *armv7m = target->arch_info;
1225         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
1226         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
1227         int retval;
1228
1229         /* sanitize arguments */
1230         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1231                 return ERROR_INVALID_ARGUMENTS;
1232
1233         switch (size)
1234         {
1235                 case 4:
1236                         retval = ahbap_write_buf_u32(swjdp, buffer, 4 * count, address);
1237                         break;
1238                 case 2:
1239                         retval = ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
1240                         break;
1241                 case 1:
1242                         retval = ahbap_write_buf_u8(swjdp, buffer, count, address);
1243                         break;
1244                 default:
1245                         LOG_ERROR("BUG: we shouldn't get here");
1246                         exit(-1);
1247         }
1248
1249         return retval;
1250 }
1251
1252 int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
1253 {
1254         return cortex_m3_write_memory(target, address, 4, count, buffer);
1255 }
1256
1257 void cortex_m3_build_reg_cache(target_t *target)
1258 {
1259         armv7m_build_reg_cache(target);
1260 }
1261
1262 int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1263 {
1264         cortex_m3_build_reg_cache(target);
1265         return ERROR_OK;
1266 }
1267
1268 int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target)
1269 {
1270         int retval;
1271         u32 cpuid, fpcr, dwtcr, ictr;
1272         int i;
1273
1274         /* get pointers to arch-specific information */
1275         armv7m_common_t *armv7m = target->arch_info;
1276         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
1277         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
1278
1279         target->type->examined = 1;
1280
1281         if ((retval=ahbap_debugport_init(swjdp))!=ERROR_OK)
1282                 return retval;
1283
1284         /* Read from Device Identification Registers */
1285         if ((retval=target_read_u32(target, CPUID, &cpuid))!=ERROR_OK)
1286                 return retval;
1287
1288         if (((cpuid >> 4) & 0xc3f) == 0xc23)
1289                 LOG_DEBUG("CORTEX-M3 processor detected");
1290         LOG_DEBUG("cpuid: 0x%8.8x", cpuid);
1291
1292         target_read_u32(target, NVIC_ICTR, &ictr);
1293         cortex_m3->intlinesnum = (ictr & 0x1F) + 1;
1294         cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4);
1295         for (i = 0; i < cortex_m3->intlinesnum; i++)
1296         {
1297                 target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i);
1298                 LOG_DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]);
1299         }
1300
1301         /* Setup FPB */
1302         target_read_u32(target, FP_CTRL, &fpcr);
1303         cortex_m3->auto_bp_type = 1;
1304         cortex_m3->fp_num_code = (fpcr >> 4) & 0xF;
1305         cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1306         cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1307         cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t));
1308         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1309         {
1310                 cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1311                 cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1312         }
1313         LOG_DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1314
1315         /* Setup DWT */
1316         target_read_u32(target, DWT_CTRL, &dwtcr);
1317         cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1318         cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp;
1319         cortex_m3->dwt_comparator_list=calloc(cortex_m3->dwt_num_comp, sizeof(cortex_m3_dwt_comparator_t));
1320         for (i = 0; i < cortex_m3->dwt_num_comp; i++)
1321         {
1322                 cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1323         }
1324
1325         return ERROR_OK;
1326 }
1327
1328
1329 int cortex_m3_quit()
1330 {
1331
1332         return ERROR_OK;
1333 }
1334
1335 int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
1336 {
1337         u16 dcrdr;
1338
1339         ahbap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
1340         *ctrl = (u8)dcrdr;
1341         *value = (u8)(dcrdr >> 8);
1342
1343         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1344
1345         /* write ack back to software dcc register
1346          * signify we have read data */
1347         if (dcrdr & (1 << 0))
1348         {
1349                 dcrdr = 0;
1350                 ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
1351         }
1352
1353         return ERROR_OK;
1354 }
1355
1356 int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer)
1357 {
1358         armv7m_common_t *armv7m = target->arch_info;
1359         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
1360         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
1361         u8 data;
1362         u8 ctrl;
1363         int i;
1364
1365         for (i = 0; i < (size * 4); i++)
1366         {
1367                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1368                 buffer[i] = data;
1369         }
1370
1371         return ERROR_OK;
1372 }
1373
1374 int cortex_m3_handle_target_request(void *priv)
1375 {
1376         target_t *target = priv;
1377         if (!target->type->examined)
1378                 return ERROR_OK;
1379         armv7m_common_t *armv7m = target->arch_info;
1380         cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
1381         swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
1382
1383         if (!target->dbg_msg_enabled)
1384                 return ERROR_OK;
1385
1386         if (target->state == TARGET_RUNNING)
1387         {
1388                 u8 data;
1389                 u8 ctrl;
1390
1391                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1392
1393                 /* check if we have data */
1394                 if (ctrl & (1 << 0))
1395                 {
1396                         u32 request;
1397
1398                         /* we assume target is quick enough */
1399                         request = data;
1400                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1401                         request |= (data << 8);
1402                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1403                         request |= (data << 16);
1404                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1405                         request |= (data << 24);
1406                         target_request(target, request);
1407                 }
1408         }
1409
1410         return ERROR_OK;
1411 }
1412
1413 int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, char *variant)
1414 {
1415         armv7m_common_t *armv7m;
1416         armv7m = &cortex_m3->armv7m;
1417
1418         /* prepare JTAG information for the new target */
1419         cortex_m3->jtag_info.chain_pos = chain_pos;
1420         cortex_m3->jtag_info.scann_size = 4;
1421
1422         cortex_m3->swjdp_info.dp_select_value = -1;
1423         cortex_m3->swjdp_info.ap_csw_value = -1;
1424         cortex_m3->swjdp_info.ap_tar_value = -1;
1425         cortex_m3->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1426
1427         /* initialize arch-specific breakpoint handling */
1428
1429         cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1430         cortex_m3->arch_info = NULL;
1431
1432         /* register arch-specific functions */
1433         armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1434
1435         armv7m->pre_debug_entry = NULL;
1436         armv7m->post_debug_entry = NULL;
1437
1438         armv7m->pre_restore_context = NULL;
1439         armv7m->post_restore_context = NULL;
1440
1441         armv7m_init_arch_info(target, armv7m);
1442         armv7m->arch_info = cortex_m3;
1443         armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1444         armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1445
1446         target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1447
1448         return ERROR_OK;
1449 }
1450
1451 /* target cortex_m3 <endianess> <startup_mode> <chain_pos> <variant>*/
1452 int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1453 {
1454         int chain_pos;
1455         char *variant = NULL;
1456         cortex_m3_common_t *cortex_m3 = malloc(sizeof(cortex_m3_common_t));
1457         memset(cortex_m3, 0, sizeof(*cortex_m3));
1458
1459         if (argc < 4)
1460         {
1461                 LOG_ERROR("'target cortex_m3' requires at least one additional argument");
1462                 exit(-1);
1463         }
1464
1465         chain_pos = strtoul(args[3], NULL, 0);
1466
1467         if (argc >= 5)
1468                 variant = args[4];
1469
1470         cortex_m3_init_arch_info(target, cortex_m3, chain_pos, variant);
1471         cortex_m3_register_commands(cmd_ctx);
1472
1473         return ERROR_OK;
1474 }
1475
1476 int cortex_m3_register_commands(struct command_context_s *cmd_ctx)
1477 {
1478         int retval;
1479
1480         retval = armv7m_register_commands(cmd_ctx);
1481
1482         return retval;
1483 }
1484