git.gag.com Git - fw/openocd/blob - src/target/cortex_m3.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "breakpoints.h"
  35 #include "cortex_m3.h"
  36 #include "target_request.h"
  37 #include "target_type.h"
  38 #include "arm_disassembler.h"
  39 #include "register.h"
  40 #include "arm_opcodes.h"
  41
  42
  43 /* NOTE:  most of this should work fine for the Cortex-M1 and
  44  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  45  */
  46
  47
  48 /* forward declarations */
  49 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
  50 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
  51 static void cortex_m3_enable_watchpoints(struct target *target);
  52 static int cortex_m3_store_core_reg_u32(struct target *target,
  53                 enum armv7m_regtype type, uint32_t num, uint32_t value);
  54
  55 #ifdef ARMV7_GDB_HACKS
  56 extern uint8_t armv7m_gdb_dummy_cpsr_value[];
  57 extern struct reg armv7m_gdb_dummy_cpsr_reg;
  58 #endif
  59
  60 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
  61                 uint32_t *value, int regnum)
  62 {
  63         int retval;
  64         uint32_t dcrdr;
  65
  66         /* because the DCB_DCRDR is used for the emulated dcc channel
  67          * we have to save/restore the DCB_DCRDR when used */
  68
  69         mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  70
  71         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  72
  73         /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  74         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  75         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  76
  77         /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  78         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  79         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  80
  81         retval = swjdp_transaction_endcheck(swjdp);
  82
  83         /* restore DCB_DCRDR - this needs to be in a seperate
  84          * transaction otherwise the emulated DCC channel breaks */
  85         if (retval == ERROR_OK)
  86                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  87
  88         return retval;
  89 }
  90
  91 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
  92                 uint32_t value, int regnum)
  93 {
  94         int retval;
  95         uint32_t dcrdr;
  96
  97         /* because the DCB_DCRDR is used for the emulated dcc channel
  98          * we have to save/restore the DCB_DCRDR when used */
  99
 100         mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 101
 102         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 103
 104         /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
 105         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 106         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 107
 108         /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
 109         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 110         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 111
 112         retval = swjdp_transaction_endcheck(swjdp);
 113
 114         /* restore DCB_DCRDR - this needs to be in a seperate
 115          * transaction otherwise the emulated DCC channel breaks */
 116         if (retval == ERROR_OK)
 117                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 118
 119         return retval;
 120 }
 121
 122 static int cortex_m3_write_debug_halt_mask(struct target *target,
 123                 uint32_t mask_on, uint32_t mask_off)
 124 {
 125         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 126         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 127
 128         /* mask off status bits */
 129         cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 130         /* create new register mask */
 131         cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 132
 133         return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
 134 }
 135
 136 static int cortex_m3_clear_halt(struct target *target)
 137 {
 138         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 139         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 140
 141         /* clear step if any */
 142         cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 143
 144         /* Read Debug Fault Status Register */
 145         mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 146         /* Clear Debug Fault Status */
 147         mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
 148         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 149
 150         return ERROR_OK;
 151 }
 152
 153 static int cortex_m3_single_step_core(struct target *target)
 154 {
 155         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 156         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 157         uint32_t dhcsr_save;
 158
 159         /* backup dhcsr reg */
 160         dhcsr_save = cortex_m3->dcb_dhcsr;
 161
 162         /* mask interrupts if not done already */
 163         if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
 164                 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 165         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 166         LOG_DEBUG(" ");
 167
 168         /* restore dhcsr reg */
 169         cortex_m3->dcb_dhcsr = dhcsr_save;
 170         cortex_m3_clear_halt(target);
 171
 172         return ERROR_OK;
 173 }
 174
 175 static int cortex_m3_endreset_event(struct target *target)
 176 {
 177         int i;
 178         uint32_t dcb_demcr;
 179         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 180         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 181         struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 182         struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 183
 184         mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 185         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 186
 187         /* this regsiter is used for emulated dcc channel */
 188         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 189
 190         /* Enable debug requests */
 191         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 192         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 193                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 194
 195         /* clear any interrupt masking */
 196         cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
 197
 198         /* Enable trace and dwt */
 199         mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
 200         /* Monitor bus faults */
 201         mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
 202
 203         /* Enable FPB */
 204         target_write_u32(target, FP_CTRL, 3);
 205         cortex_m3->fpb_enabled = 1;
 206
 207         /* Restore FPB registers */
 208         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
 209         {
 210                 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 211         }
 212
 213         /* Restore DWT registers */
 214         for (i = 0; i < cortex_m3->dwt_num_comp; i++)
 215         {
 216                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 217                                 dwt_list[i].comp);
 218                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 219                                 dwt_list[i].mask);
 220                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 221                                 dwt_list[i].function);
 222         }
 223         swjdp_transaction_endcheck(swjdp);
 224
 225         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 226
 227         /* make sure we have latest dhcsr flags */
 228         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 229
 230         return ERROR_OK;
 231 }
 232
 233 static int cortex_m3_examine_debug_reason(struct target *target)
 234 {
 235         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 236
 237         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
 238         /* only check the debug reason if we don't know it already */
 239
 240         if ((target->debug_reason != DBG_REASON_DBGRQ)
 241                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 242         {
 243                 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 244                 {
 245                         target->debug_reason = DBG_REASON_BREAKPOINT;
 246                         if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 247                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 248                 }
 249                 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 250                         target->debug_reason = DBG_REASON_WATCHPOINT;
 251                 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
 252                         target->debug_reason = DBG_REASON_BREAKPOINT;
 253                 else /* EXTERNAL, HALTED */
 254                         target->debug_reason = DBG_REASON_UNDEFINED;
 255         }
 256
 257         return ERROR_OK;
 258 }
 259
 260 static int cortex_m3_examine_exception_reason(struct target *target)
 261 {
 262         uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
 263         struct armv7m_common *armv7m = target_to_armv7m(target);
 264         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 265
 266         mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 267         switch (armv7m->exception_number)
 268         {
 269                 case 2: /* NMI */
 270                         break;
 271                 case 3: /* Hard Fault */
 272                         mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 273                         if (except_sr & 0x40000000)
 274                         {
 275                                 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
 276                         }
 277                         break;
 278                 case 4: /* Memory Management */
 279                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 280                         mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
 281                         break;
 282                 case 5: /* Bus Fault */
 283                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 284                         mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
 285                         break;
 286                 case 6: /* Usage Fault */
 287                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 288                         break;
 289                 case 11:        /* SVCall */
 290                         break;
 291                 case 12:        /* Debug Monitor */
 292                         mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
 293                         break;
 294                 case 14:        /* PendSV */
 295                         break;
 296                 case 15:        /* SysTick */
 297                         break;
 298                 default:
 299                         except_sr = 0;
 300                         break;
 301         }
 302         swjdp_transaction_endcheck(swjdp);
 303         LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
 304                 shcsr, except_sr, cfsr, except_ar);
 305         return ERROR_OK;
 306 }
 307
 308 static int cortex_m3_debug_entry(struct target *target)
 309 {
 310         int i;
 311         uint32_t xPSR;
 312         int retval;
 313         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 314         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 315         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 316
 317         LOG_DEBUG(" ");
 318
 319         cortex_m3_clear_halt(target);
 320         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 321
 322         if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
 323                 return retval;
 324
 325         /* Examine target state and mode */
 326         /* First load register acessible through core debug port*/
 327         int num_regs = armv7m->core_cache->num_regs;
 328
 329         for (i = 0; i < num_regs; i++)
 330         {
 331                 if (!armv7m->core_cache->reg_list[i].valid)
 332                         armv7m->read_core_reg(target, i);
 333         }
 334
 335         xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
 336
 337 #ifdef ARMV7_GDB_HACKS
 338         /* FIXME this breaks on scan chains with more than one Cortex-M3.
 339          * Instead, each CM3 should have its own dummy value...
 340          */
 341         /* copy real xpsr reg for gdb, setting thumb bit */
 342         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
 343         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
 344         armv7m_gdb_dummy_cpsr_reg.valid = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
 345         armv7m_gdb_dummy_cpsr_reg.dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty;
 346 #endif
 347
 348         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 349         if (xPSR & 0xf00)
 350         {
 351                 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
 352                 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 353         }
 354
 355         /* Are we in an exception handler */
 356         if (xPSR & 0x1FF)
 357         {
 358                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 359                 armv7m->exception_number = (xPSR & 0x1FF);
 360         }
 361         else
 362         {
 363                 armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
 364                 armv7m->exception_number = 0;
 365         }
 366
 367         if (armv7m->exception_number)
 368         {
 369                 cortex_m3_examine_exception_reason(target);
 370         }
 371
 372         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 373                 armv7m_mode_strings[armv7m->core_mode],
 374                 *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
 375                 target_state_name(target));
 376
 377         if (armv7m->post_debug_entry)
 378                 armv7m->post_debug_entry(target);
 379
 380         return ERROR_OK;
 381 }
 382
 383 static int cortex_m3_poll(struct target *target)
 384 {
 385         int retval;
 386         enum target_state prev_target_state = target->state;
 387         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 388         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 389
 390         /* Read from Debug Halting Control and Status Register */
 391         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 392         if (retval != ERROR_OK)
 393         {
 394                 target->state = TARGET_UNKNOWN;
 395                 return retval;
 396         }
 397
 398         if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 399         {
 400                 /* check if still in reset */
 401                 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 402
 403                 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 404                 {
 405                         target->state = TARGET_RESET;
 406                         return ERROR_OK;
 407                 }
 408         }
 409
 410         if (target->state == TARGET_RESET)
 411         {
 412                 /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
 413                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32 "", cortex_m3->dcb_dhcsr);
 414                 cortex_m3_endreset_event(target);
 415                 target->state = TARGET_RUNNING;
 416                 prev_target_state = TARGET_RUNNING;
 417         }
 418
 419         if (cortex_m3->dcb_dhcsr & S_HALT)
 420         {
 421                 target->state = TARGET_HALTED;
 422
 423                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 424                 {
 425                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 426                                 return retval;
 427
 428                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 429                 }
 430                 if (prev_target_state == TARGET_DEBUG_RUNNING)
 431                 {
 432                         LOG_DEBUG(" ");
 433                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 434                                 return retval;
 435
 436                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 437                 }
 438         }
 439
 440         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 441          * How best to model low power modes?
 442          */
 443
 444         if (target->state == TARGET_UNKNOWN)
 445         {
 446                 /* check if processor is retiring instructions */
 447                 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
 448                 {
 449                         target->state = TARGET_RUNNING;
 450                         return ERROR_OK;
 451                 }
 452         }
 453
 454         return ERROR_OK;
 455 }
 456
 457 static int cortex_m3_halt(struct target *target)
 458 {
 459         LOG_DEBUG("target->state: %s",
 460                 target_state_name(target));
 461
 462         if (target->state == TARGET_HALTED)
 463         {
 464                 LOG_DEBUG("target was already halted");
 465                 return ERROR_OK;
 466         }
 467
 468         if (target->state == TARGET_UNKNOWN)
 469         {
 470                 LOG_WARNING("target was in unknown state when halt was requested");
 471         }
 472
 473         if (target->state == TARGET_RESET)
 474         {
 475                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
 476                 {
 477                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 478                         return ERROR_TARGET_FAILURE;
 479                 }
 480                 else
 481                 {
 482                         /* we came here in a reset_halt or reset_init sequence
 483                          * debug entry was already prepared in cortex_m3_prepare_reset_halt()
 484                          */
 485                         target->debug_reason = DBG_REASON_DBGRQ;
 486
 487                         return ERROR_OK;
 488                 }
 489         }
 490
 491         /* Write to Debug Halting Control and Status Register */
 492         cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 493
 494         target->debug_reason = DBG_REASON_DBGRQ;
 495
 496         return ERROR_OK;
 497 }
 498
 499 static int cortex_m3_soft_reset_halt(struct target *target)
 500 {
 501         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 502         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 503         uint32_t dcb_dhcsr = 0;
 504         int retval, timeout = 0;
 505
 506         /* Enter debug state on reset, cf. end_reset_event() */
 507         mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 508
 509         /* Request a reset */
 510         mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
 511         target->state = TARGET_RESET;
 512
 513         /* registers are now invalid */
 514         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 515
 516         while (timeout < 100)
 517         {
 518                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 519                 if (retval == ERROR_OK)
 520                 {
 521                         mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 522                         if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 523                         {
 524                                 LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32 ", nvic_dfsr 0x%" PRIx32 "", dcb_dhcsr, cortex_m3->nvic_dfsr);
 525                                 cortex_m3_poll(target);
 526                                 return ERROR_OK;
 527                         }
 528                         else
 529                                 LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32 ", %i ms", dcb_dhcsr, timeout);
 530                 }
 531                 timeout++;
 532                 alive_sleep(1);
 533         }
 534
 535         return ERROR_OK;
 536 }
 537
 538 static void cortex_m3_enable_breakpoints(struct target *target)
 539 {
 540         struct breakpoint *breakpoint = target->breakpoints;
 541
 542         /* set any pending breakpoints */
 543         while (breakpoint)
 544         {
 545                 if (breakpoint->set == 0)
 546                         cortex_m3_set_breakpoint(target, breakpoint);
 547                 breakpoint = breakpoint->next;
 548         }
 549 }
 550
 551 static int cortex_m3_resume(struct target *target, int current,
 552                 uint32_t address, int handle_breakpoints, int debug_execution)
 553 {
 554         struct armv7m_common *armv7m = target_to_armv7m(target);
 555         struct breakpoint *breakpoint = NULL;
 556         uint32_t resume_pc;
 557
 558         if (target->state != TARGET_HALTED)
 559         {
 560                 LOG_WARNING("target not halted");
 561                 return ERROR_TARGET_NOT_HALTED;
 562         }
 563
 564         if (!debug_execution)
 565         {
 566                 target_free_all_working_areas(target);
 567                 cortex_m3_enable_breakpoints(target);
 568                 cortex_m3_enable_watchpoints(target);
 569         }
 570
 571         if (debug_execution)
 572         {
 573                 /* Disable interrupts */
 574                 /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
 575                  * This is probably the same issue as Cortex-M3 Errata  377493:
 576                  * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
 577                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
 578                 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
 579                 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
 580
 581                 /* Make sure we are in Thumb mode */
 582                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
 583                         buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
 584                 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
 585                 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
 586         }
 587
 588         /* current = 1: continue on current pc, otherwise continue at <address> */
 589         if (!current)
 590         {
 591                 buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
 592                 armv7m->core_cache->reg_list[15].dirty = 1;
 593                 armv7m->core_cache->reg_list[15].valid = 1;
 594         }
 595
 596         resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32);
 597
 598         armv7m_restore_context(target);
 599
 600         /* the front-end may request us not to handle breakpoints */
 601         if (handle_breakpoints)
 602         {
 603                 /* Single step past breakpoint at current address */
 604                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 605                 {
 606                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 607                                           breakpoint->address,
 608                                           breakpoint->unique_id);
 609                         cortex_m3_unset_breakpoint(target, breakpoint);
 610                         cortex_m3_single_step_core(target);
 611                         cortex_m3_set_breakpoint(target, breakpoint);
 612                 }
 613         }
 614
 615         /* Restart core */
 616         cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 617
 618         target->debug_reason = DBG_REASON_NOTHALTED;
 619
 620         /* registers are now invalid */
 621         register_cache_invalidate(armv7m->core_cache);
 622
 623         if (!debug_execution)
 624         {
 625                 target->state = TARGET_RUNNING;
 626                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 627                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 628         }
 629         else
 630         {
 631                 target->state = TARGET_DEBUG_RUNNING;
 632                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 633                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 634         }
 635
 636         return ERROR_OK;
 637 }
 638
 639 /* int irqstepcount = 0; */
 640 static int cortex_m3_step(struct target *target, int current,
 641                 uint32_t address, int handle_breakpoints)
 642 {
 643         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 644         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 645         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 646         struct breakpoint *breakpoint = NULL;
 647
 648         if (target->state != TARGET_HALTED)
 649         {
 650                 LOG_WARNING("target not halted");
 651                 return ERROR_TARGET_NOT_HALTED;
 652         }
 653
 654         /* current = 1: continue on current pc, otherwise continue at <address> */
 655         if (!current)
 656                 buf_set_u32(cortex_m3->armv7m.core_cache->reg_list[15].value,
 657                                 0, 32, address);
 658
 659         /* the front-end may request us not to handle breakpoints */
 660         if (handle_breakpoints) {
 661                 breakpoint = breakpoint_find(target, buf_get_u32(armv7m
 662                                 ->core_cache->reg_list[15].value, 0, 32));
 663                 if (breakpoint)
 664                         cortex_m3_unset_breakpoint(target, breakpoint);
 665         }
 666
 667         target->debug_reason = DBG_REASON_SINGLESTEP;
 668
 669         armv7m_restore_context(target);
 670
 671         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 672
 673         /* set step and clear halt */
 674         cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 675         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 676
 677         /* registers are now invalid */
 678         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 679
 680         if (breakpoint)
 681                 cortex_m3_set_breakpoint(target, breakpoint);
 682
 683         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 684
 685         cortex_m3_debug_entry(target);
 686         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 687
 688         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 689         return ERROR_OK;
 690 }
 691
 692 static int cortex_m3_assert_reset(struct target *target)
 693 {
 694         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 695         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 696         int assert_srst = 1;
 697
 698         LOG_DEBUG("target->state: %s",
 699                 target_state_name(target));
 700
 701         enum reset_types jtag_reset_config = jtag_get_reset_config();
 702
 703         /*
 704          * We can reset Cortex-M3 targets using just the NVIC without
 705          * requiring SRST, getting a SoC reset (or a core-only reset)
 706          * instead of a system reset.
 707          */
 708         if (!(jtag_reset_config & RESET_HAS_SRST))
 709                 assert_srst = 0;
 710
 711         /* Enable debug requests */
 712         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 713         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 714                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 715
 716         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 717
 718         if (!target->reset_halt)
 719         {
 720                 /* Set/Clear C_MASKINTS in a separate operation */
 721                 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
 722                         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
 723
 724                 /* clear any debug flags before resuming */
 725                 cortex_m3_clear_halt(target);
 726
 727                 /* clear C_HALT in dhcsr reg */
 728                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 729
 730                 /* Enter debug state on reset, cf. end_reset_event() */
 731                 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
 732         }
 733         else
 734         {
 735                 /* Enter debug state on reset, cf. end_reset_event() */
 736                 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 737         }
 738
 739         /*
 740          * When nRST is asserted on most Stellaris devices, it clears some of
 741          * the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
 742          * and OpenOCD depends on those TRMs.  So we won't use SRST on those
 743          * chips.  (Only power-on reset should affect debug state, beyond a
 744          * few specified bits; not the chip's nRST input, wired to SRST.)
 745          *
 746          * REVISIT current errata specs don't seem to cover this issue.
 747          * Do we have more details than this email?
 748          *   https://lists.berlios.de/pipermail
 749          *      /openocd-development/2008-August/003065.html
 750          */
 751         if (strcmp(target->variant, "lm3s") == 0)
 752         {
 753                 /* Check for silicon revisions with the issue. */
 754                 uint32_t did0;
 755
 756                 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
 757                 {
 758                         switch ((did0 >> 16) & 0xff)
 759                         {
 760                                 case 0:
 761                                         /* all Sandstorm suffer issue */
 762                                         assert_srst = 0;
 763                                         break;
 764
 765                                 case 1:
 766                                 case 3:
 767                                         /* Fury and DustDevil rev A have
 768                                          * this nRST problem.  It should
 769                                          * be fixed in rev B silicon.
 770                                          */
 771                                         if (((did0 >> 8) & 0xff) == 0)
 772                                                 assert_srst = 0;
 773                                         break;
 774                                 case 4:
 775                                         /* Tempest should be fine. */
 776                                         break;
 777                         }
 778                 }
 779         }
 780
 781         if (assert_srst)
 782         {
 783                 /* default to asserting srst */
 784                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 785                 {
 786                         jtag_add_reset(1, 1);
 787                 }
 788                 else
 789                 {
 790                         jtag_add_reset(0, 1);
 791                 }
 792         }
 793         else
 794         {
 795                 /* Use a standard Cortex-M3 software reset mechanism.
 796                  * SYSRESETREQ will reset SoC peripherals outside the
 797                  * core, like watchdog timers, if the SoC wires it up
 798                  * correctly.  Else VECRESET can reset just the core.
 799                  */
 800                 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 801                                 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
 802                 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
 803
 804                 {
 805                         /* I do not know why this is necessary, but it
 806                          * fixes strange effects (step/resume cause NMI
 807                          * after reset) on LM3S6918 -- Michael Schwingen
 808                          */
 809                         uint32_t tmp;
 810                         mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
 811                 }
 812         }
 813
 814         target->state = TARGET_RESET;
 815         jtag_add_sleep(50000);
 816
 817         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 818
 819         if (target->reset_halt)
 820         {
 821                 int retval;
 822                 if ((retval = target_halt(target)) != ERROR_OK)
 823                         return retval;
 824         }
 825
 826         return ERROR_OK;
 827 }
 828
 829 static int cortex_m3_deassert_reset(struct target *target)
 830 {
 831         LOG_DEBUG("target->state: %s",
 832                 target_state_name(target));
 833
 834         /* deassert reset lines */
 835         jtag_add_reset(0, 0);
 836
 837         return ERROR_OK;
 838 }
 839
 840 static int
 841 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
 842 {
 843         int retval;
 844         int fp_num = 0;
 845         uint32_t hilo;
 846         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 847         struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
 848
 849         if (breakpoint->set)
 850         {
 851                 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
 852                 return ERROR_OK;
 853         }
 854
 855         if (cortex_m3->auto_bp_type)
 856         {
 857                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
 858         }
 859
 860         if (breakpoint->type == BKPT_HARD)
 861         {
 862                 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
 863                         fp_num++;
 864                 if (fp_num >= cortex_m3->fp_num_code)
 865                 {
 866                         LOG_ERROR("Can not find free FPB Comparator!");
 867                         return ERROR_FAIL;
 868                 }
 869                 breakpoint->set = fp_num + 1;
 870                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
 871                 comparator_list[fp_num].used = 1;
 872                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
 873                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
 874                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
 875                 if (!cortex_m3->fpb_enabled)
 876                 {
 877                         LOG_DEBUG("FPB wasn't enabled, do it now");
 878                         target_write_u32(target, FP_CTRL, 3);
 879                 }
 880         }
 881         else if (breakpoint->type == BKPT_SOFT)
 882         {
 883                 uint8_t code[4];
 884                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
 885                 if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
 886                 {
 887                         return retval;
 888                 }
 889                 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
 890                 {
 891                         return retval;
 892                 }
 893                 breakpoint->set = 0x11; /* Any nice value but 0 */
 894         }
 895
 896         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
 897                           breakpoint->unique_id,
 898                           (int)(breakpoint->type),
 899                           breakpoint->address,
 900                           breakpoint->length,
 901                           breakpoint->set);
 902
 903         return ERROR_OK;
 904 }
 905
 906 static int
 907 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
 908 {
 909         int retval;
 910         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 911         struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
 912
 913         if (!breakpoint->set)
 914         {
 915                 LOG_WARNING("breakpoint not set");
 916                 return ERROR_OK;
 917         }
 918
 919         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
 920                           breakpoint->unique_id,
 921                           (int)(breakpoint->type),
 922                           breakpoint->address,
 923                           breakpoint->length,
 924                           breakpoint->set);
 925
 926         if (breakpoint->type == BKPT_HARD)
 927         {
 928                 int fp_num = breakpoint->set - 1;
 929                 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
 930                 {
 931                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
 932                         return ERROR_OK;
 933                 }
 934                 comparator_list[fp_num].used = 0;
 935                 comparator_list[fp_num].fpcr_value = 0;
 936                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
 937         }
 938         else
 939         {
 940                 /* restore original instruction (kept in target endianness) */
 941                 if (breakpoint->length == 4)
 942                 {
 943                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 944                         {
 945                                 return retval;
 946                         }
 947                 }
 948                 else
 949                 {
 950                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 951                         {
 952                                 return retval;
 953                         }
 954                 }
 955         }
 956         breakpoint->set = 0;
 957
 958         return ERROR_OK;
 959 }
 960
 961 static int
 962 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 963 {
 964         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 965
 966         if (cortex_m3->auto_bp_type)
 967         {
 968                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
 969 #ifdef ARMV7_GDB_HACKS
 970                 if (breakpoint->length != 2) {
 971                         /* XXX Hack: Replace all breakpoints with length != 2 with
 972                          * a hardware breakpoint. */
 973                         breakpoint->type = BKPT_HARD;
 974                         breakpoint->length = 2;
 975                 }
 976 #endif
 977         }
 978
 979         if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
 980         {
 981                 LOG_INFO("flash patch comparator requested outside code memory region");
 982                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 983         }
 984
 985         if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
 986         {
 987                 LOG_INFO("soft breakpoint requested in code (flash) memory region");
 988                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 989         }
 990
 991         if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
 992         {
 993                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
 994                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 995         }
 996
 997         if ((breakpoint->length != 2))
 998         {
 999                 LOG_INFO("only breakpoints of two bytes length supported");
1000                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1001         }
1002
1003         if (breakpoint->type == BKPT_HARD)
1004                 cortex_m3->fp_code_available--;
1005         cortex_m3_set_breakpoint(target, breakpoint);
1006
1007         return ERROR_OK;
1008 }
1009
1010 static int
1011 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1012 {
1013         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1014
1015         /* REVISIT why check? FBP can be updated with core running ... */
1016         if (target->state != TARGET_HALTED)
1017         {
1018                 LOG_WARNING("target not halted");
1019                 return ERROR_TARGET_NOT_HALTED;
1020         }
1021
1022         if (cortex_m3->auto_bp_type)
1023         {
1024                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1025         }
1026
1027         if (breakpoint->set)
1028         {
1029                 cortex_m3_unset_breakpoint(target, breakpoint);
1030         }
1031
1032         if (breakpoint->type == BKPT_HARD)
1033                 cortex_m3->fp_code_available++;
1034
1035         return ERROR_OK;
1036 }
1037
1038 static int
1039 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1040 {
1041         int dwt_num = 0;
1042         uint32_t mask, temp;
1043         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1044
1045         /* watchpoint params were validated earlier */
1046         mask = 0;
1047         temp = watchpoint->length;
1048         while (temp) {
1049                 temp >>= 1;
1050                 mask++;
1051         }
1052         mask--;
1053
1054         /* REVISIT Don't fully trust these "not used" records ... users
1055          * may set up breakpoints by hand, e.g. dual-address data value
1056          * watchpoint using comparator #1; comparator #0 matching cycle
1057          * count; send data trace info through ITM and TPIU; etc
1058          */
1059         struct cortex_m3_dwt_comparator *comparator;
1060
1061         for (comparator = cortex_m3->dwt_comparator_list;
1062                         comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1063                         comparator++, dwt_num++)
1064                 continue;
1065         if (dwt_num >= cortex_m3->dwt_num_comp)
1066         {
1067                 LOG_ERROR("Can not find free DWT Comparator");
1068                 return ERROR_FAIL;
1069         }
1070         comparator->used = 1;
1071         watchpoint->set = dwt_num + 1;
1072
1073         comparator->comp = watchpoint->address;
1074         target_write_u32(target, comparator->dwt_comparator_address + 0,
1075                         comparator->comp);
1076
1077         comparator->mask = mask;
1078         target_write_u32(target, comparator->dwt_comparator_address + 4,
1079                         comparator->mask);
1080
1081         switch (watchpoint->rw) {
1082         case WPT_READ:
1083                 comparator->function = 5;
1084                 break;
1085         case WPT_WRITE:
1086                 comparator->function = 6;
1087                 break;
1088         case WPT_ACCESS:
1089                 comparator->function = 7;
1090                 break;
1091         }
1092         target_write_u32(target, comparator->dwt_comparator_address + 8,
1093                         comparator->function);
1094
1095         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1096                         watchpoint->unique_id, dwt_num,
1097                         (unsigned) comparator->comp,
1098                         (unsigned) comparator->mask,
1099                         (unsigned) comparator->function);
1100         return ERROR_OK;
1101 }
1102
1103 static int
1104 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1105 {
1106         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1107         struct cortex_m3_dwt_comparator *comparator;
1108         int dwt_num;
1109
1110         if (!watchpoint->set)
1111         {
1112                 LOG_WARNING("watchpoint (wpid: %d) not set",
1113                                 watchpoint->unique_id);
1114                 return ERROR_OK;
1115         }
1116
1117         dwt_num = watchpoint->set - 1;
1118
1119         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1120                         watchpoint->unique_id, dwt_num,
1121                         (unsigned) watchpoint->address);
1122
1123         if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1124         {
1125                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1126                 return ERROR_OK;
1127         }
1128
1129         comparator = cortex_m3->dwt_comparator_list + dwt_num;
1130         comparator->used = 0;
1131         comparator->function = 0;
1132         target_write_u32(target, comparator->dwt_comparator_address + 8,
1133                         comparator->function);
1134
1135         watchpoint->set = 0;
1136
1137         return ERROR_OK;
1138 }
1139
1140 static int
1141 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1142 {
1143         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1144
1145         if (cortex_m3->dwt_comp_available < 1)
1146         {
1147                 LOG_DEBUG("no comparators?");
1148                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1149         }
1150
1151         /* hardware doesn't support data value masking */
1152         if (watchpoint->mask != ~(uint32_t)0) {
1153                 LOG_DEBUG("watchpoint value masks not supported");
1154                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1155         }
1156
1157         /* hardware allows address masks of up to 32K */
1158         unsigned mask;
1159
1160         for (mask = 0; mask < 16; mask++) {
1161                 if ((1u << mask) == watchpoint->length)
1162                         break;
1163         }
1164         if (mask == 16) {
1165                 LOG_DEBUG("unsupported watchpoint length");
1166                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1167         }
1168         if (watchpoint->address & ((1 << mask) - 1)) {
1169                 LOG_DEBUG("watchpoint address is unaligned");
1170                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1171         }
1172
1173         /* Caller doesn't seem to be able to describe watching for data
1174          * values of zero; that flags "no value".
1175          *
1176          * REVISIT This DWT may well be able to watch for specific data
1177          * values.  Requires comparator #1 to set DATAVMATCH and match
1178          * the data, and another comparator (DATAVADDR0) matching addr.
1179          */
1180         if (watchpoint->value) {
1181                 LOG_DEBUG("data value watchpoint not YET supported");
1182                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1183         }
1184
1185         cortex_m3->dwt_comp_available--;
1186         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1187
1188         return ERROR_OK;
1189 }
1190
1191 static int
1192 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1193 {
1194         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1195
1196         /* REVISIT why check? DWT can be updated with core running ... */
1197         if (target->state != TARGET_HALTED)
1198         {
1199                 LOG_WARNING("target not halted");
1200                 return ERROR_TARGET_NOT_HALTED;
1201         }
1202
1203         if (watchpoint->set)
1204         {
1205                 cortex_m3_unset_watchpoint(target, watchpoint);
1206         }
1207
1208         cortex_m3->dwt_comp_available++;
1209         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1210
1211         return ERROR_OK;
1212 }
1213
1214 static void cortex_m3_enable_watchpoints(struct target *target)
1215 {
1216         struct watchpoint *watchpoint = target->watchpoints;
1217
1218         /* set any pending watchpoints */
1219         while (watchpoint)
1220         {
1221                 if (watchpoint->set == 0)
1222                         cortex_m3_set_watchpoint(target, watchpoint);
1223                 watchpoint = watchpoint->next;
1224         }
1225 }
1226
1227 static int cortex_m3_load_core_reg_u32(struct target *target,
1228                 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1229 {
1230         int retval;
1231         struct armv7m_common *armv7m = target_to_armv7m(target);
1232         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1233
1234         /* NOTE:  we "know" here that the register identifiers used
1235          * in the v7m header match the Cortex-M3 Debug Core Register
1236          * Selector values for R0..R15, xPSR, MSP, and PSP.
1237          */
1238         switch (num) {
1239         case 0 ... 18:
1240                 /* read a normal core register */
1241                 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1242
1243                 if (retval != ERROR_OK)
1244                 {
1245                         LOG_ERROR("JTAG failure %i",retval);
1246                         return ERROR_JTAG_DEVICE_ERROR;
1247                 }
1248                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",(int)num,*value);
1249                 break;
1250
1251         case ARMV7M_PRIMASK:
1252         case ARMV7M_BASEPRI:
1253         case ARMV7M_FAULTMASK:
1254         case ARMV7M_CONTROL:
1255                 /* Cortex-M3 packages these four registers as bitfields
1256                  * in one Debug Core register.  So say r0 and r2 docs;
1257                  * it was removed from r1 docs, but still works.
1258                  */
1259                 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1260
1261                 switch (num)
1262                 {
1263                         case ARMV7M_PRIMASK:
1264                                 *value = buf_get_u32((uint8_t*)value, 0, 1);
1265                                 break;
1266
1267                         case ARMV7M_BASEPRI:
1268                                 *value = buf_get_u32((uint8_t*)value, 8, 8);
1269                                 break;
1270
1271                         case ARMV7M_FAULTMASK:
1272                                 *value = buf_get_u32((uint8_t*)value, 16, 1);
1273                                 break;
1274
1275                         case ARMV7M_CONTROL:
1276                                 *value = buf_get_u32((uint8_t*)value, 24, 2);
1277                                 break;
1278                 }
1279
1280                 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1281                 break;
1282
1283         default:
1284                 return ERROR_INVALID_ARGUMENTS;
1285         }
1286
1287         return ERROR_OK;
1288 }
1289
1290 static int cortex_m3_store_core_reg_u32(struct target *target,
1291                 enum armv7m_regtype type, uint32_t num, uint32_t value)
1292 {
1293         int retval;
1294         uint32_t reg;
1295         struct armv7m_common *armv7m = target_to_armv7m(target);
1296         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1297
1298 #ifdef ARMV7_GDB_HACKS
1299         /* If the LR register is being modified, make sure it will put us
1300          * in "thumb" mode, or an INVSTATE exception will occur. This is a
1301          * hack to deal with the fact that gdb will sometimes "forge"
1302          * return addresses, and doesn't set the LSB correctly (i.e., when
1303          * printing expressions containing function calls, it sets LR = 0.)
1304          * Valid exception return codes have bit 0 set too.
1305          */
1306         if (num == ARMV7M_R14)
1307                 value |= 0x01;
1308 #endif
1309
1310         /* NOTE:  we "know" here that the register identifiers used
1311          * in the v7m header match the Cortex-M3 Debug Core Register
1312          * Selector values for R0..R15, xPSR, MSP, and PSP.
1313          */
1314         switch (num) {
1315         case 0 ... 18:
1316                 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1317                 if (retval != ERROR_OK)
1318                 {
1319                         LOG_ERROR("JTAG failure %i", retval);
1320                         armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
1321                         return ERROR_JTAG_DEVICE_ERROR;
1322                 }
1323                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1324                 break;
1325
1326         case ARMV7M_PRIMASK:
1327         case ARMV7M_BASEPRI:
1328         case ARMV7M_FAULTMASK:
1329         case ARMV7M_CONTROL:
1330                 /* Cortex-M3 packages these four registers as bitfields
1331                  * in one Debug Core register.  So say r0 and r2 docs;
1332                  * it was removed from r1 docs, but still works.
1333                  */
1334                 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1335
1336                 switch (num)
1337                 {
1338                         case ARMV7M_PRIMASK:
1339                                 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1340                                 break;
1341
1342                         case ARMV7M_BASEPRI:
1343                                 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1344                                 break;
1345
1346                         case ARMV7M_FAULTMASK:
1347                                 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1348                                 break;
1349
1350                         case ARMV7M_CONTROL:
1351                                 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1352                                 break;
1353                 }
1354
1355                 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1356
1357                 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1358                 break;
1359
1360         default:
1361                 return ERROR_INVALID_ARGUMENTS;
1362         }
1363
1364         return ERROR_OK;
1365 }
1366
1367 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1368                 uint32_t size, uint32_t count, uint8_t *buffer)
1369 {
1370         struct armv7m_common *armv7m = target_to_armv7m(target);
1371         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1372         int retval = ERROR_INVALID_ARGUMENTS;
1373
1374         /* cortex_m3 handles unaligned memory access */
1375         if (count && buffer) {
1376                 switch (size) {
1377                 case 4:
1378                         retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1379                         break;
1380                 case 2:
1381                         retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1382                         break;
1383                 case 1:
1384                         retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1385                         break;
1386                 }
1387         }
1388
1389         return retval;
1390 }
1391
1392 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1393                 uint32_t size, uint32_t count, uint8_t *buffer)
1394 {
1395         struct armv7m_common *armv7m = target_to_armv7m(target);
1396         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1397         int retval = ERROR_INVALID_ARGUMENTS;
1398
1399         if (count && buffer) {
1400                 switch (size) {
1401                 case 4:
1402                         retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1403                         break;
1404                 case 2:
1405                         retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1406                         break;
1407                 case 1:
1408                         retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1409                         break;
1410                 }
1411         }
1412
1413         return retval;
1414 }
1415
1416 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1417                 uint32_t count, uint8_t *buffer)
1418 {
1419         return cortex_m3_write_memory(target, address, 4, count, buffer);
1420 }
1421
1422 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1423                 struct target *target)
1424 {
1425         armv7m_build_reg_cache(target);
1426         return ERROR_OK;
1427 }
1428
1429 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1430  * on r/w if the core is not running, and clear on resume or reset ... or
1431  * at least, in a post_restore_context() method.
1432  */
1433
1434 struct dwt_reg_state {
1435         struct target   *target;
1436         uint32_t        addr;
1437         uint32_t        value;  /* scratch/cache */
1438 };
1439
1440 static int cortex_m3_dwt_get_reg(struct reg *reg)
1441 {
1442         struct dwt_reg_state *state = reg->arch_info;
1443
1444         return target_read_u32(state->target, state->addr, &state->value);
1445 }
1446
1447 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1448 {
1449         struct dwt_reg_state *state = reg->arch_info;
1450
1451         return target_write_u32(state->target, state->addr,
1452                         buf_get_u32(buf, 0, reg->size));
1453 }
1454
1455 struct dwt_reg {
1456         uint32_t        addr;
1457         char            *name;
1458         unsigned        size;
1459 };
1460
1461 static struct dwt_reg dwt_base_regs[] = {
1462         { DWT_CTRL, "dwt_ctrl", 32, },
1463         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1464         /* plus some 8 bit counters, useful for profiling with TPIU */
1465 };
1466
1467 static struct dwt_reg dwt_comp[] = {
1468 #define DWT_COMPARATOR(i) \
1469                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1470                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1471                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1472         DWT_COMPARATOR(0),
1473         DWT_COMPARATOR(1),
1474         DWT_COMPARATOR(2),
1475         DWT_COMPARATOR(3),
1476 #undef DWT_COMPARATOR
1477 };
1478
1479 static const struct reg_arch_type dwt_reg_type = {
1480         .get = cortex_m3_dwt_get_reg,
1481         .set = cortex_m3_dwt_set_reg,
1482 };
1483
1484 static void
1485 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1486 {
1487         struct dwt_reg_state *state;
1488
1489         state = calloc(1, sizeof *state);
1490         if (!state)
1491                 return;
1492         state->addr = d->addr;
1493         state->target = t;
1494
1495         r->name = d->name;
1496         r->size = d->size;
1497         r->value = &state->value;
1498         r->arch_info = state;
1499         r->type = &dwt_reg_type;
1500 }
1501
1502 static void
1503 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1504 {
1505         uint32_t dwtcr;
1506         struct reg_cache *cache;
1507         struct cortex_m3_dwt_comparator *comparator;
1508         int reg, i;
1509
1510         target_read_u32(target, DWT_CTRL, &dwtcr);
1511         if (!dwtcr) {
1512                 LOG_DEBUG("no DWT");
1513                 return;
1514         }
1515
1516         cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1517         cm3->dwt_comp_available = cm3->dwt_num_comp;
1518         cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1519                         sizeof(struct cortex_m3_dwt_comparator));
1520         if (!cm3->dwt_comparator_list) {
1521 fail0:
1522                 cm3->dwt_num_comp = 0;
1523                 LOG_ERROR("out of mem");
1524                 return;
1525         }
1526
1527         cache = calloc(1, sizeof *cache);
1528         if (!cache) {
1529 fail1:
1530                 free(cm3->dwt_comparator_list);
1531                 goto fail0;
1532         }
1533         cache->name = "cortex-m3 dwt registers";
1534         cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1535         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1536         if (!cache->reg_list) {
1537                 free(cache);
1538                 goto fail1;
1539         }
1540
1541         for (reg = 0; reg < 2; reg++)
1542                 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1543                                 dwt_base_regs + reg);
1544
1545         comparator = cm3->dwt_comparator_list;
1546         for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1547                 int j;
1548
1549                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1550                 for (j = 0; j < 3; j++, reg++)
1551                         cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1552                                         dwt_comp + 3 * i + j);
1553         }
1554
1555         *register_get_last_cache_p(&target->reg_cache) = cache;
1556         cm3->dwt_cache = cache;
1557
1558         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1559                         dwtcr, cm3->dwt_num_comp,
1560                         (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1561
1562         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1563          * implement single-address data value watchpoints ... so we
1564          * won't need to check it later, when asked to set one up.
1565          */
1566 }
1567
1568 static int cortex_m3_examine(struct target *target)
1569 {
1570         int retval;
1571         uint32_t cpuid, fpcr;
1572         int i;
1573         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1574         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
1575
1576         if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1577                 return retval;
1578
1579         if (!target_was_examined(target))
1580         {
1581                 target_set_examined(target);
1582
1583                 /* Read from Device Identification Registers */
1584                 retval = target_read_u32(target, CPUID, &cpuid);
1585                 if (retval != ERROR_OK)
1586                         return retval;
1587
1588                 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1589                         LOG_DEBUG("CORTEX-M3 processor detected");
1590                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1591
1592                 /* NOTE: FPB and DWT are both optional. */
1593
1594                 /* Setup FPB */
1595                 target_read_u32(target, FP_CTRL, &fpcr);
1596                 cortex_m3->auto_bp_type = 1;
1597                 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1598                 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1599                 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1600                 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1601                 cortex_m3->fpb_enabled = fpcr & 1;
1602                 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1603                 {
1604                         cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1605                         cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1606                 }
1607                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1608
1609                 /* Setup DWT */
1610                 cortex_m3_dwt_setup(cortex_m3, target);
1611
1612                 /* These hardware breakpoints only work for code in flash! */
1613                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1614                                 target_name(target),
1615                                 cortex_m3->fp_num_code,
1616                                 cortex_m3->dwt_num_comp);
1617         }
1618
1619         return ERROR_OK;
1620 }
1621
1622 static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1623 {
1624         uint16_t dcrdr;
1625
1626         mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1627         *ctrl = (uint8_t)dcrdr;
1628         *value = (uint8_t)(dcrdr >> 8);
1629
1630         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1631
1632         /* write ack back to software dcc register
1633          * signify we have read data */
1634         if (dcrdr & (1 << 0))
1635         {
1636                 dcrdr = 0;
1637                 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1638         }
1639
1640         return ERROR_OK;
1641 }
1642
1643 static int cortex_m3_target_request_data(struct target *target,
1644                 uint32_t size, uint8_t *buffer)
1645 {
1646         struct armv7m_common *armv7m = target_to_armv7m(target);
1647         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1648         uint8_t data;
1649         uint8_t ctrl;
1650         uint32_t i;
1651
1652         for (i = 0; i < (size * 4); i++)
1653         {
1654                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1655                 buffer[i] = data;
1656         }
1657
1658         return ERROR_OK;
1659 }
1660
1661 static int cortex_m3_handle_target_request(void *priv)
1662 {
1663         struct target *target = priv;
1664         if (!target_was_examined(target))
1665                 return ERROR_OK;
1666         struct armv7m_common *armv7m = target_to_armv7m(target);
1667         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1668
1669         if (!target->dbg_msg_enabled)
1670                 return ERROR_OK;
1671
1672         if (target->state == TARGET_RUNNING)
1673         {
1674                 uint8_t data;
1675                 uint8_t ctrl;
1676
1677                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1678
1679                 /* check if we have data */
1680                 if (ctrl & (1 << 0))
1681                 {
1682                         uint32_t request;
1683
1684                         /* we assume target is quick enough */
1685                         request = data;
1686                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1687                         request |= (data << 8);
1688                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1689                         request |= (data << 16);
1690                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1691                         request |= (data << 24);
1692                         target_request(target, request);
1693                 }
1694         }
1695
1696         return ERROR_OK;
1697 }
1698
1699 static int cortex_m3_init_arch_info(struct target *target,
1700                 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1701 {
1702         int retval;
1703         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1704
1705         armv7m_init_arch_info(target, armv7m);
1706
1707         /* prepare JTAG information for the new target */
1708         cortex_m3->jtag_info.tap = tap;
1709         cortex_m3->jtag_info.scann_size = 4;
1710
1711         armv7m->swjdp_info.dp_select_value = -1;
1712         armv7m->swjdp_info.ap_csw_value = -1;
1713         armv7m->swjdp_info.ap_tar_value = -1;
1714         armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1715         armv7m->swjdp_info.memaccess_tck = 8;
1716         armv7m->swjdp_info.tar_autoincr_block = (1 << 12);      /* Cortex-M3 has 4096 bytes autoincrement range */
1717
1718         /* register arch-specific functions */
1719         armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1720
1721         armv7m->post_debug_entry = NULL;
1722
1723         armv7m->pre_restore_context = NULL;
1724         armv7m->post_restore_context = NULL;
1725
1726         armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1727         armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1728
1729         target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1730
1731         if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1732         {
1733                 return retval;
1734         }
1735
1736         return ERROR_OK;
1737 }
1738
1739 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1740 {
1741         struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1742
1743         cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1744         cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1745
1746         return ERROR_OK;
1747 }
1748
1749 /*--------------------------------------------------------------------------*/
1750
1751 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1752                 struct cortex_m3_common *cm3)
1753 {
1754         if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1755                 command_print(cmd_ctx, "target is not a Cortex-M3");
1756                 return ERROR_TARGET_INVALID;
1757         }
1758         return ERROR_OK;
1759 }
1760
1761 /*
1762  * Only stuff below this line should need to verify that its target
1763  * is a Cortex-M3.  Everything else should have indirected through the
1764  * cortexm3_target structure, which is only used with CM3 targets.
1765  */
1766
1767 /*
1768  * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1769  * as at least ARM-1156T2.  The interesting thing about Cortex-M is
1770  * that *only* Thumb2 disassembly matters.  There are also some small
1771  * additions to Thumb2 that are specific to ARMv7-M.
1772  */
1773 COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
1774 {
1775         int retval;
1776         struct target *target = get_current_target(CMD_CTX);
1777         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1778         uint32_t address;
1779         unsigned long count = 1;
1780         struct arm_instruction cur_instruction;
1781
1782         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1783         if (retval != ERROR_OK)
1784                 return retval;
1785
1786         errno = 0;
1787         switch (CMD_ARGC) {
1788         case 2:
1789                 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count);
1790                 /* FALL THROUGH */
1791         case 1:
1792                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1793                 break;
1794         default:
1795                 command_print(CMD_CTX,
1796                         "usage: cortex_m3 disassemble <address> [<count>]");
1797                 return ERROR_OK;
1798         }
1799
1800         while (count--) {
1801                 retval = thumb2_opcode(target, address, &cur_instruction);
1802                 if (retval != ERROR_OK)
1803                         return retval;
1804                 command_print(CMD_CTX, "%s", cur_instruction.text);
1805                 address += cur_instruction.instruction_size;
1806         }
1807
1808         return ERROR_OK;
1809 }
1810
1811 static const struct {
1812         char name[10];
1813         unsigned mask;
1814 } vec_ids[] = {
1815         { "hard_err",   VC_HARDERR, },
1816         { "int_err",    VC_INTERR, },
1817         { "bus_err",    VC_BUSERR, },
1818         { "state_err",  VC_STATERR, },
1819         { "chk_err",    VC_CHKERR, },
1820         { "nocp_err",   VC_NOCPERR, },
1821         { "mm_err",     VC_MMERR, },
1822         { "reset",      VC_CORERESET, },
1823 };
1824
1825 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1826 {
1827         struct target *target = get_current_target(CMD_CTX);
1828         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1829         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1830         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1831         uint32_t demcr = 0;
1832         int retval;
1833
1834         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1835         if (retval != ERROR_OK)
1836                 return retval;
1837
1838         mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1839
1840         if (CMD_ARGC > 0) {
1841                 unsigned catch = 0;
1842
1843                 if (CMD_ARGC == 1) {
1844                         if (strcmp(CMD_ARGV[0], "all") == 0) {
1845                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1846                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
1847                                         | VC_MMERR | VC_CORERESET;
1848                                 goto write;
1849                         } else if (strcmp(CMD_ARGV[0], "none") == 0) {
1850                                 goto write;
1851                         }
1852                 }
1853                 while (CMD_ARGC-- > 0) {
1854                         unsigned i;
1855                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1856                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
1857                                         continue;
1858                                 catch |= vec_ids[i].mask;
1859                                 break;
1860                         }
1861                         if (i == ARRAY_SIZE(vec_ids)) {
1862                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
1863                                 return ERROR_INVALID_ARGUMENTS;
1864                         }
1865                 }
1866 write:
1867                 demcr &= ~0xffff;
1868                 demcr |= catch;
1869
1870                 /* write, but don't assume it stuck */
1871                 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
1872                 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1873         }
1874
1875         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
1876         {
1877                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
1878                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
1879         }
1880
1881         return ERROR_OK;
1882 }
1883
1884 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
1885 {
1886         struct target *target = get_current_target(CMD_CTX);
1887         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1888         int retval;
1889
1890         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1891         if (retval != ERROR_OK)
1892                 return retval;
1893
1894         if (target->state != TARGET_HALTED)
1895         {
1896                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1897                 return ERROR_OK;
1898         }
1899
1900         if (CMD_ARGC > 0)
1901         {
1902                 bool enable;
1903                 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
1904                 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
1905                 uint32_t mask_off = enable ? 0 : C_MASKINTS;
1906                 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
1907         }
1908
1909         command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
1910                         (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
1911
1912         return ERROR_OK;
1913 }
1914
1915 static const struct command_registration cortex_m3_exec_command_handlers[] = {
1916         {
1917                 .name = "disassemble",
1918                 .handler = &handle_cortex_m3_disassemble_command,
1919                 .mode = COMMAND_EXEC,
1920                 .help = "disassemble Thumb2 instructions",
1921                 .usage = "<address> [<count>]",
1922         },
1923         {
1924                 .name = "maskisr",
1925                 .handler = &handle_cortex_m3_mask_interrupts_command,
1926                 .mode = COMMAND_EXEC,
1927                 .help = "mask cortex_m3 interrupts",
1928                 .usage = "['on'|'off']",
1929         },
1930         {
1931                 .name = "vector_catch",
1932                 .handler = &handle_cortex_m3_vector_catch_command,
1933                 .mode = COMMAND_EXEC,
1934                 .help = "catch hardware vectors",
1935                 .usage = "['all'|'none'|<list>]",
1936         },
1937         COMMAND_REGISTRATION_DONE
1938 };
1939 static const struct command_registration cortex_m3_command_handlers[] = {
1940         {
1941                 .chain = armv7m_command_handlers,
1942         },
1943         {
1944                 .name = "cortex_m3",
1945                 .mode = COMMAND_ANY,
1946                 .help = "Cortex-M3 command group",
1947                 .chain = cortex_m3_exec_command_handlers,
1948         },
1949         COMMAND_REGISTRATION_DONE
1950 };
1951
1952 struct target_type cortexm3_target =
1953 {
1954         .name = "cortex_m3",
1955
1956         .poll = cortex_m3_poll,
1957         .arch_state = armv7m_arch_state,
1958
1959         .target_request_data = cortex_m3_target_request_data,
1960
1961         .halt = cortex_m3_halt,
1962         .resume = cortex_m3_resume,
1963         .step = cortex_m3_step,
1964
1965         .assert_reset = cortex_m3_assert_reset,
1966         .deassert_reset = cortex_m3_deassert_reset,
1967         .soft_reset_halt = cortex_m3_soft_reset_halt,
1968
1969         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
1970
1971         .read_memory = cortex_m3_read_memory,
1972         .write_memory = cortex_m3_write_memory,
1973         .bulk_write_memory = cortex_m3_bulk_write_memory,
1974         .checksum_memory = armv7m_checksum_memory,
1975         .blank_check_memory = armv7m_blank_check_memory,
1976
1977         .run_algorithm = armv7m_run_algorithm,
1978
1979         .add_breakpoint = cortex_m3_add_breakpoint,
1980         .remove_breakpoint = cortex_m3_remove_breakpoint,
1981         .add_watchpoint = cortex_m3_add_watchpoint,
1982         .remove_watchpoint = cortex_m3_remove_watchpoint,
1983
1984         .commands = cortex_m3_command_handlers,
1985         .target_create = cortex_m3_target_create,
1986         .init_target = cortex_m3_init_target,
1987         .examine = cortex_m3_examine,
1988 };