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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "breakpoints.h"
  35 #include "cortex_m3.h"
  36 #include "target_request.h"
  37 #include "target_type.h"
  38 #include "arm_disassembler.h"
  39 #include "register.h"
  40
  41
  42 /* NOTE:  most of this should work fine for the Cortex-M1 and
  43  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  44  */
  45
  46
  47 /* forward declarations */
  48 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
  49 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
  50 static void cortex_m3_enable_watchpoints(struct target *target);
  51 static int cortex_m3_store_core_reg_u32(struct target *target,
  52                 enum armv7m_regtype type, uint32_t num, uint32_t value);
  53
  54 #ifdef ARMV7_GDB_HACKS
  55 extern uint8_t armv7m_gdb_dummy_cpsr_value[];
  56 extern struct reg armv7m_gdb_dummy_cpsr_reg;
  57 #endif
  58
  59 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
  60                 uint32_t *value, int regnum)
  61 {
  62         int retval;
  63         uint32_t dcrdr;
  64
  65         /* because the DCB_DCRDR is used for the emulated dcc channel
  66          * we have to save/restore the DCB_DCRDR when used */
  67
  68         mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  69
  70         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  71
  72         /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  73         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  74         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  75
  76         /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  77         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  78         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  79
  80         retval = swjdp_transaction_endcheck(swjdp);
  81
  82         /* restore DCB_DCRDR - this needs to be in a seperate
  83          * transaction otherwise the emulated DCC channel breaks */
  84         if (retval == ERROR_OK)
  85                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  86
  87         return retval;
  88 }
  89
  90 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
  91                 uint32_t value, int regnum)
  92 {
  93         int retval;
  94         uint32_t dcrdr;
  95
  96         /* because the DCB_DCRDR is used for the emulated dcc channel
  97          * we have to save/restore the DCB_DCRDR when used */
  98
  99         mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 100
 101         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 102
 103         /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
 104         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 105         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 106
 107         /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
 108         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 109         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 110
 111         retval = swjdp_transaction_endcheck(swjdp);
 112
 113         /* restore DCB_DCRDR - this needs to be in a seperate
 114          * transaction otherwise the emulated DCC channel breaks */
 115         if (retval == ERROR_OK)
 116                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 117
 118         return retval;
 119 }
 120
 121 static int cortex_m3_write_debug_halt_mask(struct target *target,
 122                 uint32_t mask_on, uint32_t mask_off)
 123 {
 124         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 125         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 126
 127         /* mask off status bits */
 128         cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 129         /* create new register mask */
 130         cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 131
 132         return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
 133 }
 134
 135 static int cortex_m3_clear_halt(struct target *target)
 136 {
 137         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 138         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 139
 140         /* clear step if any */
 141         cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 142
 143         /* Read Debug Fault Status Register */
 144         mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 145         /* Clear Debug Fault Status */
 146         mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
 147         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 148
 149         return ERROR_OK;
 150 }
 151
 152 static int cortex_m3_single_step_core(struct target *target)
 153 {
 154         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 155         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 156         uint32_t dhcsr_save;
 157
 158         /* backup dhcsr reg */
 159         dhcsr_save = cortex_m3->dcb_dhcsr;
 160
 161         /* mask interrupts if not done already */
 162         if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
 163                 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 164         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 165         LOG_DEBUG(" ");
 166
 167         /* restore dhcsr reg */
 168         cortex_m3->dcb_dhcsr = dhcsr_save;
 169         cortex_m3_clear_halt(target);
 170
 171         return ERROR_OK;
 172 }
 173
 174 static int cortex_m3_endreset_event(struct target *target)
 175 {
 176         int i;
 177         uint32_t dcb_demcr;
 178         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 179         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 180         struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 181         struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 182
 183         mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 184         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 185
 186         /* this regsiter is used for emulated dcc channel */
 187         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 188
 189         /* Enable debug requests */
 190         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 191         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 192                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 193
 194         /* clear any interrupt masking */
 195         cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
 196
 197         /* Enable trace and dwt */
 198         mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
 199         /* Monitor bus faults */
 200         mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
 201
 202         /* Enable FPB */
 203         target_write_u32(target, FP_CTRL, 3);
 204         cortex_m3->fpb_enabled = 1;
 205
 206         /* Restore FPB registers */
 207         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
 208         {
 209                 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 210         }
 211
 212         /* Restore DWT registers */
 213         for (i = 0; i < cortex_m3->dwt_num_comp; i++)
 214         {
 215                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 216                                 dwt_list[i].comp);
 217                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 218                                 dwt_list[i].mask);
 219                 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 220                                 dwt_list[i].function);
 221         }
 222         swjdp_transaction_endcheck(swjdp);
 223
 224         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 225
 226         /* make sure we have latest dhcsr flags */
 227         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 228
 229         return ERROR_OK;
 230 }
 231
 232 static int cortex_m3_examine_debug_reason(struct target *target)
 233 {
 234         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 235
 236         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
 237         /* only check the debug reason if we don't know it already */
 238
 239         if ((target->debug_reason != DBG_REASON_DBGRQ)
 240                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 241         {
 242                 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 243                 {
 244                         target->debug_reason = DBG_REASON_BREAKPOINT;
 245                         if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 246                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 247                 }
 248                 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 249                         target->debug_reason = DBG_REASON_WATCHPOINT;
 250                 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
 251                         target->debug_reason = DBG_REASON_BREAKPOINT;
 252                 else /* EXTERNAL, HALTED */
 253                         target->debug_reason = DBG_REASON_UNDEFINED;
 254         }
 255
 256         return ERROR_OK;
 257 }
 258
 259 static int cortex_m3_examine_exception_reason(struct target *target)
 260 {
 261         uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
 262         struct armv7m_common *armv7m = target_to_armv7m(target);
 263         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 264
 265         mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 266         switch (armv7m->exception_number)
 267         {
 268                 case 2: /* NMI */
 269                         break;
 270                 case 3: /* Hard Fault */
 271                         mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 272                         if (except_sr & 0x40000000)
 273                         {
 274                                 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
 275                         }
 276                         break;
 277                 case 4: /* Memory Management */
 278                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 279                         mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
 280                         break;
 281                 case 5: /* Bus Fault */
 282                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 283                         mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
 284                         break;
 285                 case 6: /* Usage Fault */
 286                         mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 287                         break;
 288                 case 11:        /* SVCall */
 289                         break;
 290                 case 12:        /* Debug Monitor */
 291                         mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
 292                         break;
 293                 case 14:        /* PendSV */
 294                         break;
 295                 case 15:        /* SysTick */
 296                         break;
 297                 default:
 298                         except_sr = 0;
 299                         break;
 300         }
 301         swjdp_transaction_endcheck(swjdp);
 302         LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
 303                 shcsr, except_sr, cfsr, except_ar);
 304         return ERROR_OK;
 305 }
 306
 307 static int cortex_m3_debug_entry(struct target *target)
 308 {
 309         int i;
 310         uint32_t xPSR;
 311         int retval;
 312         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 313         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 314         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 315
 316         LOG_DEBUG(" ");
 317
 318         cortex_m3_clear_halt(target);
 319         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 320
 321         if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
 322                 return retval;
 323
 324         /* Examine target state and mode */
 325         /* First load register acessible through core debug port*/
 326         int num_regs = armv7m->core_cache->num_regs;
 327
 328         for (i = 0; i < num_regs; i++)
 329         {
 330                 if (!armv7m->core_cache->reg_list[i].valid)
 331                         armv7m->read_core_reg(target, i);
 332         }
 333
 334         xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
 335
 336 #ifdef ARMV7_GDB_HACKS
 337         /* FIXME this breaks on scan chains with more than one Cortex-M3.
 338          * Instead, each CM3 should have its own dummy value...
 339          */
 340         /* copy real xpsr reg for gdb, setting thumb bit */
 341         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
 342         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
 343         armv7m_gdb_dummy_cpsr_reg.valid = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
 344         armv7m_gdb_dummy_cpsr_reg.dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty;
 345 #endif
 346
 347         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 348         if (xPSR & 0xf00)
 349         {
 350                 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
 351                 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 352         }
 353
 354         /* Are we in an exception handler */
 355         if (xPSR & 0x1FF)
 356         {
 357                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 358                 armv7m->exception_number = (xPSR & 0x1FF);
 359         }
 360         else
 361         {
 362                 armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
 363                 armv7m->exception_number = 0;
 364         }
 365
 366         if (armv7m->exception_number)
 367         {
 368                 cortex_m3_examine_exception_reason(target);
 369         }
 370
 371         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 372                 armv7m_mode_strings[armv7m->core_mode],
 373                 *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
 374                 target_state_name(target));
 375
 376         if (armv7m->post_debug_entry)
 377                 armv7m->post_debug_entry(target);
 378
 379         return ERROR_OK;
 380 }
 381
 382 static int cortex_m3_poll(struct target *target)
 383 {
 384         int retval;
 385         enum target_state prev_target_state = target->state;
 386         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 387         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 388
 389         /* Read from Debug Halting Control and Status Register */
 390         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 391         if (retval != ERROR_OK)
 392         {
 393                 target->state = TARGET_UNKNOWN;
 394                 return retval;
 395         }
 396
 397         if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 398         {
 399                 /* check if still in reset */
 400                 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 401
 402                 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 403                 {
 404                         target->state = TARGET_RESET;
 405                         return ERROR_OK;
 406                 }
 407         }
 408
 409         if (target->state == TARGET_RESET)
 410         {
 411                 /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
 412                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32 "", cortex_m3->dcb_dhcsr);
 413                 cortex_m3_endreset_event(target);
 414                 target->state = TARGET_RUNNING;
 415                 prev_target_state = TARGET_RUNNING;
 416         }
 417
 418         if (cortex_m3->dcb_dhcsr & S_HALT)
 419         {
 420                 target->state = TARGET_HALTED;
 421
 422                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 423                 {
 424                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 425                                 return retval;
 426
 427                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 428                 }
 429                 if (prev_target_state == TARGET_DEBUG_RUNNING)
 430                 {
 431                         LOG_DEBUG(" ");
 432                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 433                                 return retval;
 434
 435                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 436                 }
 437         }
 438
 439         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 440          * How best to model low power modes?
 441          */
 442
 443         if (target->state == TARGET_UNKNOWN)
 444         {
 445                 /* check if processor is retiring instructions */
 446                 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
 447                 {
 448                         target->state = TARGET_RUNNING;
 449                         return ERROR_OK;
 450                 }
 451         }
 452
 453         return ERROR_OK;
 454 }
 455
 456 static int cortex_m3_halt(struct target *target)
 457 {
 458         LOG_DEBUG("target->state: %s",
 459                 target_state_name(target));
 460
 461         if (target->state == TARGET_HALTED)
 462         {
 463                 LOG_DEBUG("target was already halted");
 464                 return ERROR_OK;
 465         }
 466
 467         if (target->state == TARGET_UNKNOWN)
 468         {
 469                 LOG_WARNING("target was in unknown state when halt was requested");
 470         }
 471
 472         if (target->state == TARGET_RESET)
 473         {
 474                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
 475                 {
 476                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 477                         return ERROR_TARGET_FAILURE;
 478                 }
 479                 else
 480                 {
 481                         /* we came here in a reset_halt or reset_init sequence
 482                          * debug entry was already prepared in cortex_m3_prepare_reset_halt()
 483                          */
 484                         target->debug_reason = DBG_REASON_DBGRQ;
 485
 486                         return ERROR_OK;
 487                 }
 488         }
 489
 490         /* Write to Debug Halting Control and Status Register */
 491         cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 492
 493         target->debug_reason = DBG_REASON_DBGRQ;
 494
 495         return ERROR_OK;
 496 }
 497
 498 static int cortex_m3_soft_reset_halt(struct target *target)
 499 {
 500         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 501         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 502         uint32_t dcb_dhcsr = 0;
 503         int retval, timeout = 0;
 504
 505         /* Enter debug state on reset, cf. end_reset_event() */
 506         mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 507
 508         /* Request a reset */
 509         mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
 510         target->state = TARGET_RESET;
 511
 512         /* registers are now invalid */
 513         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 514
 515         while (timeout < 100)
 516         {
 517                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 518                 if (retval == ERROR_OK)
 519                 {
 520                         mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 521                         if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 522                         {
 523                                 LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32 ", nvic_dfsr 0x%" PRIx32 "", dcb_dhcsr, cortex_m3->nvic_dfsr);
 524                                 cortex_m3_poll(target);
 525                                 return ERROR_OK;
 526                         }
 527                         else
 528                                 LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32 ", %i ms", dcb_dhcsr, timeout);
 529                 }
 530                 timeout++;
 531                 alive_sleep(1);
 532         }
 533
 534         return ERROR_OK;
 535 }
 536
 537 static void cortex_m3_enable_breakpoints(struct target *target)
 538 {
 539         struct breakpoint *breakpoint = target->breakpoints;
 540
 541         /* set any pending breakpoints */
 542         while (breakpoint)
 543         {
 544                 if (breakpoint->set == 0)
 545                         cortex_m3_set_breakpoint(target, breakpoint);
 546                 breakpoint = breakpoint->next;
 547         }
 548 }
 549
 550 static int cortex_m3_resume(struct target *target, int current,
 551                 uint32_t address, int handle_breakpoints, int debug_execution)
 552 {
 553         struct armv7m_common *armv7m = target_to_armv7m(target);
 554         struct breakpoint *breakpoint = NULL;
 555         uint32_t resume_pc;
 556
 557         if (target->state != TARGET_HALTED)
 558         {
 559                 LOG_WARNING("target not halted");
 560                 return ERROR_TARGET_NOT_HALTED;
 561         }
 562
 563         if (!debug_execution)
 564         {
 565                 target_free_all_working_areas(target);
 566                 cortex_m3_enable_breakpoints(target);
 567                 cortex_m3_enable_watchpoints(target);
 568         }
 569
 570         if (debug_execution)
 571         {
 572                 /* Disable interrupts */
 573                 /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
 574                  * This is probably the same issue as Cortex-M3 Errata  377493:
 575                  * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
 576                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
 577                 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
 578                 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
 579
 580                 /* Make sure we are in Thumb mode */
 581                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
 582                         buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
 583                 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
 584                 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
 585         }
 586
 587         /* current = 1: continue on current pc, otherwise continue at <address> */
 588         if (!current)
 589         {
 590                 buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
 591                 armv7m->core_cache->reg_list[15].dirty = 1;
 592                 armv7m->core_cache->reg_list[15].valid = 1;
 593         }
 594
 595         resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32);
 596
 597         armv7m_restore_context(target);
 598
 599         /* the front-end may request us not to handle breakpoints */
 600         if (handle_breakpoints)
 601         {
 602                 /* Single step past breakpoint at current address */
 603                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 604                 {
 605                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 606                                           breakpoint->address,
 607                                           breakpoint->unique_id);
 608                         cortex_m3_unset_breakpoint(target, breakpoint);
 609                         cortex_m3_single_step_core(target);
 610                         cortex_m3_set_breakpoint(target, breakpoint);
 611                 }
 612         }
 613
 614         /* Restart core */
 615         cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 616
 617         target->debug_reason = DBG_REASON_NOTHALTED;
 618
 619         /* registers are now invalid */
 620         register_cache_invalidate(armv7m->core_cache);
 621
 622         if (!debug_execution)
 623         {
 624                 target->state = TARGET_RUNNING;
 625                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 626                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 627         }
 628         else
 629         {
 630                 target->state = TARGET_DEBUG_RUNNING;
 631                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 632                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 633         }
 634
 635         return ERROR_OK;
 636 }
 637
 638 /* int irqstepcount = 0; */
 639 static int cortex_m3_step(struct target *target, int current,
 640                 uint32_t address, int handle_breakpoints)
 641 {
 642         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 643         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 644         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 645         struct breakpoint *breakpoint = NULL;
 646
 647         if (target->state != TARGET_HALTED)
 648         {
 649                 LOG_WARNING("target not halted");
 650                 return ERROR_TARGET_NOT_HALTED;
 651         }
 652
 653         /* current = 1: continue on current pc, otherwise continue at <address> */
 654         if (!current)
 655                 buf_set_u32(cortex_m3->armv7m.core_cache->reg_list[15].value,
 656                                 0, 32, address);
 657
 658         /* the front-end may request us not to handle breakpoints */
 659         if (handle_breakpoints) {
 660                 breakpoint = breakpoint_find(target, buf_get_u32(armv7m
 661                                 ->core_cache->reg_list[15].value, 0, 32));
 662                 if (breakpoint)
 663                         cortex_m3_unset_breakpoint(target, breakpoint);
 664         }
 665
 666         target->debug_reason = DBG_REASON_SINGLESTEP;
 667
 668         armv7m_restore_context(target);
 669
 670         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 671
 672         /* set step and clear halt */
 673         cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 674         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 675
 676         /* registers are now invalid */
 677         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 678
 679         if (breakpoint)
 680                 cortex_m3_set_breakpoint(target, breakpoint);
 681
 682         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 683
 684         cortex_m3_debug_entry(target);
 685         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 686
 687         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 688         return ERROR_OK;
 689 }
 690
 691 static int cortex_m3_assert_reset(struct target *target)
 692 {
 693         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 694         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 695         int assert_srst = 1;
 696
 697         LOG_DEBUG("target->state: %s",
 698                 target_state_name(target));
 699
 700         enum reset_types jtag_reset_config = jtag_get_reset_config();
 701
 702         /*
 703          * We can reset Cortex-M3 targets using just the NVIC without
 704          * requiring SRST, getting a SoC reset (or a core-only reset)
 705          * instead of a system reset.
 706          */
 707         if (!(jtag_reset_config & RESET_HAS_SRST))
 708                 assert_srst = 0;
 709
 710         /* Enable debug requests */
 711         mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 712         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 713                 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 714
 715         mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 716
 717         if (!target->reset_halt)
 718         {
 719                 /* Set/Clear C_MASKINTS in a separate operation */
 720                 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
 721                         mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
 722
 723                 /* clear any debug flags before resuming */
 724                 cortex_m3_clear_halt(target);
 725
 726                 /* clear C_HALT in dhcsr reg */
 727                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 728
 729                 /* Enter debug state on reset, cf. end_reset_event() */
 730                 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
 731         }
 732         else
 733         {
 734                 /* Enter debug state on reset, cf. end_reset_event() */
 735                 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 736         }
 737
 738         /*
 739          * When nRST is asserted on most Stellaris devices, it clears some of
 740          * the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
 741          * and OpenOCD depends on those TRMs.  So we won't use SRST on those
 742          * chips.  (Only power-on reset should affect debug state, beyond a
 743          * few specified bits; not the chip's nRST input, wired to SRST.)
 744          *
 745          * REVISIT current errata specs don't seem to cover this issue.
 746          * Do we have more details than this email?
 747          *   https://lists.berlios.de/pipermail
 748          *      /openocd-development/2008-August/003065.html
 749          */
 750         if (strcmp(target->variant, "lm3s") == 0)
 751         {
 752                 /* Check for silicon revisions with the issue. */
 753                 uint32_t did0;
 754
 755                 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
 756                 {
 757                         switch ((did0 >> 16) & 0xff)
 758                         {
 759                                 case 0:
 760                                         /* all Sandstorm suffer issue */
 761                                         assert_srst = 0;
 762                                         break;
 763
 764                                 case 1:
 765                                 case 3:
 766                                         /* Fury and DustDevil rev A have
 767                                          * this nRST problem.  It should
 768                                          * be fixed in rev B silicon.
 769                                          */
 770                                         if (((did0 >> 8) & 0xff) == 0)
 771                                                 assert_srst = 0;
 772                                         break;
 773                                 case 4:
 774                                         /* Tempest should be fine. */
 775                                         break;
 776                         }
 777                 }
 778         }
 779
 780         if (assert_srst)
 781         {
 782                 /* default to asserting srst */
 783                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 784                 {
 785                         jtag_add_reset(1, 1);
 786                 }
 787                 else
 788                 {
 789                         jtag_add_reset(0, 1);
 790                 }
 791         }
 792         else
 793         {
 794                 /* Use a standard Cortex-M3 software reset mechanism.
 795                  * SYSRESETREQ will reset SoC peripherals outside the
 796                  * core, like watchdog timers, if the SoC wires it up
 797                  * correctly.  Else VECRESET can reset just the core.
 798                  */
 799                 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 800                                 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
 801                 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
 802
 803                 {
 804                         /* I do not know why this is necessary, but it
 805                          * fixes strange effects (step/resume cause NMI
 806                          * after reset) on LM3S6918 -- Michael Schwingen
 807                          */
 808                         uint32_t tmp;
 809                         mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
 810                 }
 811         }
 812
 813         target->state = TARGET_RESET;
 814         jtag_add_sleep(50000);
 815
 816         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 817
 818         if (target->reset_halt)
 819         {
 820                 int retval;
 821                 if ((retval = target_halt(target)) != ERROR_OK)
 822                         return retval;
 823         }
 824
 825         return ERROR_OK;
 826 }
 827
 828 static int cortex_m3_deassert_reset(struct target *target)
 829 {
 830         LOG_DEBUG("target->state: %s",
 831                 target_state_name(target));
 832
 833         /* deassert reset lines */
 834         jtag_add_reset(0, 0);
 835
 836         return ERROR_OK;
 837 }
 838
 839 static int
 840 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
 841 {
 842         int retval;
 843         int fp_num = 0;
 844         uint32_t hilo;
 845         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 846         struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
 847
 848         if (breakpoint->set)
 849         {
 850                 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
 851                 return ERROR_OK;
 852         }
 853
 854         if (cortex_m3->auto_bp_type)
 855         {
 856                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
 857         }
 858
 859         if (breakpoint->type == BKPT_HARD)
 860         {
 861                 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
 862                         fp_num++;
 863                 if (fp_num >= cortex_m3->fp_num_code)
 864                 {
 865                         LOG_ERROR("Can not find free FPB Comparator!");
 866                         return ERROR_FAIL;
 867                 }
 868                 breakpoint->set = fp_num + 1;
 869                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
 870                 comparator_list[fp_num].used = 1;
 871                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
 872                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
 873                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
 874                 if (!cortex_m3->fpb_enabled)
 875                 {
 876                         LOG_DEBUG("FPB wasn't enabled, do it now");
 877                         target_write_u32(target, FP_CTRL, 3);
 878                 }
 879         }
 880         else if (breakpoint->type == BKPT_SOFT)
 881         {
 882                 uint8_t code[4];
 883                 buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
 884                 if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
 885                 {
 886                         return retval;
 887                 }
 888                 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
 889                 {
 890                         return retval;
 891                 }
 892                 breakpoint->set = 0x11; /* Any nice value but 0 */
 893         }
 894
 895         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
 896                           breakpoint->unique_id,
 897                           (int)(breakpoint->type),
 898                           breakpoint->address,
 899                           breakpoint->length,
 900                           breakpoint->set);
 901
 902         return ERROR_OK;
 903 }
 904
 905 static int
 906 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
 907 {
 908         int retval;
 909         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 910         struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
 911
 912         if (!breakpoint->set)
 913         {
 914                 LOG_WARNING("breakpoint not set");
 915                 return ERROR_OK;
 916         }
 917
 918         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
 919                           breakpoint->unique_id,
 920                           (int)(breakpoint->type),
 921                           breakpoint->address,
 922                           breakpoint->length,
 923                           breakpoint->set);
 924
 925         if (breakpoint->type == BKPT_HARD)
 926         {
 927                 int fp_num = breakpoint->set - 1;
 928                 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
 929                 {
 930                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
 931                         return ERROR_OK;
 932                 }
 933                 comparator_list[fp_num].used = 0;
 934                 comparator_list[fp_num].fpcr_value = 0;
 935                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
 936         }
 937         else
 938         {
 939                 /* restore original instruction (kept in target endianness) */
 940                 if (breakpoint->length == 4)
 941                 {
 942                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 943                         {
 944                                 return retval;
 945                         }
 946                 }
 947                 else
 948                 {
 949                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 950                         {
 951                                 return retval;
 952                         }
 953                 }
 954         }
 955         breakpoint->set = 0;
 956
 957         return ERROR_OK;
 958 }
 959
 960 static int
 961 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 962 {
 963         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 964
 965         if (cortex_m3->auto_bp_type)
 966         {
 967                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
 968 #ifdef ARMV7_GDB_HACKS
 969                 if (breakpoint->length != 2) {
 970                         /* XXX Hack: Replace all breakpoints with length != 2 with
 971                          * a hardware breakpoint. */
 972                         breakpoint->type = BKPT_HARD;
 973                         breakpoint->length = 2;
 974                 }
 975 #endif
 976         }
 977
 978         if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
 979         {
 980                 LOG_INFO("flash patch comparator requested outside code memory region");
 981                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 982         }
 983
 984         if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
 985         {
 986                 LOG_INFO("soft breakpoint requested in code (flash) memory region");
 987                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 988         }
 989
 990         if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
 991         {
 992                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
 993                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 994         }
 995
 996         if ((breakpoint->length != 2))
 997         {
 998                 LOG_INFO("only breakpoints of two bytes length supported");
 999                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1000         }
1001
1002         if (breakpoint->type == BKPT_HARD)
1003                 cortex_m3->fp_code_available--;
1004         cortex_m3_set_breakpoint(target, breakpoint);
1005
1006         return ERROR_OK;
1007 }
1008
1009 static int
1010 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1011 {
1012         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1013
1014         /* REVISIT why check? FBP can be updated with core running ... */
1015         if (target->state != TARGET_HALTED)
1016         {
1017                 LOG_WARNING("target not halted");
1018                 return ERROR_TARGET_NOT_HALTED;
1019         }
1020
1021         if (cortex_m3->auto_bp_type)
1022         {
1023                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1024         }
1025
1026         if (breakpoint->set)
1027         {
1028                 cortex_m3_unset_breakpoint(target, breakpoint);
1029         }
1030
1031         if (breakpoint->type == BKPT_HARD)
1032                 cortex_m3->fp_code_available++;
1033
1034         return ERROR_OK;
1035 }
1036
1037 static int
1038 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1039 {
1040         int dwt_num = 0;
1041         uint32_t mask, temp;
1042         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1043
1044         /* watchpoint params were validated earlier */
1045         mask = 0;
1046         temp = watchpoint->length;
1047         while (temp) {
1048                 temp >>= 1;
1049                 mask++;
1050         }
1051         mask--;
1052
1053         /* REVISIT Don't fully trust these "not used" records ... users
1054          * may set up breakpoints by hand, e.g. dual-address data value
1055          * watchpoint using comparator #1; comparator #0 matching cycle
1056          * count; send data trace info through ITM and TPIU; etc
1057          */
1058         struct cortex_m3_dwt_comparator *comparator;
1059
1060         for (comparator = cortex_m3->dwt_comparator_list;
1061                         comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1062                         comparator++, dwt_num++)
1063                 continue;
1064         if (dwt_num >= cortex_m3->dwt_num_comp)
1065         {
1066                 LOG_ERROR("Can not find free DWT Comparator");
1067                 return ERROR_FAIL;
1068         }
1069         comparator->used = 1;
1070         watchpoint->set = dwt_num + 1;
1071
1072         comparator->comp = watchpoint->address;
1073         target_write_u32(target, comparator->dwt_comparator_address + 0,
1074                         comparator->comp);
1075
1076         comparator->mask = mask;
1077         target_write_u32(target, comparator->dwt_comparator_address + 4,
1078                         comparator->mask);
1079
1080         switch (watchpoint->rw) {
1081         case WPT_READ:
1082                 comparator->function = 5;
1083                 break;
1084         case WPT_WRITE:
1085                 comparator->function = 6;
1086                 break;
1087         case WPT_ACCESS:
1088                 comparator->function = 7;
1089                 break;
1090         }
1091         target_write_u32(target, comparator->dwt_comparator_address + 8,
1092                         comparator->function);
1093
1094         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1095                         watchpoint->unique_id, dwt_num,
1096                         (unsigned) comparator->comp,
1097                         (unsigned) comparator->mask,
1098                         (unsigned) comparator->function);
1099         return ERROR_OK;
1100 }
1101
1102 static int
1103 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1104 {
1105         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1106         struct cortex_m3_dwt_comparator *comparator;
1107         int dwt_num;
1108
1109         if (!watchpoint->set)
1110         {
1111                 LOG_WARNING("watchpoint (wpid: %d) not set",
1112                                 watchpoint->unique_id);
1113                 return ERROR_OK;
1114         }
1115
1116         dwt_num = watchpoint->set - 1;
1117
1118         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1119                         watchpoint->unique_id, dwt_num,
1120                         (unsigned) watchpoint->address);
1121
1122         if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1123         {
1124                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1125                 return ERROR_OK;
1126         }
1127
1128         comparator = cortex_m3->dwt_comparator_list + dwt_num;
1129         comparator->used = 0;
1130         comparator->function = 0;
1131         target_write_u32(target, comparator->dwt_comparator_address + 8,
1132                         comparator->function);
1133
1134         watchpoint->set = 0;
1135
1136         return ERROR_OK;
1137 }
1138
1139 static int
1140 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1141 {
1142         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1143
1144         /* REVISIT why check? DWT can be updated with core running ... */
1145         if (target->state != TARGET_HALTED)
1146         {
1147                 LOG_WARNING("target not halted");
1148                 return ERROR_TARGET_NOT_HALTED;
1149         }
1150
1151         if (cortex_m3->dwt_comp_available < 1)
1152         {
1153                 LOG_DEBUG("no comparators?");
1154                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1155         }
1156
1157         /* hardware doesn't support data value masking */
1158         if (watchpoint->mask != ~(uint32_t)0) {
1159                 LOG_DEBUG("watchpoint value masks not supported");
1160                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1161         }
1162
1163         /* hardware allows address masks of up to 32K */
1164         unsigned mask;
1165
1166         for (mask = 0; mask < 16; mask++) {
1167                 if ((1u << mask) == watchpoint->length)
1168                         break;
1169         }
1170         if (mask == 16) {
1171                 LOG_DEBUG("unsupported watchpoint length");
1172                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1173         }
1174         if (watchpoint->address & ((1 << mask) - 1)) {
1175                 LOG_DEBUG("watchpoint address is unaligned");
1176                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1177         }
1178
1179         /* Caller doesn't seem to be able to describe watching for data
1180          * values of zero; that flags "no value".
1181          *
1182          * REVISIT This DWT may well be able to watch for specific data
1183          * values.  Requires comparator #1 to set DATAVMATCH and match
1184          * the data, and another comparator (DATAVADDR0) matching addr.
1185          */
1186         if (watchpoint->value) {
1187                 LOG_DEBUG("data value watchpoint not YET supported");
1188                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1189         }
1190
1191         cortex_m3->dwt_comp_available--;
1192         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1193
1194         return ERROR_OK;
1195 }
1196
1197 static int
1198 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1199 {
1200         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1201
1202         /* REVISIT why check? DWT can be updated with core running ... */
1203         if (target->state != TARGET_HALTED)
1204         {
1205                 LOG_WARNING("target not halted");
1206                 return ERROR_TARGET_NOT_HALTED;
1207         }
1208
1209         if (watchpoint->set)
1210         {
1211                 cortex_m3_unset_watchpoint(target, watchpoint);
1212         }
1213
1214         cortex_m3->dwt_comp_available++;
1215         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1216
1217         return ERROR_OK;
1218 }
1219
1220 static void cortex_m3_enable_watchpoints(struct target *target)
1221 {
1222         struct watchpoint *watchpoint = target->watchpoints;
1223
1224         /* set any pending watchpoints */
1225         while (watchpoint)
1226         {
1227                 if (watchpoint->set == 0)
1228                         cortex_m3_set_watchpoint(target, watchpoint);
1229                 watchpoint = watchpoint->next;
1230         }
1231 }
1232
1233 static int cortex_m3_load_core_reg_u32(struct target *target,
1234                 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1235 {
1236         int retval;
1237         struct armv7m_common *armv7m = target_to_armv7m(target);
1238         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1239
1240         /* NOTE:  we "know" here that the register identifiers used
1241          * in the v7m header match the Cortex-M3 Debug Core Register
1242          * Selector values for R0..R15, xPSR, MSP, and PSP.
1243          */
1244         switch (num) {
1245         case 0 ... 18:
1246                 /* read a normal core register */
1247                 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1248
1249                 if (retval != ERROR_OK)
1250                 {
1251                         LOG_ERROR("JTAG failure %i",retval);
1252                         return ERROR_JTAG_DEVICE_ERROR;
1253                 }
1254                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",(int)num,*value);
1255                 break;
1256
1257         case ARMV7M_PRIMASK:
1258         case ARMV7M_BASEPRI:
1259         case ARMV7M_FAULTMASK:
1260         case ARMV7M_CONTROL:
1261                 /* Cortex-M3 packages these four registers as bitfields
1262                  * in one Debug Core register.  So say r0 and r2 docs;
1263                  * it was removed from r1 docs, but still works.
1264                  */
1265                 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1266
1267                 switch (num)
1268                 {
1269                         case ARMV7M_PRIMASK:
1270                                 *value = buf_get_u32((uint8_t*)value, 0, 1);
1271                                 break;
1272
1273                         case ARMV7M_BASEPRI:
1274                                 *value = buf_get_u32((uint8_t*)value, 8, 8);
1275                                 break;
1276
1277                         case ARMV7M_FAULTMASK:
1278                                 *value = buf_get_u32((uint8_t*)value, 16, 1);
1279                                 break;
1280
1281                         case ARMV7M_CONTROL:
1282                                 *value = buf_get_u32((uint8_t*)value, 24, 2);
1283                                 break;
1284                 }
1285
1286                 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1287                 break;
1288
1289         default:
1290                 return ERROR_INVALID_ARGUMENTS;
1291         }
1292
1293         return ERROR_OK;
1294 }
1295
1296 static int cortex_m3_store_core_reg_u32(struct target *target,
1297                 enum armv7m_regtype type, uint32_t num, uint32_t value)
1298 {
1299         int retval;
1300         uint32_t reg;
1301         struct armv7m_common *armv7m = target_to_armv7m(target);
1302         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1303
1304 #ifdef ARMV7_GDB_HACKS
1305         /* If the LR register is being modified, make sure it will put us
1306          * in "thumb" mode, or an INVSTATE exception will occur. This is a
1307          * hack to deal with the fact that gdb will sometimes "forge"
1308          * return addresses, and doesn't set the LSB correctly (i.e., when
1309          * printing expressions containing function calls, it sets LR = 0.)
1310          * Valid exception return codes have bit 0 set too.
1311          */
1312         if (num == ARMV7M_R14)
1313                 value |= 0x01;
1314 #endif
1315
1316         /* NOTE:  we "know" here that the register identifiers used
1317          * in the v7m header match the Cortex-M3 Debug Core Register
1318          * Selector values for R0..R15, xPSR, MSP, and PSP.
1319          */
1320         switch (num) {
1321         case 0 ... 18:
1322                 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1323                 if (retval != ERROR_OK)
1324                 {
1325                         LOG_ERROR("JTAG failure %i", retval);
1326                         armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
1327                         return ERROR_JTAG_DEVICE_ERROR;
1328                 }
1329                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1330                 break;
1331
1332         case ARMV7M_PRIMASK:
1333         case ARMV7M_BASEPRI:
1334         case ARMV7M_FAULTMASK:
1335         case ARMV7M_CONTROL:
1336                 /* Cortex-M3 packages these four registers as bitfields
1337                  * in one Debug Core register.  So say r0 and r2 docs;
1338                  * it was removed from r1 docs, but still works.
1339                  */
1340                 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1341
1342                 switch (num)
1343                 {
1344                         case ARMV7M_PRIMASK:
1345                                 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1346                                 break;
1347
1348                         case ARMV7M_BASEPRI:
1349                                 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1350                                 break;
1351
1352                         case ARMV7M_FAULTMASK:
1353                                 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1354                                 break;
1355
1356                         case ARMV7M_CONTROL:
1357                                 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1358                                 break;
1359                 }
1360
1361                 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1362
1363                 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1364                 break;
1365
1366         default:
1367                 return ERROR_INVALID_ARGUMENTS;
1368         }
1369
1370         return ERROR_OK;
1371 }
1372
1373 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1374                 uint32_t size, uint32_t count, uint8_t *buffer)
1375 {
1376         struct armv7m_common *armv7m = target_to_armv7m(target);
1377         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1378         int retval = ERROR_INVALID_ARGUMENTS;
1379
1380         /* cortex_m3 handles unaligned memory access */
1381         if (count && buffer) {
1382                 switch (size) {
1383                 case 4:
1384                         retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1385                         break;
1386                 case 2:
1387                         retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1388                         break;
1389                 case 1:
1390                         retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1391                         break;
1392                 }
1393         }
1394
1395         return retval;
1396 }
1397
1398 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1399                 uint32_t size, uint32_t count, uint8_t *buffer)
1400 {
1401         struct armv7m_common *armv7m = target_to_armv7m(target);
1402         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1403         int retval = ERROR_INVALID_ARGUMENTS;
1404
1405         if (count && buffer) {
1406                 switch (size) {
1407                 case 4:
1408                         retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1409                         break;
1410                 case 2:
1411                         retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1412                         break;
1413                 case 1:
1414                         retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1415                         break;
1416                 }
1417         }
1418
1419         return retval;
1420 }
1421
1422 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1423                 uint32_t count, uint8_t *buffer)
1424 {
1425         return cortex_m3_write_memory(target, address, 4, count, buffer);
1426 }
1427
1428 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1429                 struct target *target)
1430 {
1431         armv7m_build_reg_cache(target);
1432         return ERROR_OK;
1433 }
1434
1435 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1436  * on r/w if the core is not running, and clear on resume or reset ... or
1437  * at least, in a post_restore_context() method.
1438  */
1439
1440 struct dwt_reg_state {
1441         struct target   *target;
1442         uint32_t        addr;
1443         uint32_t        value;  /* scratch/cache */
1444 };
1445
1446 static int cortex_m3_dwt_get_reg(struct reg *reg)
1447 {
1448         struct dwt_reg_state *state = reg->arch_info;
1449
1450         return target_read_u32(state->target, state->addr, &state->value);
1451 }
1452
1453 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1454 {
1455         struct dwt_reg_state *state = reg->arch_info;
1456
1457         return target_write_u32(state->target, state->addr,
1458                         buf_get_u32(buf, 0, reg->size));
1459 }
1460
1461 struct dwt_reg {
1462         uint32_t        addr;
1463         char            *name;
1464         unsigned        size;
1465 };
1466
1467 static struct dwt_reg dwt_base_regs[] = {
1468         { DWT_CTRL, "dwt_ctrl", 32, },
1469         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1470         /* plus some 8 bit counters, useful for profiling with TPIU */
1471 };
1472
1473 static struct dwt_reg dwt_comp[] = {
1474 #define DWT_COMPARATOR(i) \
1475                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1476                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1477                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1478         DWT_COMPARATOR(0),
1479         DWT_COMPARATOR(1),
1480         DWT_COMPARATOR(2),
1481         DWT_COMPARATOR(3),
1482 #undef DWT_COMPARATOR
1483 };
1484
1485 static const struct reg_arch_type dwt_reg_type = {
1486         .get = cortex_m3_dwt_get_reg,
1487         .set = cortex_m3_dwt_set_reg,
1488 };
1489
1490 static void
1491 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1492 {
1493         struct dwt_reg_state *state;
1494
1495         state = calloc(1, sizeof *state);
1496         if (!state)
1497                 return;
1498         state->addr = d->addr;
1499         state->target = t;
1500
1501         r->name = d->name;
1502         r->size = d->size;
1503         r->value = &state->value;
1504         r->arch_info = state;
1505         r->type = &dwt_reg_type;
1506 }
1507
1508 static void
1509 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1510 {
1511         uint32_t dwtcr;
1512         struct reg_cache *cache;
1513         struct cortex_m3_dwt_comparator *comparator;
1514         int reg, i;
1515
1516         target_read_u32(target, DWT_CTRL, &dwtcr);
1517         if (!dwtcr) {
1518                 LOG_DEBUG("no DWT");
1519                 return;
1520         }
1521
1522         cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1523         cm3->dwt_comp_available = cm3->dwt_num_comp;
1524         cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1525                         sizeof(struct cortex_m3_dwt_comparator));
1526         if (!cm3->dwt_comparator_list) {
1527 fail0:
1528                 cm3->dwt_num_comp = 0;
1529                 LOG_ERROR("out of mem");
1530                 return;
1531         }
1532
1533         cache = calloc(1, sizeof *cache);
1534         if (!cache) {
1535 fail1:
1536                 free(cm3->dwt_comparator_list);
1537                 goto fail0;
1538         }
1539         cache->name = "cortex-m3 dwt registers";
1540         cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1541         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1542         if (!cache->reg_list) {
1543                 free(cache);
1544                 goto fail1;
1545         }
1546
1547         for (reg = 0; reg < 2; reg++)
1548                 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1549                                 dwt_base_regs + reg);
1550
1551         comparator = cm3->dwt_comparator_list;
1552         for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1553                 int j;
1554
1555                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1556                 for (j = 0; j < 3; j++, reg++)
1557                         cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1558                                         dwt_comp + 3 * i + j);
1559         }
1560
1561         *register_get_last_cache_p(&target->reg_cache) = cache;
1562         cm3->dwt_cache = cache;
1563
1564         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1565                         dwtcr, cm3->dwt_num_comp,
1566                         (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1567
1568         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1569          * implement single-address data value watchpoints ... so we
1570          * won't need to check it later, when asked to set one up.
1571          */
1572 }
1573
1574 static int cortex_m3_examine(struct target *target)
1575 {
1576         int retval;
1577         uint32_t cpuid, fpcr;
1578         int i;
1579         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1580         struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
1581
1582         if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1583                 return retval;
1584
1585         if (!target_was_examined(target))
1586         {
1587                 target_set_examined(target);
1588
1589                 /* Read from Device Identification Registers */
1590                 retval = target_read_u32(target, CPUID, &cpuid);
1591                 if (retval != ERROR_OK)
1592                         return retval;
1593
1594                 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1595                         LOG_DEBUG("CORTEX-M3 processor detected");
1596                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1597
1598                 /* NOTE: FPB and DWT are both optional. */
1599
1600                 /* Setup FPB */
1601                 target_read_u32(target, FP_CTRL, &fpcr);
1602                 cortex_m3->auto_bp_type = 1;
1603                 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1604                 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1605                 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1606                 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1607                 cortex_m3->fpb_enabled = fpcr & 1;
1608                 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1609                 {
1610                         cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1611                         cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1612                 }
1613                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1614
1615                 /* Setup DWT */
1616                 cortex_m3_dwt_setup(cortex_m3, target);
1617         }
1618
1619         return ERROR_OK;
1620 }
1621
1622 static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1623 {
1624         uint16_t dcrdr;
1625
1626         mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1627         *ctrl = (uint8_t)dcrdr;
1628         *value = (uint8_t)(dcrdr >> 8);
1629
1630         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1631
1632         /* write ack back to software dcc register
1633          * signify we have read data */
1634         if (dcrdr & (1 << 0))
1635         {
1636                 dcrdr = 0;
1637                 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1638         }
1639
1640         return ERROR_OK;
1641 }
1642
1643 static int cortex_m3_target_request_data(struct target *target,
1644                 uint32_t size, uint8_t *buffer)
1645 {
1646         struct armv7m_common *armv7m = target_to_armv7m(target);
1647         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1648         uint8_t data;
1649         uint8_t ctrl;
1650         uint32_t i;
1651
1652         for (i = 0; i < (size * 4); i++)
1653         {
1654                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1655                 buffer[i] = data;
1656         }
1657
1658         return ERROR_OK;
1659 }
1660
1661 static int cortex_m3_handle_target_request(void *priv)
1662 {
1663         struct target *target = priv;
1664         if (!target_was_examined(target))
1665                 return ERROR_OK;
1666         struct armv7m_common *armv7m = target_to_armv7m(target);
1667         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1668
1669         if (!target->dbg_msg_enabled)
1670                 return ERROR_OK;
1671
1672         if (target->state == TARGET_RUNNING)
1673         {
1674                 uint8_t data;
1675                 uint8_t ctrl;
1676
1677                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1678
1679                 /* check if we have data */
1680                 if (ctrl & (1 << 0))
1681                 {
1682                         uint32_t request;
1683
1684                         /* we assume target is quick enough */
1685                         request = data;
1686                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1687                         request |= (data << 8);
1688                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1689                         request |= (data << 16);
1690                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1691                         request |= (data << 24);
1692                         target_request(target, request);
1693                 }
1694         }
1695
1696         return ERROR_OK;
1697 }
1698
1699 static int cortex_m3_init_arch_info(struct target *target,
1700                 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1701 {
1702         int retval;
1703         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1704
1705         armv7m_init_arch_info(target, armv7m);
1706
1707         /* prepare JTAG information for the new target */
1708         cortex_m3->jtag_info.tap = tap;
1709         cortex_m3->jtag_info.scann_size = 4;
1710
1711         armv7m->swjdp_info.dp_select_value = -1;
1712         armv7m->swjdp_info.ap_csw_value = -1;
1713         armv7m->swjdp_info.ap_tar_value = -1;
1714         armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1715         armv7m->swjdp_info.memaccess_tck = 8;
1716         armv7m->swjdp_info.tar_autoincr_block = (1 << 12);      /* Cortex-M3 has 4096 bytes autoincrement range */
1717
1718         /* register arch-specific functions */
1719         armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1720
1721         armv7m->post_debug_entry = NULL;
1722
1723         armv7m->pre_restore_context = NULL;
1724         armv7m->post_restore_context = NULL;
1725
1726         armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1727         armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1728
1729         target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1730
1731         if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1732         {
1733                 return retval;
1734         }
1735
1736         return ERROR_OK;
1737 }
1738
1739 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1740 {
1741         struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1742
1743         cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1744         cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1745
1746         return ERROR_OK;
1747 }
1748
1749 /*--------------------------------------------------------------------------*/
1750
1751 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1752                 struct cortex_m3_common *cm3)
1753 {
1754         if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1755                 command_print(cmd_ctx, "target is not a Cortex-M3");
1756                 return ERROR_TARGET_INVALID;
1757         }
1758         return ERROR_OK;
1759 }
1760
1761 /*
1762  * Only stuff below this line should need to verify that its target
1763  * is a Cortex-M3.  Everything else should have indirected through the
1764  * cortexm3_target structure, which is only used with CM3 targets.
1765  */
1766
1767 /*
1768  * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1769  * as at least ARM-1156T2.  The interesting thing about Cortex-M is
1770  * that *only* Thumb2 disassembly matters.  There are also some small
1771  * additions to Thumb2 that are specific to ARMv7-M.
1772  */
1773 COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
1774 {
1775         int retval;
1776         struct target *target = get_current_target(CMD_CTX);
1777         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1778         uint32_t address;
1779         unsigned long count = 1;
1780         struct arm_instruction cur_instruction;
1781
1782         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1783         if (retval != ERROR_OK)
1784                 return retval;
1785
1786         errno = 0;
1787         switch (CMD_ARGC) {
1788         case 2:
1789                 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count);
1790                 /* FALL THROUGH */
1791         case 1:
1792                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1793                 break;
1794         default:
1795                 command_print(CMD_CTX,
1796                         "usage: cortex_m3 disassemble <address> [<count>]");
1797                 return ERROR_OK;
1798         }
1799
1800         while (count--) {
1801                 retval = thumb2_opcode(target, address, &cur_instruction);
1802                 if (retval != ERROR_OK)
1803                         return retval;
1804                 command_print(CMD_CTX, "%s", cur_instruction.text);
1805                 address += cur_instruction.instruction_size;
1806         }
1807
1808         return ERROR_OK;
1809 }
1810
1811 static const struct {
1812         char name[10];
1813         unsigned mask;
1814 } vec_ids[] = {
1815         { "hard_err",   VC_HARDERR, },
1816         { "int_err",    VC_INTERR, },
1817         { "bus_err",    VC_BUSERR, },
1818         { "state_err",  VC_STATERR, },
1819         { "chk_err",    VC_CHKERR, },
1820         { "nocp_err",   VC_NOCPERR, },
1821         { "mm_err",     VC_MMERR, },
1822         { "reset",      VC_CORERESET, },
1823 };
1824
1825 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1826 {
1827         struct target *target = get_current_target(CMD_CTX);
1828         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1829         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1830         struct swjdp_common *swjdp = &armv7m->swjdp_info;
1831         uint32_t demcr = 0;
1832         int retval;
1833
1834         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1835         if (retval != ERROR_OK)
1836                 return retval;
1837
1838         mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1839
1840         if (CMD_ARGC > 0) {
1841                 unsigned catch = 0;
1842
1843                 if (CMD_ARGC == 1) {
1844                         if (strcmp(CMD_ARGV[0], "all") == 0) {
1845                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1846                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
1847                                         | VC_MMERR | VC_CORERESET;
1848                                 goto write;
1849                         } else if (strcmp(CMD_ARGV[0], "none") == 0) {
1850                                 goto write;
1851                         }
1852                 }
1853                 while (CMD_ARGC-- > 0) {
1854                         unsigned i;
1855                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1856                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
1857                                         continue;
1858                                 catch |= vec_ids[i].mask;
1859                                 break;
1860                         }
1861                         if (i == ARRAY_SIZE(vec_ids)) {
1862                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
1863                                 return ERROR_INVALID_ARGUMENTS;
1864                         }
1865                 }
1866 write:
1867                 demcr &= ~0xffff;
1868                 demcr |= catch;
1869
1870                 /* write, but don't assume it stuck */
1871                 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
1872                 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1873         }
1874
1875         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
1876         {
1877                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
1878                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
1879         }
1880
1881         return ERROR_OK;
1882 }
1883
1884 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
1885 {
1886         struct target *target = get_current_target(CMD_CTX);
1887         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1888         int retval;
1889
1890         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1891         if (retval != ERROR_OK)
1892                 return retval;
1893
1894         if (target->state != TARGET_HALTED)
1895         {
1896                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1897                 return ERROR_OK;
1898         }
1899
1900         if (CMD_ARGC > 0)
1901         {
1902                 bool enable;
1903                 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
1904                 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
1905                 uint32_t mask_off = enable ? 0 : C_MASKINTS;
1906                 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
1907         }
1908
1909         command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
1910                         (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
1911
1912         return ERROR_OK;
1913 }
1914
1915 static int cortex_m3_register_commands(struct command_context *cmd_ctx)
1916 {
1917         int retval;
1918         struct command *cortex_m3_cmd;
1919
1920         retval = armv7m_register_commands(cmd_ctx);
1921
1922         cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3",
1923                         NULL, COMMAND_ANY, "cortex_m3 specific commands");
1924
1925         register_command(cmd_ctx, cortex_m3_cmd, "disassemble",
1926                         handle_cortex_m3_disassemble_command, COMMAND_EXEC,
1927                         "disassemble Thumb2 instructions <address> [<count>]");
1928         register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
1929                         handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC,
1930                         "mask cortex_m3 interrupts ['on'|'off']");
1931         register_command(cmd_ctx, cortex_m3_cmd, "vector_catch",
1932                         handle_cortex_m3_vector_catch_command, COMMAND_EXEC,
1933                         "catch hardware vectors ['all'|'none'|<list>]");
1934
1935         return retval;
1936 }
1937
1938 struct target_type cortexm3_target =
1939 {
1940         .name = "cortex_m3",
1941
1942         .poll = cortex_m3_poll,
1943         .arch_state = armv7m_arch_state,
1944
1945         .target_request_data = cortex_m3_target_request_data,
1946
1947         .halt = cortex_m3_halt,
1948         .resume = cortex_m3_resume,
1949         .step = cortex_m3_step,
1950
1951         .assert_reset = cortex_m3_assert_reset,
1952         .deassert_reset = cortex_m3_deassert_reset,
1953         .soft_reset_halt = cortex_m3_soft_reset_halt,
1954
1955         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
1956
1957         .read_memory = cortex_m3_read_memory,
1958         .write_memory = cortex_m3_write_memory,
1959         .bulk_write_memory = cortex_m3_bulk_write_memory,
1960         .checksum_memory = armv7m_checksum_memory,
1961         .blank_check_memory = armv7m_blank_check_memory,
1962
1963         .run_algorithm = armv7m_run_algorithm,
1964
1965         .add_breakpoint = cortex_m3_add_breakpoint,
1966         .remove_breakpoint = cortex_m3_remove_breakpoint,
1967         .add_watchpoint = cortex_m3_add_watchpoint,
1968         .remove_watchpoint = cortex_m3_remove_watchpoint,
1969
1970         .register_commands = cortex_m3_register_commands,
1971         .target_create = cortex_m3_target_create,
1972         .init_target = cortex_m3_init_target,
1973         .examine = cortex_m3_examine,
1974 };