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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "breakpoints.h"
  35 #include "cortex_m3.h"
  36 #include "target_request.h"
  37 #include "target_type.h"
  38 #include "arm_disassembler.h"
  39 #include "register.h"
  40 #include "arm_opcodes.h"
  41 #include "arm_semihosting.h"
  42
  43 /* NOTE:  most of this should work fine for the Cortex-M1 and
  44  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  45  * Some differences:  M0/M1 doesn't have FBP remapping or the
  46  * DWT tracing/profiling support.  (So the cycle counter will
  47  * not be usable; the other stuff isn't currently used here.)
  48  *
  49  * Although there are some workarounds for errata seen only in r0p0
  50  * silicon, such old parts are hard to find and thus not much tested
  51  * any longer.
  52  */
  53
  54
  55 /* forward declarations */
  56 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
  57 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
  58 static void cortex_m3_enable_watchpoints(struct target *target);
  59 static int cortex_m3_store_core_reg_u32(struct target *target,
  60                 enum armv7m_regtype type, uint32_t num, uint32_t value);
  61
  62 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
  63                 uint32_t *value, int regnum)
  64 {
  65         int retval;
  66         uint32_t dcrdr;
  67
  68         /* because the DCB_DCRDR is used for the emulated dcc channel
  69          * we have to save/restore the DCB_DCRDR when used */
  70
  71         retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  72         if (retval != ERROR_OK)
  73                 return retval;
  74
  75         /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  76         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  77         if (retval != ERROR_OK)
  78                 return retval;
  79         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  80         if (retval != ERROR_OK)
  81                 return retval;
  82
  83         /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  84         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  85         if (retval != ERROR_OK)
  86                 return retval;
  87         retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  88         if (retval != ERROR_OK)
  89                 return retval;
  90
  91         retval = dap_run(swjdp);
  92         if (retval != ERROR_OK)
  93                 return retval;
  94
  95         /* restore DCB_DCRDR - this needs to be in a seperate
  96          * transaction otherwise the emulated DCC channel breaks */
  97         if (retval == ERROR_OK)
  98                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  99
 100         return retval;
 101 }
 102
 103 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
 104                 uint32_t value, int regnum)
 105 {
 106         int retval;
 107         uint32_t dcrdr;
 108
 109         /* because the DCB_DCRDR is used for the emulated dcc channel
 110          * we have to save/restore the DCB_DCRDR when used */
 111
 112         retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 113         if (retval != ERROR_OK)
 114                 return retval;
 115
 116         /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
 117         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 118         if (retval != ERROR_OK)
 119                 return retval;
 120         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 121         // XXX check retval
 122
 123         /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
 124         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 125         if (retval != ERROR_OK)
 126                 return retval;
 127         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 128         // XXX check retval
 129
 130         retval = dap_run(swjdp);
 131
 132         /* restore DCB_DCRDR - this needs to be in a seperate
 133          * transaction otherwise the emulated DCC channel breaks */
 134         if (retval == ERROR_OK)
 135                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 136
 137         return retval;
 138 }
 139
 140 static int cortex_m3_write_debug_halt_mask(struct target *target,
 141                 uint32_t mask_on, uint32_t mask_off)
 142 {
 143         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 144         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 145
 146         /* mask off status bits */
 147         cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 148         /* create new register mask */
 149         cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 150
 151         return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
 152 }
 153
 154 static int cortex_m3_clear_halt(struct target *target)
 155 {
 156         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 157         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 158         int retval;
 159
 160         /* clear step if any */
 161         cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 162
 163         /* Read Debug Fault Status Register */
 164         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 165         if (retval != ERROR_OK)
 166                 return retval;
 167
 168         /* Clear Debug Fault Status */
 169         retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
 170         if (retval != ERROR_OK)
 171                 return retval;
 172         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 173
 174         return ERROR_OK;
 175 }
 176
 177 static int cortex_m3_single_step_core(struct target *target)
 178 {
 179         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 180         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 181         uint32_t dhcsr_save;
 182         int retval;
 183
 184         /* backup dhcsr reg */
 185         dhcsr_save = cortex_m3->dcb_dhcsr;
 186
 187         /* Mask interrupts before clearing halt, if done already.  This avoids
 188          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 189          * HALT can put the core into an unknown state.
 190          */
 191         if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
 192         {
 193                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 194                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 195                 if (retval != ERROR_OK)
 196                         return retval;
 197         }
 198         retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 199                                 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 200         if (retval != ERROR_OK)
 201                 return retval;
 202         LOG_DEBUG(" ");
 203
 204         /* restore dhcsr reg */
 205         cortex_m3->dcb_dhcsr = dhcsr_save;
 206         cortex_m3_clear_halt(target);
 207
 208         return ERROR_OK;
 209 }
 210
 211 static int cortex_m3_endreset_event(struct target *target)
 212 {
 213         int i;
 214         int retval;
 215         uint32_t dcb_demcr;
 216         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 217         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 218         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 219         struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 220         struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 221
 222         /* REVISIT The four debug monitor bits are currently ignored... */
 223         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 224         if (retval != ERROR_OK)
 225                 return retval;
 226         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 227
 228         /* this register is used for emulated dcc channel */
 229         retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 230         if (retval != ERROR_OK)
 231                 return retval;
 232
 233         /* Enable debug requests */
 234         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 235         if (retval != ERROR_OK)
 236                 return retval;
 237         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 238         {
 239                 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 240                 if (retval != ERROR_OK)
 241                         return retval;
 242         }
 243
 244         /* clear any interrupt masking */
 245         cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
 246
 247         /* Enable features controlled by ITM and DWT blocks, and catch only
 248          * the vectors we were told to pay attention to.
 249          *
 250          * Target firmware is responsible for all fault handling policy
 251          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 252          * or manual updates to the NVIC SHCSR and CCR registers.
 253          */
 254         retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
 255         if (retval != ERROR_OK)
 256                 return retval;
 257
 258         /* Paranoia: evidently some (early?) chips don't preserve all the
 259          * debug state (including FBP, DWT, etc) across reset...
 260          */
 261
 262         /* Enable FPB */
 263         retval = target_write_u32(target, FP_CTRL, 3);
 264         if (retval != ERROR_OK)
 265                 return retval;
 266
 267         cortex_m3->fpb_enabled = 1;
 268
 269         /* Restore FPB registers */
 270         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
 271         {
 272                 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 273                 if (retval != ERROR_OK)
 274                         return retval;
 275         }
 276
 277         /* Restore DWT registers */
 278         for (i = 0; i < cortex_m3->dwt_num_comp; i++)
 279         {
 280                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 281                                 dwt_list[i].comp);
 282                 if (retval != ERROR_OK)
 283                         return retval;
 284                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 285                                 dwt_list[i].mask);
 286                 if (retval != ERROR_OK)
 287                         return retval;
 288                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 289                                 dwt_list[i].function);
 290                 if (retval != ERROR_OK)
 291                         return retval;
 292         }
 293         retval = dap_run(swjdp);
 294         if (retval != ERROR_OK)
 295                 return retval;
 296
 297         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 298
 299         /* make sure we have latest dhcsr flags */
 300         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 301
 302         return retval;
 303 }
 304
 305 static int cortex_m3_examine_debug_reason(struct target *target)
 306 {
 307         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 308
 309         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
 310         /* only check the debug reason if we don't know it already */
 311
 312         if ((target->debug_reason != DBG_REASON_DBGRQ)
 313                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 314         {
 315                 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 316                 {
 317                         target->debug_reason = DBG_REASON_BREAKPOINT;
 318                         if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 319                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 320                 }
 321                 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 322                         target->debug_reason = DBG_REASON_WATCHPOINT;
 323                 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
 324                         target->debug_reason = DBG_REASON_BREAKPOINT;
 325                 else /* EXTERNAL, HALTED */
 326                         target->debug_reason = DBG_REASON_UNDEFINED;
 327         }
 328
 329         return ERROR_OK;
 330 }
 331
 332 static int cortex_m3_examine_exception_reason(struct target *target)
 333 {
 334         uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
 335         struct armv7m_common *armv7m = target_to_armv7m(target);
 336         struct adiv5_dap *swjdp = &armv7m->dap;
 337         int retval;
 338
 339         retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 340         if (retval != ERROR_OK)
 341                 return retval;
 342         switch (armv7m->exception_number)
 343         {
 344                 case 2: /* NMI */
 345                         break;
 346                 case 3: /* Hard Fault */
 347                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 348                         if (retval != ERROR_OK)
 349                                 return retval;
 350                         if (except_sr & 0x40000000)
 351                         {
 352                                 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
 353                                 if (retval != ERROR_OK)
 354                                         return retval;
 355                         }
 356                         break;
 357                 case 4: /* Memory Management */
 358                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 359                         if (retval != ERROR_OK)
 360                                 return retval;
 361                         retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
 362                         if (retval != ERROR_OK)
 363                                 return retval;
 364                         break;
 365                 case 5: /* Bus Fault */
 366                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 367                         if (retval != ERROR_OK)
 368                                 return retval;
 369                         retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
 370                         if (retval != ERROR_OK)
 371                                 return retval;
 372                         break;
 373                 case 6: /* Usage Fault */
 374                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 375                         if (retval != ERROR_OK)
 376                                 return retval;
 377                         break;
 378                 case 11:        /* SVCall */
 379                         break;
 380                 case 12:        /* Debug Monitor */
 381                         retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
 382                         if (retval != ERROR_OK)
 383                                 return retval;
 384                         break;
 385                 case 14:        /* PendSV */
 386                         break;
 387                 case 15:        /* SysTick */
 388                         break;
 389                 default:
 390                         except_sr = 0;
 391                         break;
 392         }
 393         retval = dap_run(swjdp);
 394         if (retval == ERROR_OK)
 395                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 396                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 397                         armv7m_exception_string(armv7m->exception_number),
 398                         shcsr, except_sr, cfsr, except_ar);
 399         return retval;
 400 }
 401
 402 /* PSP is used in some thread modes */
 403 static const int armv7m_psp_reg_map[17] = {
 404         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 405         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 406         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 407         ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
 408         ARMV7M_xPSR,
 409 };
 410
 411 /* MSP is used in handler and some thread modes */
 412 static const int armv7m_msp_reg_map[17] = {
 413         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 414         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 415         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 416         ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
 417         ARMV7M_xPSR,
 418 };
 419
 420 static int cortex_m3_debug_entry(struct target *target)
 421 {
 422         int i;
 423         uint32_t xPSR;
 424         int retval;
 425         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 426         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 427         struct arm *arm = &armv7m->arm;
 428         struct adiv5_dap *swjdp = &armv7m->dap;
 429         struct reg *r;
 430
 431         LOG_DEBUG(" ");
 432
 433         cortex_m3_clear_halt(target);
 434         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 435         if (retval != ERROR_OK)
 436                 return retval;
 437
 438         if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
 439                 return retval;
 440
 441         /* Examine target state and mode */
 442         /* First load register acessible through core debug port*/
 443         int num_regs = armv7m->core_cache->num_regs;
 444
 445         for (i = 0; i < num_regs; i++)
 446         {
 447                 if (!armv7m->core_cache->reg_list[i].valid)
 448                         armv7m->read_core_reg(target, i);
 449         }
 450
 451         r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 452         xPSR = buf_get_u32(r->value, 0, 32);
 453
 454 #ifdef ARMV7_GDB_HACKS
 455         /* FIXME this breaks on scan chains with more than one Cortex-M3.
 456          * Instead, each CM3 should have its own dummy value...
 457          */
 458         /* copy real xpsr reg for gdb, setting thumb bit */
 459         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
 460         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
 461         armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
 462         armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
 463 #endif
 464
 465         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 466         if (xPSR & 0xf00)
 467         {
 468                 r->dirty = r->valid;
 469                 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 470         }
 471
 472         /* Are we in an exception handler */
 473         if (xPSR & 0x1FF)
 474         {
 475                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 476                 armv7m->exception_number = (xPSR & 0x1FF);
 477
 478                 arm->core_mode = ARM_MODE_HANDLER;
 479                 arm->map = armv7m_msp_reg_map;
 480         }
 481         else
 482         {
 483                 unsigned control = buf_get_u32(armv7m->core_cache
 484                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 485
 486                 /* is this thread privileged? */
 487                 armv7m->core_mode = control & 1;
 488                 arm->core_mode = armv7m->core_mode
 489                                 ? ARM_MODE_USER_THREAD
 490                                 : ARM_MODE_THREAD;
 491
 492                 /* which stack is it using? */
 493                 if (control & 2)
 494                         arm->map = armv7m_psp_reg_map;
 495                 else
 496                         arm->map = armv7m_msp_reg_map;
 497
 498                 armv7m->exception_number = 0;
 499         }
 500
 501         if (armv7m->exception_number)
 502         {
 503                 cortex_m3_examine_exception_reason(target);
 504         }
 505
 506         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 507                 armv7m_mode_strings[armv7m->core_mode],
 508                 *(uint32_t*)(arm->pc->value),
 509                 target_state_name(target));
 510
 511         if (armv7m->post_debug_entry)
 512         {
 513                 retval = armv7m->post_debug_entry(target);
 514                 if (retval != ERROR_OK)
 515                         return retval;
 516         }
 517
 518         return ERROR_OK;
 519 }
 520
 521 static int cortex_m3_poll(struct target *target)
 522 {
 523         int retval;
 524         enum target_state prev_target_state = target->state;
 525         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 526         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 527
 528         /* Read from Debug Halting Control and Status Register */
 529         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 530         if (retval != ERROR_OK)
 531         {
 532                 target->state = TARGET_UNKNOWN;
 533                 return retval;
 534         }
 535
 536         /* Recover from lockup.  See ARMv7-M architecture spec,
 537          * section B1.5.15 "Unrecoverable exception cases".
 538          *
 539          * REVISIT Is there a better way to report and handle this?
 540          */
 541         if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
 542                 LOG_WARNING("%s -- clearing lockup after double fault",
 543                                 target_name(target));
 544                 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 545                 target->debug_reason = DBG_REASON_DBGRQ;
 546
 547                 /* refresh status bits */
 548                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 549                 if (retval != ERROR_OK)
 550                         return retval;
 551         }
 552
 553         if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 554         {
 555                 /* check if still in reset */
 556                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 557                 if (retval != ERROR_OK)
 558                         return retval;
 559
 560                 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 561                 {
 562                         target->state = TARGET_RESET;
 563                         return ERROR_OK;
 564                 }
 565         }
 566
 567         if (target->state == TARGET_RESET)
 568         {
 569                 /* Cannot switch context while running so endreset is
 570                  * called with target->state == TARGET_RESET
 571                  */
 572                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 573                                 cortex_m3->dcb_dhcsr);
 574                 cortex_m3_endreset_event(target);
 575                 target->state = TARGET_RUNNING;
 576                 prev_target_state = TARGET_RUNNING;
 577         }
 578
 579         if (cortex_m3->dcb_dhcsr & S_HALT)
 580         {
 581                 target->state = TARGET_HALTED;
 582
 583                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 584                 {
 585                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 586                                 return retval;
 587
 588                         if (arm_semihosting(target, &retval) != 0)
 589                                 return retval;
 590
 591                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 592                 }
 593                 if (prev_target_state == TARGET_DEBUG_RUNNING)
 594                 {
 595                         LOG_DEBUG(" ");
 596                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 597                                 return retval;
 598
 599                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 600                 }
 601         }
 602
 603         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 604          * How best to model low power modes?
 605          */
 606
 607         if (target->state == TARGET_UNKNOWN)
 608         {
 609                 /* check if processor is retiring instructions */
 610                 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
 611                 {
 612                         target->state = TARGET_RUNNING;
 613                         return ERROR_OK;
 614                 }
 615         }
 616
 617         return ERROR_OK;
 618 }
 619
 620 static int cortex_m3_halt(struct target *target)
 621 {
 622         LOG_DEBUG("target->state: %s",
 623                 target_state_name(target));
 624
 625         if (target->state == TARGET_HALTED)
 626         {
 627                 LOG_DEBUG("target was already halted");
 628                 return ERROR_OK;
 629         }
 630
 631         if (target->state == TARGET_UNKNOWN)
 632         {
 633                 LOG_WARNING("target was in unknown state when halt was requested");
 634         }
 635
 636         if (target->state == TARGET_RESET)
 637         {
 638                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
 639                 {
 640                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 641                         return ERROR_TARGET_FAILURE;
 642                 }
 643                 else
 644                 {
 645                         /* we came here in a reset_halt or reset_init sequence
 646                          * debug entry was already prepared in cortex_m3_prepare_reset_halt()
 647                          */
 648                         target->debug_reason = DBG_REASON_DBGRQ;
 649
 650                         return ERROR_OK;
 651                 }
 652         }
 653
 654         /* Write to Debug Halting Control and Status Register */
 655         cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 656
 657         target->debug_reason = DBG_REASON_DBGRQ;
 658
 659         return ERROR_OK;
 660 }
 661
 662 static int cortex_m3_soft_reset_halt(struct target *target)
 663 {
 664         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 665         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 666         uint32_t dcb_dhcsr = 0;
 667         int retval, timeout = 0;
 668
 669         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 670         retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
 671                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 672         if (retval != ERROR_OK)
 673                 return retval;
 674
 675         /* Request a core-only reset */
 676         retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 677                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 678         if (retval != ERROR_OK)
 679                 return retval;
 680         target->state = TARGET_RESET;
 681
 682         /* registers are now invalid */
 683         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 684
 685         while (timeout < 100)
 686         {
 687                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 688                 if (retval == ERROR_OK)
 689                 {
 690                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
 691                                         &cortex_m3->nvic_dfsr);
 692                         if (retval != ERROR_OK)
 693                                 return retval;
 694                         if ((dcb_dhcsr & S_HALT)
 695                                         && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 696                         {
 697                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 698                                         "DFSR 0x%08x",
 699                                         (unsigned) dcb_dhcsr,
 700                                         (unsigned) cortex_m3->nvic_dfsr);
 701                                 cortex_m3_poll(target);
 702                                 /* FIXME restore user's vector catch config */
 703                                 return ERROR_OK;
 704                         }
 705                         else
 706                                 LOG_DEBUG("waiting for system reset-halt, "
 707                                         "DHCSR 0x%08x, %d ms",
 708                                         (unsigned) dcb_dhcsr, timeout);
 709                 }
 710                 timeout++;
 711                 alive_sleep(1);
 712         }
 713
 714         return ERROR_OK;
 715 }
 716
 717 static void cortex_m3_enable_breakpoints(struct target *target)
 718 {
 719         struct breakpoint *breakpoint = target->breakpoints;
 720
 721         /* set any pending breakpoints */
 722         while (breakpoint)
 723         {
 724                 if (!breakpoint->set)
 725                         cortex_m3_set_breakpoint(target, breakpoint);
 726                 breakpoint = breakpoint->next;
 727         }
 728 }
 729
 730 static int cortex_m3_resume(struct target *target, int current,
 731                 uint32_t address, int handle_breakpoints, int debug_execution)
 732 {
 733         struct armv7m_common *armv7m = target_to_armv7m(target);
 734         struct breakpoint *breakpoint = NULL;
 735         uint32_t resume_pc;
 736         struct reg *r;
 737
 738         if (target->state != TARGET_HALTED)
 739         {
 740                 LOG_WARNING("target not halted");
 741                 return ERROR_TARGET_NOT_HALTED;
 742         }
 743
 744         if (!debug_execution)
 745         {
 746                 target_free_all_working_areas(target);
 747                 cortex_m3_enable_breakpoints(target);
 748                 cortex_m3_enable_watchpoints(target);
 749         }
 750
 751         if (debug_execution)
 752         {
 753                 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
 754
 755                 /* Disable interrupts */
 756                 /* We disable interrupts in the PRIMASK register instead of
 757                  * masking with C_MASKINTS.  This is probably the same issue
 758                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 759                  * in parallel with disabled interrupts can cause local faults
 760                  * to not be taken.
 761                  *
 762                  * REVISIT this clearly breaks non-debug execution, since the
 763                  * PRIMASK register state isn't saved/restored...  workaround
 764                  * by never resuming app code after debug execution.
 765                  */
 766                 buf_set_u32(r->value, 0, 1, 1);
 767                 r->dirty = true;
 768                 r->valid = true;
 769
 770                 /* Make sure we are in Thumb mode */
 771                 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 772                 buf_set_u32(r->value, 24, 1, 1);
 773                 r->dirty = true;
 774                 r->valid = true;
 775         }
 776
 777         /* current = 1: continue on current pc, otherwise continue at <address> */
 778         r = armv7m->arm.pc;
 779         if (!current)
 780         {
 781                 buf_set_u32(r->value, 0, 32, address);
 782                 r->dirty = true;
 783                 r->valid = true;
 784         }
 785
 786         /* if we halted last time due to a bkpt instruction
 787          * then we have to manually step over it, otherwise
 788          * the core will break again */
 789
 790         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 791                         && !debug_execution)
 792         {
 793                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 794         }
 795
 796         resume_pc = buf_get_u32(r->value, 0, 32);
 797
 798         armv7m_restore_context(target);
 799
 800         /* the front-end may request us not to handle breakpoints */
 801         if (handle_breakpoints)
 802         {
 803                 /* Single step past breakpoint at current address */
 804                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 805                 {
 806                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 807                                           breakpoint->address,
 808                                           breakpoint->unique_id);
 809                         cortex_m3_unset_breakpoint(target, breakpoint);
 810                         cortex_m3_single_step_core(target);
 811                         cortex_m3_set_breakpoint(target, breakpoint);
 812                 }
 813         }
 814
 815         /* Restart core */
 816         cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 817
 818         target->debug_reason = DBG_REASON_NOTHALTED;
 819
 820         /* registers are now invalid */
 821         register_cache_invalidate(armv7m->core_cache);
 822
 823         if (!debug_execution)
 824         {
 825                 target->state = TARGET_RUNNING;
 826                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 827                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 828         }
 829         else
 830         {
 831                 target->state = TARGET_DEBUG_RUNNING;
 832                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 833                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 834         }
 835
 836         return ERROR_OK;
 837 }
 838
 839 /* int irqstepcount = 0; */
 840 static int cortex_m3_step(struct target *target, int current,
 841                 uint32_t address, int handle_breakpoints)
 842 {
 843         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 844         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 845         struct adiv5_dap *swjdp = &armv7m->dap;
 846         struct breakpoint *breakpoint = NULL;
 847         struct reg *pc = armv7m->arm.pc;
 848         bool bkpt_inst_found = false;
 849
 850         if (target->state != TARGET_HALTED)
 851         {
 852                 LOG_WARNING("target not halted");
 853                 return ERROR_TARGET_NOT_HALTED;
 854         }
 855
 856         /* current = 1: continue on current pc, otherwise continue at <address> */
 857         if (!current)
 858                 buf_set_u32(pc->value, 0, 32, address);
 859
 860         /* the front-end may request us not to handle breakpoints */
 861         if (handle_breakpoints) {
 862                 breakpoint = breakpoint_find(target,
 863                                 buf_get_u32(pc->value, 0, 32));
 864                 if (breakpoint)
 865                         cortex_m3_unset_breakpoint(target, breakpoint);
 866         }
 867
 868         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 869
 870         target->debug_reason = DBG_REASON_SINGLESTEP;
 871
 872         armv7m_restore_context(target);
 873
 874         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 875
 876         /* if no bkpt instruction is found at pc then we can perform
 877          * a normal step, otherwise we have to manually step over the bkpt
 878          * instruction - as such simulate a step */
 879         if (bkpt_inst_found == false)
 880         {
 881                 /* set step and clear halt */
 882                 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 883         }
 884
 885         int retval;
 886         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 887         if (retval != ERROR_OK)
 888                 return retval;
 889
 890         /* registers are now invalid */
 891         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 892
 893         if (breakpoint)
 894                 cortex_m3_set_breakpoint(target, breakpoint);
 895
 896         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 897                         " nvic_icsr = 0x%" PRIx32,
 898                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 899
 900         retval = cortex_m3_debug_entry(target);
 901         if (retval != ERROR_OK)
 902                 return retval;
 903         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 904
 905         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 906                         " nvic_icsr = 0x%" PRIx32,
 907                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 908
 909         return ERROR_OK;
 910 }
 911
 912 static int cortex_m3_assert_reset(struct target *target)
 913 {
 914         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 915         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 916         enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
 917
 918         LOG_DEBUG("target->state: %s",
 919                 target_state_name(target));
 920
 921         enum reset_types jtag_reset_config = jtag_get_reset_config();
 922
 923         /*
 924          * We can reset Cortex-M3 targets using just the NVIC without
 925          * requiring SRST, getting a SoC reset (or a core-only reset)
 926          * instead of a system reset.
 927          */
 928         if (!(jtag_reset_config & RESET_HAS_SRST) &&
 929                         (cortex_m3->soft_reset_config == CORTEX_M3_RESET_SRST)) {
 930                 reset_config = CORTEX_M3_RESET_VECTRESET;
 931         }
 932
 933         /* Enable debug requests */
 934         int retval;
 935         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 936         if (retval != ERROR_OK)
 937                 return retval;
 938         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 939         {
 940                 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 941                 if (retval != ERROR_OK)
 942                         return retval;
 943         }
 944
 945         retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 946         if (retval != ERROR_OK)
 947                 return retval;
 948
 949         if (!target->reset_halt)
 950         {
 951                 /* Set/Clear C_MASKINTS in a separate operation */
 952                 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
 953                 {
 954                         retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 955                                         DBGKEY | C_DEBUGEN | C_HALT);
 956                         if (retval != ERROR_OK)
 957                                 return retval;
 958                 }
 959
 960                 /* clear any debug flags before resuming */
 961                 cortex_m3_clear_halt(target);
 962
 963                 /* clear C_HALT in dhcsr reg */
 964                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 965         }
 966         else
 967         {
 968                 /* Halt in debug on reset; endreset_event() restores DEMCR.
 969                  *
 970                  * REVISIT catching BUSERR presumably helps to defend against
 971                  * bad vector table entries.  Should this include MMERR or
 972                  * other flags too?
 973                  */
 974                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
 975                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 976                 if (retval != ERROR_OK)
 977                         return retval;
 978         }
 979
 980         if (reset_config == CORTEX_M3_RESET_SRST)
 981         {
 982                 /* default to asserting srst */
 983                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 984                 {
 985                         jtag_add_reset(1, 1);
 986                 }
 987                 else
 988                 {
 989                         jtag_add_reset(0, 1);
 990                 }
 991         }
 992         else
 993         {
 994                 /* Use a standard Cortex-M3 software reset mechanism.
 995                  * We default to using VECRESET as it is supported on all current cores.
 996                  * This has the disadvantage of not resetting the peripherals, so a
 997                  * reset-init event handler is needed to perform any peripheral resets.
 998                  */
 999                 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
1000                                 AIRCR_VECTKEY | ((reset_config == CORTEX_M3_RESET_SYSRESETREQ)
1001                                 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1002                 if (retval != ERROR_OK)
1003                         return retval;
1004
1005                 LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
1006                                 ? "SYSRESETREQ" : "VECTRESET");
1007
1008                 if (reset_config == CORTEX_M3_RESET_VECTRESET) {
1009                         LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
1010                                         "handler to reset any peripherals");
1011                 }
1012
1013                 {
1014                         /* I do not know why this is necessary, but it
1015                          * fixes strange effects (step/resume cause NMI
1016                          * after reset) on LM3S6918 -- Michael Schwingen
1017                          */
1018                         uint32_t tmp;
1019                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
1020                         if (retval != ERROR_OK)
1021                                 return retval;
1022                 }
1023         }
1024
1025         target->state = TARGET_RESET;
1026         jtag_add_sleep(50000);
1027
1028         register_cache_invalidate(cortex_m3->armv7m.core_cache);
1029
1030         if (target->reset_halt)
1031         {
1032                 if ((retval = target_halt(target)) != ERROR_OK)
1033                         return retval;
1034         }
1035
1036         return ERROR_OK;
1037 }
1038
1039 static int cortex_m3_deassert_reset(struct target *target)
1040 {
1041         LOG_DEBUG("target->state: %s",
1042                 target_state_name(target));
1043
1044         /* deassert reset lines */
1045         jtag_add_reset(0, 0);
1046
1047         return ERROR_OK;
1048 }
1049
1050 static int
1051 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1052 {
1053         int retval;
1054         int fp_num = 0;
1055         uint32_t hilo;
1056         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1057         struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
1058
1059         if (breakpoint->set)
1060         {
1061                 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
1062                 return ERROR_OK;
1063         }
1064
1065         if (cortex_m3->auto_bp_type)
1066         {
1067                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1068         }
1069
1070         if (breakpoint->type == BKPT_HARD)
1071         {
1072                 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
1073                         fp_num++;
1074                 if (fp_num >= cortex_m3->fp_num_code)
1075                 {
1076                         LOG_ERROR("Can not find free FPB Comparator!");
1077                         return ERROR_FAIL;
1078                 }
1079                 breakpoint->set = fp_num + 1;
1080                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1081                 comparator_list[fp_num].used = 1;
1082                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1083                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1084                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
1085                 if (!cortex_m3->fpb_enabled)
1086                 {
1087                         LOG_DEBUG("FPB wasn't enabled, do it now");
1088                         target_write_u32(target, FP_CTRL, 3);
1089                 }
1090         }
1091         else if (breakpoint->type == BKPT_SOFT)
1092         {
1093                 uint8_t code[4];
1094
1095                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1096                  * semihosting; don't use that.  Otherwise the BKPT
1097                  * parameter is arbitrary.
1098                  */
1099                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1100                 retval = target_read_memory(target,
1101                                 breakpoint->address & 0xFFFFFFFE,
1102                                 breakpoint->length, 1,
1103                                 breakpoint->orig_instr);
1104                 if (retval != ERROR_OK)
1105                         return retval;
1106                 retval = target_write_memory(target,
1107                                 breakpoint->address & 0xFFFFFFFE,
1108                                 breakpoint->length, 1,
1109                                 code);
1110                 if (retval != ERROR_OK)
1111                         return retval;
1112                 breakpoint->set = true;
1113         }
1114
1115         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1116                           breakpoint->unique_id,
1117                           (int)(breakpoint->type),
1118                           breakpoint->address,
1119                           breakpoint->length,
1120                           breakpoint->set);
1121
1122         return ERROR_OK;
1123 }
1124
1125 static int
1126 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1127 {
1128         int retval;
1129         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1130         struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
1131
1132         if (!breakpoint->set)
1133         {
1134                 LOG_WARNING("breakpoint not set");
1135                 return ERROR_OK;
1136         }
1137
1138         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1139                           breakpoint->unique_id,
1140                           (int)(breakpoint->type),
1141                           breakpoint->address,
1142                           breakpoint->length,
1143                           breakpoint->set);
1144
1145         if (breakpoint->type == BKPT_HARD)
1146         {
1147                 int fp_num = breakpoint->set - 1;
1148                 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
1149                 {
1150                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1151                         return ERROR_OK;
1152                 }
1153                 comparator_list[fp_num].used = 0;
1154                 comparator_list[fp_num].fpcr_value = 0;
1155                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1156         }
1157         else
1158         {
1159                 /* restore original instruction (kept in target endianness) */
1160                 if (breakpoint->length == 4)
1161                 {
1162                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1163                         {
1164                                 return retval;
1165                         }
1166                 }
1167                 else
1168                 {
1169                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1170                         {
1171                                 return retval;
1172                         }
1173                 }
1174         }
1175         breakpoint->set = false;
1176
1177         return ERROR_OK;
1178 }
1179
1180 static int
1181 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1182 {
1183         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1184
1185         if (cortex_m3->auto_bp_type)
1186         {
1187                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1188 #ifdef ARMV7_GDB_HACKS
1189                 if (breakpoint->length != 2) {
1190                         /* XXX Hack: Replace all breakpoints with length != 2 with
1191                          * a hardware breakpoint. */
1192                         breakpoint->type = BKPT_HARD;
1193                         breakpoint->length = 2;
1194                 }
1195 #endif
1196         }
1197
1198         if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
1199         {
1200                 LOG_INFO("flash patch comparator requested outside code memory region");
1201                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1202         }
1203
1204         if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
1205         {
1206                 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1207                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1208         }
1209
1210         if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1211         {
1212                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1213                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1214         }
1215
1216         if ((breakpoint->length != 2))
1217         {
1218                 LOG_INFO("only breakpoints of two bytes length supported");
1219                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1220         }
1221
1222         if (breakpoint->type == BKPT_HARD)
1223                 cortex_m3->fp_code_available--;
1224
1225         return cortex_m3_set_breakpoint(target, breakpoint);
1226 }
1227
1228 static int
1229 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1230 {
1231         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1232
1233         /* REVISIT why check? FBP can be updated with core running ... */
1234         if (target->state != TARGET_HALTED)
1235         {
1236                 LOG_WARNING("target not halted");
1237                 return ERROR_TARGET_NOT_HALTED;
1238         }
1239
1240         if (cortex_m3->auto_bp_type)
1241         {
1242                 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1243         }
1244
1245         if (breakpoint->set)
1246         {
1247                 cortex_m3_unset_breakpoint(target, breakpoint);
1248         }
1249
1250         if (breakpoint->type == BKPT_HARD)
1251                 cortex_m3->fp_code_available++;
1252
1253         return ERROR_OK;
1254 }
1255
1256 static int
1257 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1258 {
1259         int dwt_num = 0;
1260         uint32_t mask, temp;
1261         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1262
1263         /* watchpoint params were validated earlier */
1264         mask = 0;
1265         temp = watchpoint->length;
1266         while (temp) {
1267                 temp >>= 1;
1268                 mask++;
1269         }
1270         mask--;
1271
1272         /* REVISIT Don't fully trust these "not used" records ... users
1273          * may set up breakpoints by hand, e.g. dual-address data value
1274          * watchpoint using comparator #1; comparator #0 matching cycle
1275          * count; send data trace info through ITM and TPIU; etc
1276          */
1277         struct cortex_m3_dwt_comparator *comparator;
1278
1279         for (comparator = cortex_m3->dwt_comparator_list;
1280                         comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1281                         comparator++, dwt_num++)
1282                 continue;
1283         if (dwt_num >= cortex_m3->dwt_num_comp)
1284         {
1285                 LOG_ERROR("Can not find free DWT Comparator");
1286                 return ERROR_FAIL;
1287         }
1288         comparator->used = 1;
1289         watchpoint->set = dwt_num + 1;
1290
1291         comparator->comp = watchpoint->address;
1292         target_write_u32(target, comparator->dwt_comparator_address + 0,
1293                         comparator->comp);
1294
1295         comparator->mask = mask;
1296         target_write_u32(target, comparator->dwt_comparator_address + 4,
1297                         comparator->mask);
1298
1299         switch (watchpoint->rw) {
1300         case WPT_READ:
1301                 comparator->function = 5;
1302                 break;
1303         case WPT_WRITE:
1304                 comparator->function = 6;
1305                 break;
1306         case WPT_ACCESS:
1307                 comparator->function = 7;
1308                 break;
1309         }
1310         target_write_u32(target, comparator->dwt_comparator_address + 8,
1311                         comparator->function);
1312
1313         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1314                         watchpoint->unique_id, dwt_num,
1315                         (unsigned) comparator->comp,
1316                         (unsigned) comparator->mask,
1317                         (unsigned) comparator->function);
1318         return ERROR_OK;
1319 }
1320
1321 static int
1322 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1323 {
1324         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1325         struct cortex_m3_dwt_comparator *comparator;
1326         int dwt_num;
1327
1328         if (!watchpoint->set)
1329         {
1330                 LOG_WARNING("watchpoint (wpid: %d) not set",
1331                                 watchpoint->unique_id);
1332                 return ERROR_OK;
1333         }
1334
1335         dwt_num = watchpoint->set - 1;
1336
1337         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1338                         watchpoint->unique_id, dwt_num,
1339                         (unsigned) watchpoint->address);
1340
1341         if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1342         {
1343                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1344                 return ERROR_OK;
1345         }
1346
1347         comparator = cortex_m3->dwt_comparator_list + dwt_num;
1348         comparator->used = 0;
1349         comparator->function = 0;
1350         target_write_u32(target, comparator->dwt_comparator_address + 8,
1351                         comparator->function);
1352
1353         watchpoint->set = false;
1354
1355         return ERROR_OK;
1356 }
1357
1358 static int
1359 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1360 {
1361         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1362
1363         if (cortex_m3->dwt_comp_available < 1)
1364         {
1365                 LOG_DEBUG("no comparators?");
1366                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1367         }
1368
1369         /* hardware doesn't support data value masking */
1370         if (watchpoint->mask != ~(uint32_t)0) {
1371                 LOG_DEBUG("watchpoint value masks not supported");
1372                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1373         }
1374
1375         /* hardware allows address masks of up to 32K */
1376         unsigned mask;
1377
1378         for (mask = 0; mask < 16; mask++) {
1379                 if ((1u << mask) == watchpoint->length)
1380                         break;
1381         }
1382         if (mask == 16) {
1383                 LOG_DEBUG("unsupported watchpoint length");
1384                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1385         }
1386         if (watchpoint->address & ((1 << mask) - 1)) {
1387                 LOG_DEBUG("watchpoint address is unaligned");
1388                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1389         }
1390
1391         /* Caller doesn't seem to be able to describe watching for data
1392          * values of zero; that flags "no value".
1393          *
1394          * REVISIT This DWT may well be able to watch for specific data
1395          * values.  Requires comparator #1 to set DATAVMATCH and match
1396          * the data, and another comparator (DATAVADDR0) matching addr.
1397          */
1398         if (watchpoint->value) {
1399                 LOG_DEBUG("data value watchpoint not YET supported");
1400                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1401         }
1402
1403         cortex_m3->dwt_comp_available--;
1404         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1405
1406         return ERROR_OK;
1407 }
1408
1409 static int
1410 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1411 {
1412         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1413
1414         /* REVISIT why check? DWT can be updated with core running ... */
1415         if (target->state != TARGET_HALTED)
1416         {
1417                 LOG_WARNING("target not halted");
1418                 return ERROR_TARGET_NOT_HALTED;
1419         }
1420
1421         if (watchpoint->set)
1422         {
1423                 cortex_m3_unset_watchpoint(target, watchpoint);
1424         }
1425
1426         cortex_m3->dwt_comp_available++;
1427         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1428
1429         return ERROR_OK;
1430 }
1431
1432 static void cortex_m3_enable_watchpoints(struct target *target)
1433 {
1434         struct watchpoint *watchpoint = target->watchpoints;
1435
1436         /* set any pending watchpoints */
1437         while (watchpoint)
1438         {
1439                 if (!watchpoint->set)
1440                         cortex_m3_set_watchpoint(target, watchpoint);
1441                 watchpoint = watchpoint->next;
1442         }
1443 }
1444
1445 static int cortex_m3_load_core_reg_u32(struct target *target,
1446                 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1447 {
1448         int retval;
1449         struct armv7m_common *armv7m = target_to_armv7m(target);
1450         struct adiv5_dap *swjdp = &armv7m->dap;
1451
1452         /* NOTE:  we "know" here that the register identifiers used
1453          * in the v7m header match the Cortex-M3 Debug Core Register
1454          * Selector values for R0..R15, xPSR, MSP, and PSP.
1455          */
1456         switch (num) {
1457         case 0 ... 18:
1458                 /* read a normal core register */
1459                 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1460
1461                 if (retval != ERROR_OK)
1462                 {
1463                         LOG_ERROR("JTAG failure %i",retval);
1464                         return ERROR_JTAG_DEVICE_ERROR;
1465                 }
1466                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",(int)num,*value);
1467                 break;
1468
1469         case ARMV7M_PRIMASK:
1470         case ARMV7M_BASEPRI:
1471         case ARMV7M_FAULTMASK:
1472         case ARMV7M_CONTROL:
1473                 /* Cortex-M3 packages these four registers as bitfields
1474                  * in one Debug Core register.  So say r0 and r2 docs;
1475                  * it was removed from r1 docs, but still works.
1476                  */
1477                 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1478
1479                 switch (num)
1480                 {
1481                         case ARMV7M_PRIMASK:
1482                                 *value = buf_get_u32((uint8_t*)value, 0, 1);
1483                                 break;
1484
1485                         case ARMV7M_BASEPRI:
1486                                 *value = buf_get_u32((uint8_t*)value, 8, 8);
1487                                 break;
1488
1489                         case ARMV7M_FAULTMASK:
1490                                 *value = buf_get_u32((uint8_t*)value, 16, 1);
1491                                 break;
1492
1493                         case ARMV7M_CONTROL:
1494                                 *value = buf_get_u32((uint8_t*)value, 24, 2);
1495                                 break;
1496                 }
1497
1498                 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1499                 break;
1500
1501         default:
1502                 return ERROR_INVALID_ARGUMENTS;
1503         }
1504
1505         return ERROR_OK;
1506 }
1507
1508 static int cortex_m3_store_core_reg_u32(struct target *target,
1509                 enum armv7m_regtype type, uint32_t num, uint32_t value)
1510 {
1511         int retval;
1512         uint32_t reg;
1513         struct armv7m_common *armv7m = target_to_armv7m(target);
1514         struct adiv5_dap *swjdp = &armv7m->dap;
1515
1516 #ifdef ARMV7_GDB_HACKS
1517         /* If the LR register is being modified, make sure it will put us
1518          * in "thumb" mode, or an INVSTATE exception will occur. This is a
1519          * hack to deal with the fact that gdb will sometimes "forge"
1520          * return addresses, and doesn't set the LSB correctly (i.e., when
1521          * printing expressions containing function calls, it sets LR = 0.)
1522          * Valid exception return codes have bit 0 set too.
1523          */
1524         if (num == ARMV7M_R14)
1525                 value |= 0x01;
1526 #endif
1527
1528         /* NOTE:  we "know" here that the register identifiers used
1529          * in the v7m header match the Cortex-M3 Debug Core Register
1530          * Selector values for R0..R15, xPSR, MSP, and PSP.
1531          */
1532         switch (num) {
1533         case 0 ... 18:
1534                 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1535                 if (retval != ERROR_OK)
1536                 {
1537                         struct reg *r;
1538
1539                         LOG_ERROR("JTAG failure %i", retval);
1540                         r = armv7m->core_cache->reg_list + num;
1541                         r->dirty = r->valid;
1542                         return ERROR_JTAG_DEVICE_ERROR;
1543                 }
1544                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1545                 break;
1546
1547         case ARMV7M_PRIMASK:
1548         case ARMV7M_BASEPRI:
1549         case ARMV7M_FAULTMASK:
1550         case ARMV7M_CONTROL:
1551                 /* Cortex-M3 packages these four registers as bitfields
1552                  * in one Debug Core register.  So say r0 and r2 docs;
1553                  * it was removed from r1 docs, but still works.
1554                  */
1555                 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1556
1557                 switch (num)
1558                 {
1559                         case ARMV7M_PRIMASK:
1560                                 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1561                                 break;
1562
1563                         case ARMV7M_BASEPRI:
1564                                 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1565                                 break;
1566
1567                         case ARMV7M_FAULTMASK:
1568                                 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1569                                 break;
1570
1571                         case ARMV7M_CONTROL:
1572                                 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1573                                 break;
1574                 }
1575
1576                 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1577
1578                 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1579                 break;
1580
1581         default:
1582                 return ERROR_INVALID_ARGUMENTS;
1583         }
1584
1585         return ERROR_OK;
1586 }
1587
1588 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1589                 uint32_t size, uint32_t count, uint8_t *buffer)
1590 {
1591         struct armv7m_common *armv7m = target_to_armv7m(target);
1592         struct adiv5_dap *swjdp = &armv7m->dap;
1593         int retval = ERROR_INVALID_ARGUMENTS;
1594
1595         /* cortex_m3 handles unaligned memory access */
1596         if (count && buffer) {
1597                 switch (size) {
1598                 case 4:
1599                         retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1600                         break;
1601                 case 2:
1602                         retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1603                         break;
1604                 case 1:
1605                         retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1606                         break;
1607                 }
1608         }
1609
1610         return retval;
1611 }
1612
1613 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1614                 uint32_t size, uint32_t count, uint8_t *buffer)
1615 {
1616         struct armv7m_common *armv7m = target_to_armv7m(target);
1617         struct adiv5_dap *swjdp = &armv7m->dap;
1618         int retval = ERROR_INVALID_ARGUMENTS;
1619
1620         if (count && buffer) {
1621                 switch (size) {
1622                 case 4:
1623                         retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1624                         break;
1625                 case 2:
1626                         retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1627                         break;
1628                 case 1:
1629                         retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1630                         break;
1631                 }
1632         }
1633
1634         return retval;
1635 }
1636
1637 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1638                 uint32_t count, uint8_t *buffer)
1639 {
1640         return cortex_m3_write_memory(target, address, 4, count, buffer);
1641 }
1642
1643 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1644                 struct target *target)
1645 {
1646         armv7m_build_reg_cache(target);
1647         return ERROR_OK;
1648 }
1649
1650 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1651  * on r/w if the core is not running, and clear on resume or reset ... or
1652  * at least, in a post_restore_context() method.
1653  */
1654
1655 struct dwt_reg_state {
1656         struct target   *target;
1657         uint32_t        addr;
1658         uint32_t        value;  /* scratch/cache */
1659 };
1660
1661 static int cortex_m3_dwt_get_reg(struct reg *reg)
1662 {
1663         struct dwt_reg_state *state = reg->arch_info;
1664
1665         return target_read_u32(state->target, state->addr, &state->value);
1666 }
1667
1668 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1669 {
1670         struct dwt_reg_state *state = reg->arch_info;
1671
1672         return target_write_u32(state->target, state->addr,
1673                         buf_get_u32(buf, 0, reg->size));
1674 }
1675
1676 struct dwt_reg {
1677         uint32_t        addr;
1678         char            *name;
1679         unsigned        size;
1680 };
1681
1682 static struct dwt_reg dwt_base_regs[] = {
1683         { DWT_CTRL, "dwt_ctrl", 32, },
1684         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1685          * increments while the core is asleep.
1686          */
1687         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1688         /* plus some 8 bit counters, useful for profiling with TPIU */
1689 };
1690
1691 static struct dwt_reg dwt_comp[] = {
1692 #define DWT_COMPARATOR(i) \
1693                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1694                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1695                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1696         DWT_COMPARATOR(0),
1697         DWT_COMPARATOR(1),
1698         DWT_COMPARATOR(2),
1699         DWT_COMPARATOR(3),
1700 #undef DWT_COMPARATOR
1701 };
1702
1703 static const struct reg_arch_type dwt_reg_type = {
1704         .get = cortex_m3_dwt_get_reg,
1705         .set = cortex_m3_dwt_set_reg,
1706 };
1707
1708 static void
1709 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1710 {
1711         struct dwt_reg_state *state;
1712
1713         state = calloc(1, sizeof *state);
1714         if (!state)
1715                 return;
1716         state->addr = d->addr;
1717         state->target = t;
1718
1719         r->name = d->name;
1720         r->size = d->size;
1721         r->value = &state->value;
1722         r->arch_info = state;
1723         r->type = &dwt_reg_type;
1724 }
1725
1726 static void
1727 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1728 {
1729         uint32_t dwtcr;
1730         struct reg_cache *cache;
1731         struct cortex_m3_dwt_comparator *comparator;
1732         int reg, i;
1733
1734         target_read_u32(target, DWT_CTRL, &dwtcr);
1735         if (!dwtcr) {
1736                 LOG_DEBUG("no DWT");
1737                 return;
1738         }
1739
1740         cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1741         cm3->dwt_comp_available = cm3->dwt_num_comp;
1742         cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1743                         sizeof(struct cortex_m3_dwt_comparator));
1744         if (!cm3->dwt_comparator_list) {
1745 fail0:
1746                 cm3->dwt_num_comp = 0;
1747                 LOG_ERROR("out of mem");
1748                 return;
1749         }
1750
1751         cache = calloc(1, sizeof *cache);
1752         if (!cache) {
1753 fail1:
1754                 free(cm3->dwt_comparator_list);
1755                 goto fail0;
1756         }
1757         cache->name = "cortex-m3 dwt registers";
1758         cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1759         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1760         if (!cache->reg_list) {
1761                 free(cache);
1762                 goto fail1;
1763         }
1764
1765         for (reg = 0; reg < 2; reg++)
1766                 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1767                                 dwt_base_regs + reg);
1768
1769         comparator = cm3->dwt_comparator_list;
1770         for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1771                 int j;
1772
1773                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1774                 for (j = 0; j < 3; j++, reg++)
1775                         cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1776                                         dwt_comp + 3 * i + j);
1777         }
1778
1779         *register_get_last_cache_p(&target->reg_cache) = cache;
1780         cm3->dwt_cache = cache;
1781
1782         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1783                         dwtcr, cm3->dwt_num_comp,
1784                         (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1785
1786         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1787          * implement single-address data value watchpoints ... so we
1788          * won't need to check it later, when asked to set one up.
1789          */
1790 }
1791
1792 static int cortex_m3_examine(struct target *target)
1793 {
1794         int retval;
1795         uint32_t cpuid, fpcr;
1796         int i;
1797         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1798         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
1799
1800         if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1801                 return retval;
1802
1803         if (!target_was_examined(target))
1804         {
1805                 target_set_examined(target);
1806
1807                 /* Read from Device Identification Registers */
1808                 retval = target_read_u32(target, CPUID, &cpuid);
1809                 if (retval != ERROR_OK)
1810                         return retval;
1811
1812                 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1813                         LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
1814                                 (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1815                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1816
1817                 /* NOTE: FPB and DWT are both optional. */
1818
1819                 /* Setup FPB */
1820                 target_read_u32(target, FP_CTRL, &fpcr);
1821                 cortex_m3->auto_bp_type = 1;
1822                 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1823                 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1824                 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1825                 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1826                 cortex_m3->fpb_enabled = fpcr & 1;
1827                 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1828                 {
1829                         cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1830                         cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1831                 }
1832                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1833
1834                 /* Setup DWT */
1835                 cortex_m3_dwt_setup(cortex_m3, target);
1836
1837                 /* These hardware breakpoints only work for code in flash! */
1838                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1839                                 target_name(target),
1840                                 cortex_m3->fp_num_code,
1841                                 cortex_m3->dwt_num_comp);
1842         }
1843
1844         return ERROR_OK;
1845 }
1846
1847 static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
1848 {
1849         uint16_t dcrdr;
1850         int retval;
1851
1852         mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1853         *ctrl = (uint8_t)dcrdr;
1854         *value = (uint8_t)(dcrdr >> 8);
1855
1856         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1857
1858         /* write ack back to software dcc register
1859          * signify we have read data */
1860         if (dcrdr & (1 << 0))
1861         {
1862                 dcrdr = 0;
1863                 retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1864                 if (retval != ERROR_OK)
1865                         return retval;
1866         }
1867
1868         return ERROR_OK;
1869 }
1870
1871 static int cortex_m3_target_request_data(struct target *target,
1872                 uint32_t size, uint8_t *buffer)
1873 {
1874         struct armv7m_common *armv7m = target_to_armv7m(target);
1875         struct adiv5_dap *swjdp = &armv7m->dap;
1876         uint8_t data;
1877         uint8_t ctrl;
1878         uint32_t i;
1879
1880         for (i = 0; i < (size * 4); i++)
1881         {
1882                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1883                 buffer[i] = data;
1884         }
1885
1886         return ERROR_OK;
1887 }
1888
1889 static int cortex_m3_handle_target_request(void *priv)
1890 {
1891         struct target *target = priv;
1892         if (!target_was_examined(target))
1893                 return ERROR_OK;
1894         struct armv7m_common *armv7m = target_to_armv7m(target);
1895         struct adiv5_dap *swjdp = &armv7m->dap;
1896
1897         if (!target->dbg_msg_enabled)
1898                 return ERROR_OK;
1899
1900         if (target->state == TARGET_RUNNING)
1901         {
1902                 uint8_t data;
1903                 uint8_t ctrl;
1904
1905                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1906
1907                 /* check if we have data */
1908                 if (ctrl & (1 << 0))
1909                 {
1910                         uint32_t request;
1911
1912                         /* we assume target is quick enough */
1913                         request = data;
1914                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1915                         request |= (data << 8);
1916                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1917                         request |= (data << 16);
1918                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1919                         request |= (data << 24);
1920                         target_request(target, request);
1921                 }
1922         }
1923
1924         return ERROR_OK;
1925 }
1926
1927 static int cortex_m3_init_arch_info(struct target *target,
1928                 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1929 {
1930         int retval;
1931         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1932
1933         armv7m_init_arch_info(target, armv7m);
1934
1935         /* prepare JTAG information for the new target */
1936         cortex_m3->jtag_info.tap = tap;
1937         cortex_m3->jtag_info.scann_size = 4;
1938
1939         /* default reset mode is to use srst if fitted
1940          * if not it will use CORTEX_M3_RESET_VECTRESET */
1941         cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST;
1942
1943         armv7m->arm.dap = &armv7m->dap;
1944
1945         /* Leave (only) generic DAP stuff for debugport_init(); */
1946         armv7m->dap.jtag_info = &cortex_m3->jtag_info;
1947         armv7m->dap.memaccess_tck = 8;
1948         /* Cortex-M3 has 4096 bytes autoincrement range */
1949         armv7m->dap.tar_autoincr_block = (1 << 12);
1950
1951         /* register arch-specific functions */
1952         armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1953
1954         armv7m->post_debug_entry = NULL;
1955
1956         armv7m->pre_restore_context = NULL;
1957
1958         armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1959         armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1960
1961         target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1962
1963         if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1964         {
1965                 return retval;
1966         }
1967
1968         return ERROR_OK;
1969 }
1970
1971 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1972 {
1973         struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1974
1975         cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1976         cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1977
1978         return ERROR_OK;
1979 }
1980
1981 /*--------------------------------------------------------------------------*/
1982
1983 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1984                 struct cortex_m3_common *cm3)
1985 {
1986         if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1987                 command_print(cmd_ctx, "target is not a Cortex-M3");
1988                 return ERROR_TARGET_INVALID;
1989         }
1990         return ERROR_OK;
1991 }
1992
1993 /*
1994  * Only stuff below this line should need to verify that its target
1995  * is a Cortex-M3.  Everything else should have indirected through the
1996  * cortexm3_target structure, which is only used with CM3 targets.
1997  */
1998
1999 static const struct {
2000         char name[10];
2001         unsigned mask;
2002 } vec_ids[] = {
2003         { "hard_err",   VC_HARDERR, },
2004         { "int_err",    VC_INTERR, },
2005         { "bus_err",    VC_BUSERR, },
2006         { "state_err",  VC_STATERR, },
2007         { "chk_err",    VC_CHKERR, },
2008         { "nocp_err",   VC_NOCPERR, },
2009         { "mm_err",     VC_MMERR, },
2010         { "reset",      VC_CORERESET, },
2011 };
2012
2013 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
2014 {
2015         struct target *target = get_current_target(CMD_CTX);
2016         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2017         struct armv7m_common *armv7m = &cortex_m3->armv7m;
2018         struct adiv5_dap *swjdp = &armv7m->dap;
2019         uint32_t demcr = 0;
2020         int retval;
2021
2022         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2023         if (retval != ERROR_OK)
2024                 return retval;
2025
2026         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2027         if (retval != ERROR_OK)
2028                 return retval;
2029
2030         if (CMD_ARGC > 0) {
2031                 unsigned catch = 0;
2032
2033                 if (CMD_ARGC == 1) {
2034                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2035                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2036                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2037                                         | VC_MMERR | VC_CORERESET;
2038                                 goto write;
2039                         } else if (strcmp(CMD_ARGV[0], "none") == 0) {
2040                                 goto write;
2041                         }
2042                 }
2043                 while (CMD_ARGC-- > 0) {
2044                         unsigned i;
2045                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2046                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2047                                         continue;
2048                                 catch |= vec_ids[i].mask;
2049                                 break;
2050                         }
2051                         if (i == ARRAY_SIZE(vec_ids)) {
2052                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2053                                 return ERROR_INVALID_ARGUMENTS;
2054                         }
2055                 }
2056 write:
2057                 /* For now, armv7m->demcr only stores vector catch flags. */
2058                 armv7m->demcr = catch;
2059
2060                 demcr &= ~0xffff;
2061                 demcr |= catch;
2062
2063                 /* write, but don't assume it stuck (why not??) */
2064                 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2065                 if (retval != ERROR_OK)
2066                         return retval;
2067                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2068                 if (retval != ERROR_OK)
2069                         return retval;
2070
2071                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2072                  * Otherwise the vector catch hardware could fire when there's
2073                  * no debugger hooked up, causing much confusion...
2074                  */
2075         }
2076
2077         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
2078         {
2079                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2080                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2081         }
2082
2083         return ERROR_OK;
2084 }
2085
2086 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
2087 {
2088         struct target *target = get_current_target(CMD_CTX);
2089         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2090         int retval;
2091
2092         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2093         if (retval != ERROR_OK)
2094                 return retval;
2095
2096         if (target->state != TARGET_HALTED)
2097         {
2098                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2099                 return ERROR_OK;
2100         }
2101
2102         if (CMD_ARGC > 0)
2103         {
2104                 bool enable;
2105                 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
2106                 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
2107                 uint32_t mask_off = enable ? 0 : C_MASKINTS;
2108                 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
2109         }
2110
2111         command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
2112                         (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
2113
2114         return ERROR_OK;
2115 }
2116
2117 COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
2118 {
2119         struct target *target = get_current_target(CMD_CTX);
2120         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2121         int retval;
2122         char *reset_config;
2123
2124         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2125         if (retval != ERROR_OK)
2126                 return retval;
2127
2128         if (CMD_ARGC > 0)
2129         {
2130                 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2131                         cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
2132                 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2133                         cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
2134                 else
2135                         cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST;
2136         }
2137
2138         switch (cortex_m3->soft_reset_config)
2139         {
2140                 case CORTEX_M3_RESET_SRST:
2141                         reset_config = "srst";
2142                         break;
2143
2144                 case CORTEX_M3_RESET_SYSRESETREQ:
2145                         reset_config = "sysresetreq";
2146                         break;
2147
2148                 case CORTEX_M3_RESET_VECTRESET:
2149                         reset_config = "vectreset";
2150                         break;
2151
2152                 default:
2153                         reset_config = "unknown";
2154                         break;
2155         }
2156
2157         command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
2158
2159         return ERROR_OK;
2160 }
2161
2162 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2163         {
2164                 .name = "maskisr",
2165                 .handler = handle_cortex_m3_mask_interrupts_command,
2166                 .mode = COMMAND_EXEC,
2167                 .help = "mask cortex_m3 interrupts",
2168                 .usage = "['on'|'off']",
2169         },
2170         {
2171                 .name = "vector_catch",
2172                 .handler = handle_cortex_m3_vector_catch_command,
2173                 .mode = COMMAND_EXEC,
2174                 .help = "configure hardware vectors to trigger debug entry",
2175                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2176         },
2177         {
2178                 .name = "reset_config",
2179                 .handler = handle_cortex_m3_reset_config_command,
2180                 .mode = COMMAND_ANY,
2181                 .help = "configure software reset handling",
2182                 .usage = "['srst'|'sysresetreq'|'vectreset']",
2183         },
2184         COMMAND_REGISTRATION_DONE
2185 };
2186 static const struct command_registration cortex_m3_command_handlers[] = {
2187         {
2188                 .chain = armv7m_command_handlers,
2189         },
2190         {
2191                 .name = "cortex_m3",
2192                 .mode = COMMAND_EXEC,
2193                 .help = "Cortex-M3 command group",
2194                 .chain = cortex_m3_exec_command_handlers,
2195         },
2196         COMMAND_REGISTRATION_DONE
2197 };
2198
2199 struct target_type cortexm3_target =
2200 {
2201         .name = "cortex_m3",
2202
2203         .poll = cortex_m3_poll,
2204         .arch_state = armv7m_arch_state,
2205
2206         .target_request_data = cortex_m3_target_request_data,
2207
2208         .halt = cortex_m3_halt,
2209         .resume = cortex_m3_resume,
2210         .step = cortex_m3_step,
2211
2212         .assert_reset = cortex_m3_assert_reset,
2213         .deassert_reset = cortex_m3_deassert_reset,
2214         .soft_reset_halt = cortex_m3_soft_reset_halt,
2215
2216         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2217
2218         .read_memory = cortex_m3_read_memory,
2219         .write_memory = cortex_m3_write_memory,
2220         .bulk_write_memory = cortex_m3_bulk_write_memory,
2221         .checksum_memory = armv7m_checksum_memory,
2222         .blank_check_memory = armv7m_blank_check_memory,
2223
2224         .run_algorithm = armv7m_run_algorithm,
2225
2226         .add_breakpoint = cortex_m3_add_breakpoint,
2227         .remove_breakpoint = cortex_m3_remove_breakpoint,
2228         .add_watchpoint = cortex_m3_add_watchpoint,
2229         .remove_watchpoint = cortex_m3_remove_watchpoint,
2230
2231         .commands = cortex_m3_command_handlers,
2232         .target_create = cortex_m3_target_create,
2233         .init_target = cortex_m3_init_target,
2234         .examine = cortex_m3_examine,
2235 };