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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifndef OPENOCD_TARGET_CORTEX_M_H
  26 #define OPENOCD_TARGET_CORTEX_M_H
  27
  28 #include "armv7m.h"
  29 #include "helper/bits.h"
  30
  31 #define CORTEX_M_COMMON_MAGIC 0x1A451A45
  32
  33 #define SYSTEM_CONTROL_BASE 0x400FE000
  34
  35 #define ITM_TER0        0xE0000E00
  36 #define ITM_TPR         0xE0000E40
  37 #define ITM_TCR         0xE0000E80
  38 #define ITM_LAR         0xE0000FB0
  39 #define ITM_LAR_KEY     0xC5ACCE55
  40
  41 #define CPUID           0xE000ED00
  42
  43 #define ARM_CPUID_PARTNO_MASK   0xFFF0
  44
  45 #define CORTEX_M23_PARTNO       0xD200
  46 #define CORTEX_M33_PARTNO       0xD210
  47 #define CORTEX_M35P_PARTNO      0xD310
  48 #define CORTEX_M55_PARTNO       0xD220
  49
  50 /* Debug Control Block */
  51 #define DCB_DHCSR       0xE000EDF0
  52 #define DCB_DCRSR       0xE000EDF4
  53 #define DCB_DCRDR       0xE000EDF8
  54 #define DCB_DEMCR       0xE000EDFC
  55 #define DCB_DSCSR       0xE000EE08
  56
  57 #define DCRSR_WnR       BIT(16)
  58
  59 #define DWT_CTRL        0xE0001000
  60 #define DWT_CYCCNT      0xE0001004
  61 #define DWT_PCSR        0xE000101C
  62 #define DWT_COMP0       0xE0001020
  63 #define DWT_MASK0       0xE0001024
  64 #define DWT_FUNCTION0   0xE0001028
  65 #define DWT_DEVARCH             0xE0001FBC
  66
  67 #define DWT_DEVARCH_ARMV8M      0x101A02
  68
  69 #define FP_CTRL         0xE0002000
  70 #define FP_REMAP        0xE0002004
  71 #define FP_COMP0        0xE0002008
  72 #define FP_COMP1        0xE000200C
  73 #define FP_COMP2        0xE0002010
  74 #define FP_COMP3        0xE0002014
  75 #define FP_COMP4        0xE0002018
  76 #define FP_COMP5        0xE000201C
  77 #define FP_COMP6        0xE0002020
  78 #define FP_COMP7        0xE0002024
  79
  80 #define FPU_CPACR       0xE000ED88
  81 #define FPU_FPCCR       0xE000EF34
  82 #define FPU_FPCAR       0xE000EF38
  83 #define FPU_FPDSCR      0xE000EF3C
  84
  85 #define TPIU_SSPSR      0xE0040000
  86 #define TPIU_CSPSR      0xE0040004
  87 #define TPIU_ACPR       0xE0040010
  88 #define TPIU_SPPR       0xE00400F0
  89 #define TPIU_FFSR       0xE0040300
  90 #define TPIU_FFCR       0xE0040304
  91 #define TPIU_FSCR       0xE0040308
  92
  93 /* Maximum SWO prescaler value. */
  94 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
  95
  96 /* DCB_DHCSR bit and field definitions */
  97 #define DBGKEY          (0xA05Ful << 16)
  98 #define C_DEBUGEN       BIT(0)
  99 #define C_HALT          BIT(1)
 100 #define C_STEP          BIT(2)
 101 #define C_MASKINTS      BIT(3)
 102 #define S_REGRDY        BIT(16)
 103 #define S_HALT          BIT(17)
 104 #define S_SLEEP         BIT(18)
 105 #define S_LOCKUP        BIT(19)
 106 #define S_RETIRE_ST     BIT(24)
 107 #define S_RESET_ST      BIT(25)
 108
 109 /* DCB_DEMCR bit and field definitions */
 110 #define TRCENA                  BIT(24)
 111 #define VC_HARDERR              BIT(10)
 112 #define VC_INTERR               BIT(9)
 113 #define VC_BUSERR               BIT(8)
 114 #define VC_STATERR              BIT(7)
 115 #define VC_CHKERR               BIT(6)
 116 #define VC_NOCPERR              BIT(5)
 117 #define VC_MMERR                BIT(4)
 118 #define VC_CORERESET    BIT(0)
 119
 120 /* DCB_DSCSR bit and field definitions */
 121 #define DSCSR_CDS               BIT(16)
 122
 123 /* NVIC registers */
 124 #define NVIC_ICTR               0xE000E004
 125 #define NVIC_ISE0               0xE000E100
 126 #define NVIC_ICSR               0xE000ED04
 127 #define NVIC_AIRCR              0xE000ED0C
 128 #define NVIC_SHCSR              0xE000ED24
 129 #define NVIC_CFSR               0xE000ED28
 130 #define NVIC_MMFSRb             0xE000ED28
 131 #define NVIC_BFSRb              0xE000ED29
 132 #define NVIC_USFSRh             0xE000ED2A
 133 #define NVIC_HFSR               0xE000ED2C
 134 #define NVIC_DFSR               0xE000ED30
 135 #define NVIC_MMFAR              0xE000ED34
 136 #define NVIC_BFAR               0xE000ED38
 137 #define NVIC_SFSR               0xE000EDE4
 138 #define NVIC_SFAR               0xE000EDE8
 139
 140 /* NVIC_AIRCR bits */
 141 #define AIRCR_VECTKEY           (0x5FAul << 16)
 142 #define AIRCR_SYSRESETREQ       BIT(2)
 143 #define AIRCR_VECTCLRACTIVE     BIT(1)
 144 #define AIRCR_VECTRESET         BIT(0)
 145 /* NVIC_SHCSR bits */
 146 #define SHCSR_BUSFAULTENA       BIT(17)
 147 /* NVIC_DFSR bits */
 148 #define DFSR_HALTED                     1
 149 #define DFSR_BKPT                       2
 150 #define DFSR_DWTTRAP            4
 151 #define DFSR_VCATCH                     8
 152 #define DFSR_EXTERNAL           16
 153
 154 #define FPCR_CODE 0
 155 #define FPCR_LITERAL 1
 156 #define FPCR_REPLACE_REMAP  (0ul << 30)
 157 #define FPCR_REPLACE_BKPT_LOW  (1ul << 30)
 158 #define FPCR_REPLACE_BKPT_HIGH  (2ul << 30)
 159 #define FPCR_REPLACE_BKPT_BOTH  (3ul << 30)
 160
 161 struct cortex_m_fp_comparator {
 162         bool used;
 163         int type;
 164         uint32_t fpcr_value;
 165         uint32_t fpcr_address;
 166 };
 167
 168 struct cortex_m_dwt_comparator {
 169         bool used;
 170         uint32_t comp;
 171         uint32_t mask;
 172         uint32_t function;
 173         uint32_t dwt_comparator_address;
 174 };
 175
 176 enum cortex_m_soft_reset_config {
 177         CORTEX_M_RESET_SYSRESETREQ,
 178         CORTEX_M_RESET_VECTRESET,
 179 };
 180
 181 enum cortex_m_isrmasking_mode {
 182         CORTEX_M_ISRMASK_AUTO,
 183         CORTEX_M_ISRMASK_OFF,
 184         CORTEX_M_ISRMASK_ON,
 185         CORTEX_M_ISRMASK_STEPONLY,
 186 };
 187
 188 struct cortex_m_common {
 189         int common_magic;
 190
 191         /* Context information */
 192         uint32_t dcb_dhcsr;
 193         uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
 194         uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
 195
 196         /* Flash Patch and Breakpoint (FPB) */
 197         int fp_num_lit;
 198         int fp_num_code;
 199         int fp_rev;
 200         bool fpb_enabled;
 201         struct cortex_m_fp_comparator *fp_comparator_list;
 202
 203         /* Data Watchpoint and Trace (DWT) */
 204         int dwt_num_comp;
 205         int dwt_comp_available;
 206         uint32_t dwt_devarch;
 207         struct cortex_m_dwt_comparator *dwt_comparator_list;
 208         struct reg_cache *dwt_cache;
 209
 210         enum cortex_m_soft_reset_config soft_reset_config;
 211         bool vectreset_supported;
 212
 213         enum cortex_m_isrmasking_mode isrmasking_mode;
 214
 215         struct armv7m_common armv7m;
 216
 217         int apsel;
 218
 219         /* Whether this target has the erratum that makes C_MASKINTS not apply to
 220          * already pending interrupts */
 221         bool maskints_erratum;
 222 };
 223
 224 static inline struct cortex_m_common *
 225 target_to_cm(struct target *target)
 226 {
 227         return container_of(target->arch_info,
 228                         struct cortex_m_common, armv7m);
 229 }
 230
 231 int cortex_m_examine(struct target *target);
 232 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
 233 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
 234 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
 235 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
 236 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
 237 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
 238 void cortex_m_enable_breakpoints(struct target *target);
 239 void cortex_m_enable_watchpoints(struct target *target);
 240 void cortex_m_deinit_target(struct target *target);
 241 int cortex_m_profiling(struct target *target, uint32_t *samples,
 242         uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
 243
 244 #endif /* OPENOCD_TARGET_CORTEX_M_H */