1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
7 * Copyright (C) 2006 by Magnus Lundin *
10 * Copyright (C) 2008 by Spencer Oliver *
11 * spen@spen-soft.co.uk *
12 ***************************************************************************/
14 #ifndef OPENOCD_TARGET_CORTEX_M_H
15 #define OPENOCD_TARGET_CORTEX_M_H
18 #include "helper/bits.h"
20 #define CORTEX_M_COMMON_MAGIC 0x1A451A45U
22 #define SYSTEM_CONTROL_BASE 0x400FE000
24 #define ITM_TER0 0xE0000E00
25 #define ITM_TPR 0xE0000E40
26 #define ITM_TCR 0xE0000E80
27 #define ITM_TCR_ITMENA_BIT BIT(0)
28 #define ITM_TCR_BUSY_BIT BIT(23)
29 #define ITM_LAR 0xE0000FB0
30 #define ITM_LAR_KEY 0xC5ACCE55
32 #define CPUID 0xE000ED00
34 #define ARM_CPUID_PARTNO_POS 4
35 #define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS)
37 enum cortex_m_partno {
38 CORTEX_M_PARTNO_INVALID,
39 STAR_MC1_PARTNO = 0x132,
40 CORTEX_M0_PARTNO = 0xC20,
41 CORTEX_M1_PARTNO = 0xC21,
42 CORTEX_M3_PARTNO = 0xC23,
43 CORTEX_M4_PARTNO = 0xC24,
44 CORTEX_M7_PARTNO = 0xC27,
45 CORTEX_M0P_PARTNO = 0xC60,
46 CORTEX_M23_PARTNO = 0xD20,
47 CORTEX_M33_PARTNO = 0xD21,
48 CORTEX_M35P_PARTNO = 0xD31,
49 CORTEX_M55_PARTNO = 0xD22,
52 /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
53 #define CORTEX_M_F_HAS_FPV4 BIT(0)
54 #define CORTEX_M_F_HAS_FPV5 BIT(1)
55 #define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2)
57 struct cortex_m_part_info {
58 enum cortex_m_partno partno;
64 /* Debug Control Block */
65 #define DCB_DHCSR 0xE000EDF0
66 #define DCB_DCRSR 0xE000EDF4
67 #define DCB_DCRDR 0xE000EDF8
68 #define DCB_DEMCR 0xE000EDFC
69 #define DCB_DSCSR 0xE000EE08
71 #define DCRSR_WNR BIT(16)
73 #define DWT_CTRL 0xE0001000
74 #define DWT_CYCCNT 0xE0001004
75 #define DWT_PCSR 0xE000101C
76 #define DWT_COMP0 0xE0001020
77 #define DWT_MASK0 0xE0001024
78 #define DWT_FUNCTION0 0xE0001028
79 #define DWT_DEVARCH 0xE0001FBC
81 #define DWT_DEVARCH_ARMV8M 0x101A02
83 #define FP_CTRL 0xE0002000
84 #define FP_REMAP 0xE0002004
85 #define FP_COMP0 0xE0002008
86 #define FP_COMP1 0xE000200C
87 #define FP_COMP2 0xE0002010
88 #define FP_COMP3 0xE0002014
89 #define FP_COMP4 0xE0002018
90 #define FP_COMP5 0xE000201C
91 #define FP_COMP6 0xE0002020
92 #define FP_COMP7 0xE0002024
94 #define FPU_CPACR 0xE000ED88
95 #define FPU_FPCCR 0xE000EF34
96 #define FPU_FPCAR 0xE000EF38
97 #define FPU_FPDSCR 0xE000EF3C
99 #define TPIU_SSPSR 0xE0040000
100 #define TPIU_CSPSR 0xE0040004
101 #define TPIU_ACPR 0xE0040010
102 #define TPIU_SPPR 0xE00400F0
103 #define TPIU_FFSR 0xE0040300
104 #define TPIU_FFCR 0xE0040304
105 #define TPIU_FSCR 0xE0040308
107 /* Maximum SWO prescaler value. */
108 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
110 /* DCB_DHCSR bit and field definitions */
111 #define DBGKEY (0xA05Ful << 16)
112 #define C_DEBUGEN BIT(0)
113 #define C_HALT BIT(1)
114 #define C_STEP BIT(2)
115 #define C_MASKINTS BIT(3)
116 #define S_REGRDY BIT(16)
117 #define S_HALT BIT(17)
118 #define S_SLEEP BIT(18)
119 #define S_LOCKUP BIT(19)
120 #define S_RETIRE_ST BIT(24)
121 #define S_RESET_ST BIT(25)
123 /* DCB_DEMCR bit and field definitions */
124 #define TRCENA BIT(24)
125 #define VC_HARDERR BIT(10)
126 #define VC_INTERR BIT(9)
127 #define VC_BUSERR BIT(8)
128 #define VC_STATERR BIT(7)
129 #define VC_CHKERR BIT(6)
130 #define VC_NOCPERR BIT(5)
131 #define VC_MMERR BIT(4)
132 #define VC_CORERESET BIT(0)
134 /* DCB_DSCSR bit and field definitions */
135 #define DSCSR_CDS BIT(16)
138 #define NVIC_ICTR 0xE000E004
139 #define NVIC_ISE0 0xE000E100
140 #define NVIC_ICSR 0xE000ED04
141 #define NVIC_AIRCR 0xE000ED0C
142 #define NVIC_SHCSR 0xE000ED24
143 #define NVIC_CFSR 0xE000ED28
144 #define NVIC_MMFSRB 0xE000ED28
145 #define NVIC_BFSRB 0xE000ED29
146 #define NVIC_USFSRH 0xE000ED2A
147 #define NVIC_HFSR 0xE000ED2C
148 #define NVIC_DFSR 0xE000ED30
149 #define NVIC_MMFAR 0xE000ED34
150 #define NVIC_BFAR 0xE000ED38
151 #define NVIC_SFSR 0xE000EDE4
152 #define NVIC_SFAR 0xE000EDE8
154 /* NVIC_AIRCR bits */
155 #define AIRCR_VECTKEY (0x5FAul << 16)
156 #define AIRCR_SYSRESETREQ BIT(2)
157 #define AIRCR_VECTCLRACTIVE BIT(1)
158 #define AIRCR_VECTRESET BIT(0)
159 /* NVIC_SHCSR bits */
160 #define SHCSR_BUSFAULTENA BIT(17)
162 #define DFSR_HALTED 1
164 #define DFSR_DWTTRAP 4
165 #define DFSR_VCATCH 8
166 #define DFSR_EXTERNAL 16
169 #define FPCR_LITERAL 1
170 #define FPCR_REPLACE_REMAP (0ul << 30)
171 #define FPCR_REPLACE_BKPT_LOW (1ul << 30)
172 #define FPCR_REPLACE_BKPT_HIGH (2ul << 30)
173 #define FPCR_REPLACE_BKPT_BOTH (3ul << 30)
175 struct cortex_m_fp_comparator {
179 uint32_t fpcr_address;
182 struct cortex_m_dwt_comparator {
187 uint32_t dwt_comparator_address;
190 enum cortex_m_soft_reset_config {
191 CORTEX_M_RESET_SYSRESETREQ,
192 CORTEX_M_RESET_VECTRESET,
195 enum cortex_m_isrmasking_mode {
196 CORTEX_M_ISRMASK_AUTO,
197 CORTEX_M_ISRMASK_OFF,
199 CORTEX_M_ISRMASK_STEPONLY,
202 struct cortex_m_common {
203 unsigned int common_magic;
205 struct armv7m_common armv7m;
207 /* Context information */
209 uint32_t dcb_dhcsr_cumulated_sticky;
210 /* DCB DHCSR has been at least once read, so the sticky bits have been reset */
211 bool dcb_dhcsr_sticky_is_recent;
212 uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
213 uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
215 /* Flash Patch and Breakpoint (FPB) */
216 unsigned int fp_num_lit;
217 unsigned int fp_num_code;
220 struct cortex_m_fp_comparator *fp_comparator_list;
222 /* Data Watchpoint and Trace (DWT) */
223 unsigned int dwt_num_comp;
224 unsigned int dwt_comp_available;
225 uint32_t dwt_devarch;
226 struct cortex_m_dwt_comparator *dwt_comparator_list;
227 struct reg_cache *dwt_cache;
229 enum cortex_m_soft_reset_config soft_reset_config;
230 bool vectreset_supported;
231 enum cortex_m_isrmasking_mode isrmasking_mode;
233 const struct cortex_m_part_info *core_info;
235 bool slow_register_read; /* A register has not been ready, poll S_REGRDY */
239 /* Whether this target has the erratum that makes C_MASKINTS not apply to
240 * already pending interrupts */
241 bool maskints_erratum;
244 static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
246 return cortex_m->common_magic == CORTEX_M_COMMON_MAGIC;
249 static inline bool is_cortex_m_with_dap_access(const struct cortex_m_common *cortex_m)
251 if (!is_cortex_m_or_hla(cortex_m))
254 return !cortex_m->armv7m.is_hla_target;
258 * @returns the pointer to the target specific struct
259 * without matching a magic number.
260 * Use in target specific service routines, where the correct
261 * type of arch_info is certain.
263 static inline struct cortex_m_common *
264 target_to_cm(struct target *target)
266 return container_of(target->arch_info,
267 struct cortex_m_common, armv7m.arm);
271 * @returns the pointer to the target specific struct
272 * or NULL if the magic number does not match.
273 * Use in a flash driver or any place where mismatch of the arch_info
276 static inline struct cortex_m_common *
277 target_to_cortex_m_safe(struct target *target)
279 /* Check the parent types first to prevent peeking memory too far
280 * from arch_info pointer */
281 if (!target_to_armv7m_safe(target))
284 struct cortex_m_common *cortex_m = target_to_cm(target);
285 if (!is_cortex_m_or_hla(cortex_m))
292 * @returns cached value of Cortex-M part number
293 * or CORTEX_M_PARTNO_INVALID if the magic number does not match
294 * or core_info is not initialised.
296 static inline enum cortex_m_partno cortex_m_get_partno_safe(struct target *target)
298 struct cortex_m_common *cortex_m = target_to_cortex_m_safe(target);
300 return CORTEX_M_PARTNO_INVALID;
302 if (!cortex_m->core_info)
303 return CORTEX_M_PARTNO_INVALID;
305 return cortex_m->core_info->partno;
308 int cortex_m_examine(struct target *target);
309 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
310 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
311 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
312 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
313 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
314 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
315 void cortex_m_enable_breakpoints(struct target *target);
316 void cortex_m_enable_watchpoints(struct target *target);
317 void cortex_m_deinit_target(struct target *target);
318 int cortex_m_profiling(struct target *target, uint32_t *samples,
319 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
321 #endif /* OPENOCD_TARGET_CORTEX_M_H */