1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
25 #ifndef OPENOCD_TARGET_CORTEX_M_H
26 #define OPENOCD_TARGET_CORTEX_M_H
29 #include "helper/bits.h"
31 #define CORTEX_M_COMMON_MAGIC 0x1A451A45
33 #define SYSTEM_CONTROL_BASE 0x400FE000
35 #define ITM_TER0 0xE0000E00
36 #define ITM_TPR 0xE0000E40
37 #define ITM_TCR 0xE0000E80
38 #define ITM_TCR_ITMENA_BIT BIT(0)
39 #define ITM_TCR_BUSY_BIT BIT(23)
40 #define ITM_LAR 0xE0000FB0
41 #define ITM_LAR_KEY 0xC5ACCE55
43 #define CPUID 0xE000ED00
45 #define ARM_CPUID_PARTNO_POS 4
46 #define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS)
48 enum cortex_m_partno {
49 CORTEX_M_PARTNO_INVALID,
50 CORTEX_M0_PARTNO = 0xC20,
51 CORTEX_M1_PARTNO = 0xC21,
52 CORTEX_M3_PARTNO = 0xC23,
53 CORTEX_M4_PARTNO = 0xC24,
54 CORTEX_M7_PARTNO = 0xC27,
55 CORTEX_M0P_PARTNO = 0xC60,
56 CORTEX_M23_PARTNO = 0xD20,
57 CORTEX_M33_PARTNO = 0xD21,
58 CORTEX_M35P_PARTNO = 0xD31,
59 CORTEX_M55_PARTNO = 0xD22,
62 /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
63 #define CORTEX_M_F_HAS_FPV4 BIT(0)
64 #define CORTEX_M_F_HAS_FPV5 BIT(1)
65 #define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2)
67 struct cortex_m_part_info {
68 enum cortex_m_partno partno;
74 /* Debug Control Block */
75 #define DCB_DHCSR 0xE000EDF0
76 #define DCB_DCRSR 0xE000EDF4
77 #define DCB_DCRDR 0xE000EDF8
78 #define DCB_DEMCR 0xE000EDFC
79 #define DCB_DSCSR 0xE000EE08
81 #define DCRSR_WNR BIT(16)
83 #define DWT_CTRL 0xE0001000
84 #define DWT_CYCCNT 0xE0001004
85 #define DWT_PCSR 0xE000101C
86 #define DWT_COMP0 0xE0001020
87 #define DWT_MASK0 0xE0001024
88 #define DWT_FUNCTION0 0xE0001028
89 #define DWT_DEVARCH 0xE0001FBC
91 #define DWT_DEVARCH_ARMV8M 0x101A02
93 #define FP_CTRL 0xE0002000
94 #define FP_REMAP 0xE0002004
95 #define FP_COMP0 0xE0002008
96 #define FP_COMP1 0xE000200C
97 #define FP_COMP2 0xE0002010
98 #define FP_COMP3 0xE0002014
99 #define FP_COMP4 0xE0002018
100 #define FP_COMP5 0xE000201C
101 #define FP_COMP6 0xE0002020
102 #define FP_COMP7 0xE0002024
104 #define FPU_CPACR 0xE000ED88
105 #define FPU_FPCCR 0xE000EF34
106 #define FPU_FPCAR 0xE000EF38
107 #define FPU_FPDSCR 0xE000EF3C
109 #define TPIU_SSPSR 0xE0040000
110 #define TPIU_CSPSR 0xE0040004
111 #define TPIU_ACPR 0xE0040010
112 #define TPIU_SPPR 0xE00400F0
113 #define TPIU_FFSR 0xE0040300
114 #define TPIU_FFCR 0xE0040304
115 #define TPIU_FSCR 0xE0040308
117 /* Maximum SWO prescaler value. */
118 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
120 /* DCB_DHCSR bit and field definitions */
121 #define DBGKEY (0xA05Ful << 16)
122 #define C_DEBUGEN BIT(0)
123 #define C_HALT BIT(1)
124 #define C_STEP BIT(2)
125 #define C_MASKINTS BIT(3)
126 #define S_REGRDY BIT(16)
127 #define S_HALT BIT(17)
128 #define S_SLEEP BIT(18)
129 #define S_LOCKUP BIT(19)
130 #define S_RETIRE_ST BIT(24)
131 #define S_RESET_ST BIT(25)
133 /* DCB_DEMCR bit and field definitions */
134 #define TRCENA BIT(24)
135 #define VC_HARDERR BIT(10)
136 #define VC_INTERR BIT(9)
137 #define VC_BUSERR BIT(8)
138 #define VC_STATERR BIT(7)
139 #define VC_CHKERR BIT(6)
140 #define VC_NOCPERR BIT(5)
141 #define VC_MMERR BIT(4)
142 #define VC_CORERESET BIT(0)
144 /* DCB_DSCSR bit and field definitions */
145 #define DSCSR_CDS BIT(16)
148 #define NVIC_ICTR 0xE000E004
149 #define NVIC_ISE0 0xE000E100
150 #define NVIC_ICSR 0xE000ED04
151 #define NVIC_AIRCR 0xE000ED0C
152 #define NVIC_SHCSR 0xE000ED24
153 #define NVIC_CFSR 0xE000ED28
154 #define NVIC_MMFSRB 0xE000ED28
155 #define NVIC_BFSRB 0xE000ED29
156 #define NVIC_USFSRH 0xE000ED2A
157 #define NVIC_HFSR 0xE000ED2C
158 #define NVIC_DFSR 0xE000ED30
159 #define NVIC_MMFAR 0xE000ED34
160 #define NVIC_BFAR 0xE000ED38
161 #define NVIC_SFSR 0xE000EDE4
162 #define NVIC_SFAR 0xE000EDE8
164 /* NVIC_AIRCR bits */
165 #define AIRCR_VECTKEY (0x5FAul << 16)
166 #define AIRCR_SYSRESETREQ BIT(2)
167 #define AIRCR_VECTCLRACTIVE BIT(1)
168 #define AIRCR_VECTRESET BIT(0)
169 /* NVIC_SHCSR bits */
170 #define SHCSR_BUSFAULTENA BIT(17)
172 #define DFSR_HALTED 1
174 #define DFSR_DWTTRAP 4
175 #define DFSR_VCATCH 8
176 #define DFSR_EXTERNAL 16
179 #define FPCR_LITERAL 1
180 #define FPCR_REPLACE_REMAP (0ul << 30)
181 #define FPCR_REPLACE_BKPT_LOW (1ul << 30)
182 #define FPCR_REPLACE_BKPT_HIGH (2ul << 30)
183 #define FPCR_REPLACE_BKPT_BOTH (3ul << 30)
185 struct cortex_m_fp_comparator {
189 uint32_t fpcr_address;
192 struct cortex_m_dwt_comparator {
197 uint32_t dwt_comparator_address;
200 enum cortex_m_soft_reset_config {
201 CORTEX_M_RESET_SYSRESETREQ,
202 CORTEX_M_RESET_VECTRESET,
205 enum cortex_m_isrmasking_mode {
206 CORTEX_M_ISRMASK_AUTO,
207 CORTEX_M_ISRMASK_OFF,
209 CORTEX_M_ISRMASK_STEPONLY,
212 struct cortex_m_common {
215 /* Context information */
217 uint32_t dcb_dhcsr_cumulated_sticky;
218 uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
219 uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
221 /* Flash Patch and Breakpoint (FPB) */
222 unsigned int fp_num_lit;
223 unsigned int fp_num_code;
226 struct cortex_m_fp_comparator *fp_comparator_list;
228 /* Data Watchpoint and Trace (DWT) */
229 unsigned int dwt_num_comp;
230 unsigned int dwt_comp_available;
231 uint32_t dwt_devarch;
232 struct cortex_m_dwt_comparator *dwt_comparator_list;
233 struct reg_cache *dwt_cache;
235 enum cortex_m_soft_reset_config soft_reset_config;
236 bool vectreset_supported;
237 enum cortex_m_isrmasking_mode isrmasking_mode;
239 const struct cortex_m_part_info *core_info;
240 struct armv7m_common armv7m;
242 bool slow_register_read; /* A register has not been ready, poll S_REGRDY */
246 /* Whether this target has the erratum that makes C_MASKINTS not apply to
247 * already pending interrupts */
248 bool maskints_erratum;
251 static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
253 return cortex_m->common_magic == CORTEX_M_COMMON_MAGIC;
256 static inline bool is_cortex_m_with_dap_access(const struct cortex_m_common *cortex_m)
258 if (!is_cortex_m_or_hla(cortex_m))
261 return !cortex_m->armv7m.is_hla_target;
265 * @returns the pointer to the target specific struct
266 * without matching a magic number.
267 * Use in target specific service routines, where the correct
268 * type of arch_info is certain.
270 static inline struct cortex_m_common *
271 target_to_cm(struct target *target)
273 return container_of(target->arch_info,
274 struct cortex_m_common, armv7m.arm);
278 * @returns the pointer to the target specific struct
279 * or NULL if the magic number does not match.
280 * Use in a flash driver or any place where mismatch of the arch_info
283 static inline struct cortex_m_common *
284 target_to_cortex_m_safe(struct target *target)
286 /* Check the parent types first to prevent peeking memory too far
287 * from arch_info pointer */
288 if (!target_to_armv7m_safe(target))
291 struct cortex_m_common *cortex_m = target_to_cm(target);
292 if (!is_cortex_m_or_hla(cortex_m))
299 * @returns cached value of Cortex-M part number
300 * or CORTEX_M_PARTNO_INVALID if the magic number does not match
301 * or core_info is not initialised.
303 static inline enum cortex_m_partno cortex_m_get_partno_safe(struct target *target)
305 struct cortex_m_common *cortex_m = target_to_cortex_m_safe(target);
307 return CORTEX_M_PARTNO_INVALID;
309 if (!cortex_m->core_info)
310 return CORTEX_M_PARTNO_INVALID;
312 return cortex_m->core_info->partno;
315 int cortex_m_examine(struct target *target);
316 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
317 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
318 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
319 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
320 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
321 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
322 void cortex_m_enable_breakpoints(struct target *target);
323 void cortex_m_enable_watchpoints(struct target *target);
324 void cortex_m_deinit_target(struct target *target);
325 int cortex_m_profiling(struct target *target, uint32_t *samples,
326 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
328 #endif /* OPENOCD_TARGET_CORTEX_M_H */