1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
25 #ifndef OPENOCD_TARGET_CORTEX_M_H
26 #define OPENOCD_TARGET_CORTEX_M_H
29 #include "helper/bits.h"
31 #define CORTEX_M_COMMON_MAGIC 0x1A451A45
33 #define SYSTEM_CONTROL_BASE 0x400FE000
35 #define ITM_TER0 0xE0000E00
36 #define ITM_TPR 0xE0000E40
37 #define ITM_TCR 0xE0000E80
38 #define ITM_TCR_ITMENA_BIT BIT(0)
39 #define ITM_TCR_BUSY_BIT BIT(23)
40 #define ITM_LAR 0xE0000FB0
41 #define ITM_LAR_KEY 0xC5ACCE55
43 #define CPUID 0xE000ED00
45 #define ARM_CPUID_PARTNO_MASK 0xFFF0
47 #define CORTEX_M23_PARTNO 0xD200
48 #define CORTEX_M33_PARTNO 0xD210
49 #define CORTEX_M35P_PARTNO 0xD310
50 #define CORTEX_M55_PARTNO 0xD220
52 /* Debug Control Block */
53 #define DCB_DHCSR 0xE000EDF0
54 #define DCB_DCRSR 0xE000EDF4
55 #define DCB_DCRDR 0xE000EDF8
56 #define DCB_DEMCR 0xE000EDFC
57 #define DCB_DSCSR 0xE000EE08
59 #define DCRSR_WnR BIT(16)
61 #define DWT_CTRL 0xE0001000
62 #define DWT_CYCCNT 0xE0001004
63 #define DWT_PCSR 0xE000101C
64 #define DWT_COMP0 0xE0001020
65 #define DWT_MASK0 0xE0001024
66 #define DWT_FUNCTION0 0xE0001028
67 #define DWT_DEVARCH 0xE0001FBC
69 #define DWT_DEVARCH_ARMV8M 0x101A02
71 #define FP_CTRL 0xE0002000
72 #define FP_REMAP 0xE0002004
73 #define FP_COMP0 0xE0002008
74 #define FP_COMP1 0xE000200C
75 #define FP_COMP2 0xE0002010
76 #define FP_COMP3 0xE0002014
77 #define FP_COMP4 0xE0002018
78 #define FP_COMP5 0xE000201C
79 #define FP_COMP6 0xE0002020
80 #define FP_COMP7 0xE0002024
82 #define FPU_CPACR 0xE000ED88
83 #define FPU_FPCCR 0xE000EF34
84 #define FPU_FPCAR 0xE000EF38
85 #define FPU_FPDSCR 0xE000EF3C
87 #define TPIU_SSPSR 0xE0040000
88 #define TPIU_CSPSR 0xE0040004
89 #define TPIU_ACPR 0xE0040010
90 #define TPIU_SPPR 0xE00400F0
91 #define TPIU_FFSR 0xE0040300
92 #define TPIU_FFCR 0xE0040304
93 #define TPIU_FSCR 0xE0040308
95 /* Maximum SWO prescaler value. */
96 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
98 /* DCB_DHCSR bit and field definitions */
99 #define DBGKEY (0xA05Ful << 16)
100 #define C_DEBUGEN BIT(0)
101 #define C_HALT BIT(1)
102 #define C_STEP BIT(2)
103 #define C_MASKINTS BIT(3)
104 #define S_REGRDY BIT(16)
105 #define S_HALT BIT(17)
106 #define S_SLEEP BIT(18)
107 #define S_LOCKUP BIT(19)
108 #define S_RETIRE_ST BIT(24)
109 #define S_RESET_ST BIT(25)
111 /* DCB_DEMCR bit and field definitions */
112 #define TRCENA BIT(24)
113 #define VC_HARDERR BIT(10)
114 #define VC_INTERR BIT(9)
115 #define VC_BUSERR BIT(8)
116 #define VC_STATERR BIT(7)
117 #define VC_CHKERR BIT(6)
118 #define VC_NOCPERR BIT(5)
119 #define VC_MMERR BIT(4)
120 #define VC_CORERESET BIT(0)
122 /* DCB_DSCSR bit and field definitions */
123 #define DSCSR_CDS BIT(16)
126 #define NVIC_ICTR 0xE000E004
127 #define NVIC_ISE0 0xE000E100
128 #define NVIC_ICSR 0xE000ED04
129 #define NVIC_AIRCR 0xE000ED0C
130 #define NVIC_SHCSR 0xE000ED24
131 #define NVIC_CFSR 0xE000ED28
132 #define NVIC_MMFSRb 0xE000ED28
133 #define NVIC_BFSRb 0xE000ED29
134 #define NVIC_USFSRh 0xE000ED2A
135 #define NVIC_HFSR 0xE000ED2C
136 #define NVIC_DFSR 0xE000ED30
137 #define NVIC_MMFAR 0xE000ED34
138 #define NVIC_BFAR 0xE000ED38
139 #define NVIC_SFSR 0xE000EDE4
140 #define NVIC_SFAR 0xE000EDE8
142 /* NVIC_AIRCR bits */
143 #define AIRCR_VECTKEY (0x5FAul << 16)
144 #define AIRCR_SYSRESETREQ BIT(2)
145 #define AIRCR_VECTCLRACTIVE BIT(1)
146 #define AIRCR_VECTRESET BIT(0)
147 /* NVIC_SHCSR bits */
148 #define SHCSR_BUSFAULTENA BIT(17)
150 #define DFSR_HALTED 1
152 #define DFSR_DWTTRAP 4
153 #define DFSR_VCATCH 8
154 #define DFSR_EXTERNAL 16
157 #define FPCR_LITERAL 1
158 #define FPCR_REPLACE_REMAP (0ul << 30)
159 #define FPCR_REPLACE_BKPT_LOW (1ul << 30)
160 #define FPCR_REPLACE_BKPT_HIGH (2ul << 30)
161 #define FPCR_REPLACE_BKPT_BOTH (3ul << 30)
163 struct cortex_m_fp_comparator {
167 uint32_t fpcr_address;
170 struct cortex_m_dwt_comparator {
175 uint32_t dwt_comparator_address;
178 enum cortex_m_soft_reset_config {
179 CORTEX_M_RESET_SYSRESETREQ,
180 CORTEX_M_RESET_VECTRESET,
183 enum cortex_m_isrmasking_mode {
184 CORTEX_M_ISRMASK_AUTO,
185 CORTEX_M_ISRMASK_OFF,
187 CORTEX_M_ISRMASK_STEPONLY,
190 struct cortex_m_common {
193 /* Context information */
195 uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
196 uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
198 /* Flash Patch and Breakpoint (FPB) */
199 unsigned int fp_num_lit;
200 unsigned int fp_num_code;
203 struct cortex_m_fp_comparator *fp_comparator_list;
205 /* Data Watchpoint and Trace (DWT) */
206 unsigned int dwt_num_comp;
207 unsigned int dwt_comp_available;
208 uint32_t dwt_devarch;
209 struct cortex_m_dwt_comparator *dwt_comparator_list;
210 struct reg_cache *dwt_cache;
212 enum cortex_m_soft_reset_config soft_reset_config;
213 bool vectreset_supported;
215 enum cortex_m_isrmasking_mode isrmasking_mode;
217 struct armv7m_common armv7m;
221 /* Whether this target has the erratum that makes C_MASKINTS not apply to
222 * already pending interrupts */
223 bool maskints_erratum;
226 static inline struct cortex_m_common *
227 target_to_cm(struct target *target)
229 return container_of(target->arch_info,
230 struct cortex_m_common, armv7m);
233 int cortex_m_examine(struct target *target);
234 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
235 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
236 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
237 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
238 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
239 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
240 void cortex_m_enable_breakpoints(struct target *target);
241 void cortex_m_enable_watchpoints(struct target *target);
242 void cortex_m_deinit_target(struct target *target);
243 int cortex_m_profiling(struct target *target, uint32_t *samples,
244 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
246 #endif /* OPENOCD_TARGET_CORTEX_M_H */