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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "jtag/interface.h"
  35 #include "breakpoints.h"
  36 #include "cortex_m.h"
  37 #include "target_request.h"
  38 #include "target_type.h"
  39 #include "arm_disassembler.h"
  40 #include "register.h"
  41 #include "arm_opcodes.h"
  42 #include "arm_semihosting.h"
  43 #include <helper/time_support.h>
  44
  45 /* NOTE:  most of this should work fine for the Cortex-M1 and
  46  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  47  * Some differences:  M0/M1 doesn't have FBP remapping or the
  48  * DWT tracing/profiling support.  (So the cycle counter will
  49  * not be usable; the other stuff isn't currently used here.)
  50  *
  51  * Although there are some workarounds for errata seen only in r0p0
  52  * silicon, such old parts are hard to find and thus not much tested
  53  * any longer.
  54  */
  55
  56 /**
  57  * Returns the type of a break point required by address location
  58  */
  59 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
  60
  61 /* forward declarations */
  62 static int cortex_m_store_core_reg_u32(struct target *target,
  63                 uint32_t num, uint32_t value);
  64 static void cortex_m_dwt_free(struct target *target);
  65
  66 static int cortexm_dap_read_coreregister_u32(struct target *target,
  67         uint32_t *value, int regnum)
  68 {
  69         struct armv7m_common *armv7m = target_to_armv7m(target);
  70         struct adiv5_dap *swjdp = armv7m->arm.dap;
  71         int retval;
  72         uint32_t dcrdr;
  73
  74         /* because the DCB_DCRDR is used for the emulated dcc channel
  75          * we have to save/restore the DCB_DCRDR when used */
  76         if (target->dbg_msg_enabled) {
  77                 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  78                 if (retval != ERROR_OK)
  79                         return retval;
  80         }
  81
  82         retval = mem_ap_write_u32(swjdp, DCB_DCRSR, regnum);
  83         if (retval != ERROR_OK)
  84                 return retval;
  85
  86         retval = mem_ap_read_atomic_u32(swjdp, DCB_DCRDR, value);
  87         if (retval != ERROR_OK)
  88                 return retval;
  89
  90         if (target->dbg_msg_enabled) {
  91                 /* restore DCB_DCRDR - this needs to be in a separate
  92                  * transaction otherwise the emulated DCC channel breaks */
  93                 if (retval == ERROR_OK)
  94                         retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  95         }
  96
  97         return retval;
  98 }
  99
 100 static int cortexm_dap_write_coreregister_u32(struct target *target,
 101         uint32_t value, int regnum)
 102 {
 103         struct armv7m_common *armv7m = target_to_armv7m(target);
 104         struct adiv5_dap *swjdp = armv7m->arm.dap;
 105         int retval;
 106         uint32_t dcrdr;
 107
 108         /* because the DCB_DCRDR is used for the emulated dcc channel
 109          * we have to save/restore the DCB_DCRDR when used */
 110         if (target->dbg_msg_enabled) {
 111                 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 112                 if (retval != ERROR_OK)
 113                         return retval;
 114         }
 115
 116         retval = mem_ap_write_u32(swjdp, DCB_DCRDR, value);
 117         if (retval != ERROR_OK)
 118                 return retval;
 119
 120         retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRSR, regnum | DCRSR_WnR);
 121         if (retval != ERROR_OK)
 122                 return retval;
 123
 124         if (target->dbg_msg_enabled) {
 125                 /* restore DCB_DCRDR - this needs to be in a seperate
 126                  * transaction otherwise the emulated DCC channel breaks */
 127                 if (retval == ERROR_OK)
 128                         retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 129         }
 130
 131         return retval;
 132 }
 133
 134 static int cortex_m_write_debug_halt_mask(struct target *target,
 135         uint32_t mask_on, uint32_t mask_off)
 136 {
 137         struct cortex_m_common *cortex_m = target_to_cm(target);
 138         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 139
 140         /* mask off status bits */
 141         cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 142         /* create new register mask */
 143         cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 144
 145         return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m->dcb_dhcsr);
 146 }
 147
 148 static int cortex_m_clear_halt(struct target *target)
 149 {
 150         struct cortex_m_common *cortex_m = target_to_cm(target);
 151         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 152         int retval;
 153
 154         /* clear step if any */
 155         cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
 156
 157         /* Read Debug Fault Status Register */
 158         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m->nvic_dfsr);
 159         if (retval != ERROR_OK)
 160                 return retval;
 161
 162         /* Clear Debug Fault Status */
 163         retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m->nvic_dfsr);
 164         if (retval != ERROR_OK)
 165                 return retval;
 166         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
 167
 168         return ERROR_OK;
 169 }
 170
 171 static int cortex_m_single_step_core(struct target *target)
 172 {
 173         struct cortex_m_common *cortex_m = target_to_cm(target);
 174         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 175         uint32_t dhcsr_save;
 176         int retval;
 177
 178         /* backup dhcsr reg */
 179         dhcsr_save = cortex_m->dcb_dhcsr;
 180
 181         /* Mask interrupts before clearing halt, if done already.  This avoids
 182          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 183          * HALT can put the core into an unknown state.
 184          */
 185         if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
 186                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 187                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 188                 if (retval != ERROR_OK)
 189                         return retval;
 190         }
 191         retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 192                         DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 193         if (retval != ERROR_OK)
 194                 return retval;
 195         LOG_DEBUG(" ");
 196
 197         /* restore dhcsr reg */
 198         cortex_m->dcb_dhcsr = dhcsr_save;
 199         cortex_m_clear_halt(target);
 200
 201         return ERROR_OK;
 202 }
 203
 204 static int cortex_m_enable_fpb(struct target *target)
 205 {
 206         int retval = target_write_u32(target, FP_CTRL, 3);
 207         if (retval != ERROR_OK)
 208                 return retval;
 209
 210         /* check the fpb is actually enabled */
 211         uint32_t fpctrl;
 212         retval = target_read_u32(target, FP_CTRL, &fpctrl);
 213         if (retval != ERROR_OK)
 214                 return retval;
 215
 216         if (fpctrl & 1)
 217                 return ERROR_OK;
 218
 219         return ERROR_FAIL;
 220 }
 221
 222 static int cortex_m_endreset_event(struct target *target)
 223 {
 224         int i;
 225         int retval;
 226         uint32_t dcb_demcr;
 227         struct cortex_m_common *cortex_m = target_to_cm(target);
 228         struct armv7m_common *armv7m = &cortex_m->armv7m;
 229         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 230         struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
 231         struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
 232
 233         /* REVISIT The four debug monitor bits are currently ignored... */
 234         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 235         if (retval != ERROR_OK)
 236                 return retval;
 237         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
 238
 239         /* this register is used for emulated dcc channel */
 240         retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 241         if (retval != ERROR_OK)
 242                 return retval;
 243
 244         /* Enable debug requests */
 245         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 246         if (retval != ERROR_OK)
 247                 return retval;
 248         if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
 249                 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 250                 if (retval != ERROR_OK)
 251                         return retval;
 252         }
 253
 254         /* clear any interrupt masking */
 255         cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
 256
 257         /* Enable features controlled by ITM and DWT blocks, and catch only
 258          * the vectors we were told to pay attention to.
 259          *
 260          * Target firmware is responsible for all fault handling policy
 261          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 262          * or manual updates to the NVIC SHCSR and CCR registers.
 263          */
 264         retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
 265         if (retval != ERROR_OK)
 266                 return retval;
 267
 268         /* Paranoia: evidently some (early?) chips don't preserve all the
 269          * debug state (including FBP, DWT, etc) across reset...
 270          */
 271
 272         /* Enable FPB */
 273         retval = cortex_m_enable_fpb(target);
 274         if (retval != ERROR_OK) {
 275                 LOG_ERROR("Failed to enable the FPB");
 276                 return retval;
 277         }
 278
 279         cortex_m->fpb_enabled = 1;
 280
 281         /* Restore FPB registers */
 282         for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
 283                 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 284                 if (retval != ERROR_OK)
 285                         return retval;
 286         }
 287
 288         /* Restore DWT registers */
 289         for (i = 0; i < cortex_m->dwt_num_comp; i++) {
 290                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 291                                 dwt_list[i].comp);
 292                 if (retval != ERROR_OK)
 293                         return retval;
 294                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 295                                 dwt_list[i].mask);
 296                 if (retval != ERROR_OK)
 297                         return retval;
 298                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 299                                 dwt_list[i].function);
 300                 if (retval != ERROR_OK)
 301                         return retval;
 302         }
 303         retval = dap_run(swjdp);
 304         if (retval != ERROR_OK)
 305                 return retval;
 306
 307         register_cache_invalidate(armv7m->arm.core_cache);
 308
 309         /* make sure we have latest dhcsr flags */
 310         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 311
 312         return retval;
 313 }
 314
 315 static int cortex_m_examine_debug_reason(struct target *target)
 316 {
 317         struct cortex_m_common *cortex_m = target_to_cm(target);
 318
 319         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
 320          * only check the debug reason if we don't know it already */
 321
 322         if ((target->debug_reason != DBG_REASON_DBGRQ)
 323                 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
 324                 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
 325                         target->debug_reason = DBG_REASON_BREAKPOINT;
 326                         if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 327                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 328                 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 329                         target->debug_reason = DBG_REASON_WATCHPOINT;
 330                 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
 331                         target->debug_reason = DBG_REASON_BREAKPOINT;
 332                 else    /* EXTERNAL, HALTED */
 333                         target->debug_reason = DBG_REASON_UNDEFINED;
 334         }
 335
 336         return ERROR_OK;
 337 }
 338
 339 static int cortex_m_examine_exception_reason(struct target *target)
 340 {
 341         uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
 342         struct armv7m_common *armv7m = target_to_armv7m(target);
 343         struct adiv5_dap *swjdp = armv7m->arm.dap;
 344         int retval;
 345
 346         retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 347         if (retval != ERROR_OK)
 348                 return retval;
 349         switch (armv7m->exception_number) {
 350                 case 2: /* NMI */
 351                         break;
 352                 case 3: /* Hard Fault */
 353                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 354                         if (retval != ERROR_OK)
 355                                 return retval;
 356                         if (except_sr & 0x40000000) {
 357                                 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
 358                                 if (retval != ERROR_OK)
 359                                         return retval;
 360                         }
 361                         break;
 362                 case 4: /* Memory Management */
 363                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 364                         if (retval != ERROR_OK)
 365                                 return retval;
 366                         retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
 367                         if (retval != ERROR_OK)
 368                                 return retval;
 369                         break;
 370                 case 5: /* Bus Fault */
 371                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 372                         if (retval != ERROR_OK)
 373                                 return retval;
 374                         retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
 375                         if (retval != ERROR_OK)
 376                                 return retval;
 377                         break;
 378                 case 6: /* Usage Fault */
 379                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 380                         if (retval != ERROR_OK)
 381                                 return retval;
 382                         break;
 383                 case 11:        /* SVCall */
 384                         break;
 385                 case 12:        /* Debug Monitor */
 386                         retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
 387                         if (retval != ERROR_OK)
 388                                 return retval;
 389                         break;
 390                 case 14:        /* PendSV */
 391                         break;
 392                 case 15:        /* SysTick */
 393                         break;
 394                 default:
 395                         except_sr = 0;
 396                         break;
 397         }
 398         retval = dap_run(swjdp);
 399         if (retval == ERROR_OK)
 400                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 401                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 402                         armv7m_exception_string(armv7m->exception_number),
 403                         shcsr, except_sr, cfsr, except_ar);
 404         return retval;
 405 }
 406
 407 static int cortex_m_debug_entry(struct target *target)
 408 {
 409         int i;
 410         uint32_t xPSR;
 411         int retval;
 412         struct cortex_m_common *cortex_m = target_to_cm(target);
 413         struct armv7m_common *armv7m = &cortex_m->armv7m;
 414         struct arm *arm = &armv7m->arm;
 415         struct adiv5_dap *swjdp = armv7m->arm.dap;
 416         struct reg *r;
 417
 418         LOG_DEBUG(" ");
 419
 420         cortex_m_clear_halt(target);
 421         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 422         if (retval != ERROR_OK)
 423                 return retval;
 424
 425         retval = armv7m->examine_debug_reason(target);
 426         if (retval != ERROR_OK)
 427                 return retval;
 428
 429         /* Examine target state and mode
 430          * First load register accessible through core debug port */
 431         int num_regs = arm->core_cache->num_regs;
 432
 433         for (i = 0; i < num_regs; i++) {
 434                 r = &armv7m->arm.core_cache->reg_list[i];
 435                 if (!r->valid)
 436                         arm->read_core_reg(target, r, i, ARM_MODE_ANY);
 437         }
 438
 439         r = arm->cpsr;
 440         xPSR = buf_get_u32(r->value, 0, 32);
 441
 442         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 443         if (xPSR & 0xf00) {
 444                 r->dirty = r->valid;
 445                 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
 446         }
 447
 448         /* Are we in an exception handler */
 449         if (xPSR & 0x1FF) {
 450                 armv7m->exception_number = (xPSR & 0x1FF);
 451
 452                 arm->core_mode = ARM_MODE_HANDLER;
 453                 arm->map = armv7m_msp_reg_map;
 454         } else {
 455                 unsigned control = buf_get_u32(arm->core_cache
 456                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 457
 458                 /* is this thread privileged? */
 459                 arm->core_mode = control & 1
 460                         ? ARM_MODE_USER_THREAD
 461                         : ARM_MODE_THREAD;
 462
 463                 /* which stack is it using? */
 464                 if (control & 2)
 465                         arm->map = armv7m_psp_reg_map;
 466                 else
 467                         arm->map = armv7m_msp_reg_map;
 468
 469                 armv7m->exception_number = 0;
 470         }
 471
 472         if (armv7m->exception_number)
 473                 cortex_m_examine_exception_reason(target);
 474
 475         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 476                 arm_mode_name(arm->core_mode),
 477                 buf_get_u32(arm->pc->value, 0, 32),
 478                 target_state_name(target));
 479
 480         if (armv7m->post_debug_entry) {
 481                 retval = armv7m->post_debug_entry(target);
 482                 if (retval != ERROR_OK)
 483                         return retval;
 484         }
 485
 486         return ERROR_OK;
 487 }
 488
 489 static int cortex_m_poll(struct target *target)
 490 {
 491         int detected_failure = ERROR_OK;
 492         int retval = ERROR_OK;
 493         enum target_state prev_target_state = target->state;
 494         struct cortex_m_common *cortex_m = target_to_cm(target);
 495         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 496
 497         /* Read from Debug Halting Control and Status Register */
 498         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 499         if (retval != ERROR_OK) {
 500                 target->state = TARGET_UNKNOWN;
 501                 return retval;
 502         }
 503
 504         /* Recover from lockup.  See ARMv7-M architecture spec,
 505          * section B1.5.15 "Unrecoverable exception cases".
 506          */
 507         if (cortex_m->dcb_dhcsr & S_LOCKUP) {
 508                 LOG_ERROR("%s -- clearing lockup after double fault",
 509                         target_name(target));
 510                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 511                 target->debug_reason = DBG_REASON_DBGRQ;
 512
 513                 /* We have to execute the rest (the "finally" equivalent, but
 514                  * still throw this exception again).
 515                  */
 516                 detected_failure = ERROR_FAIL;
 517
 518                 /* refresh status bits */
 519                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 520                 if (retval != ERROR_OK)
 521                         return retval;
 522         }
 523
 524         if (cortex_m->dcb_dhcsr & S_RESET_ST) {
 525                 target->state = TARGET_RESET;
 526                 return ERROR_OK;
 527         }
 528
 529         if (target->state == TARGET_RESET) {
 530                 /* Cannot switch context while running so endreset is
 531                  * called with target->state == TARGET_RESET
 532                  */
 533                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 534                         cortex_m->dcb_dhcsr);
 535                 retval = cortex_m_endreset_event(target);
 536                 if (retval != ERROR_OK) {
 537                         target->state = TARGET_UNKNOWN;
 538                         return retval;
 539                 }
 540                 target->state = TARGET_RUNNING;
 541                 prev_target_state = TARGET_RUNNING;
 542         }
 543
 544         if (cortex_m->dcb_dhcsr & S_HALT) {
 545                 target->state = TARGET_HALTED;
 546
 547                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
 548                         retval = cortex_m_debug_entry(target);
 549                         if (retval != ERROR_OK)
 550                                 return retval;
 551
 552                         if (arm_semihosting(target, &retval) != 0)
 553                                 return retval;
 554
 555                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 556                 }
 557                 if (prev_target_state == TARGET_DEBUG_RUNNING) {
 558                         LOG_DEBUG(" ");
 559                         retval = cortex_m_debug_entry(target);
 560                         if (retval != ERROR_OK)
 561                                 return retval;
 562
 563                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 564                 }
 565         }
 566
 567         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 568          * How best to model low power modes?
 569          */
 570
 571         if (target->state == TARGET_UNKNOWN) {
 572                 /* check if processor is retiring instructions */
 573                 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
 574                         target->state = TARGET_RUNNING;
 575                         retval = ERROR_OK;
 576                 }
 577         }
 578
 579         /* Did we detect a failure condition that we cleared? */
 580         if (detected_failure != ERROR_OK)
 581                 retval = detected_failure;
 582         return retval;
 583 }
 584
 585 static int cortex_m_halt(struct target *target)
 586 {
 587         LOG_DEBUG("target->state: %s",
 588                 target_state_name(target));
 589
 590         if (target->state == TARGET_HALTED) {
 591                 LOG_DEBUG("target was already halted");
 592                 return ERROR_OK;
 593         }
 594
 595         if (target->state == TARGET_UNKNOWN)
 596                 LOG_WARNING("target was in unknown state when halt was requested");
 597
 598         if (target->state == TARGET_RESET) {
 599                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 600                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 601                         return ERROR_TARGET_FAILURE;
 602                 } else {
 603                         /* we came here in a reset_halt or reset_init sequence
 604                          * debug entry was already prepared in cortex_m3_assert_reset()
 605                          */
 606                         target->debug_reason = DBG_REASON_DBGRQ;
 607
 608                         return ERROR_OK;
 609                 }
 610         }
 611
 612         /* Write to Debug Halting Control and Status Register */
 613         cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 614
 615         target->debug_reason = DBG_REASON_DBGRQ;
 616
 617         return ERROR_OK;
 618 }
 619
 620 static int cortex_m_soft_reset_halt(struct target *target)
 621 {
 622         struct cortex_m_common *cortex_m = target_to_cm(target);
 623         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 624         uint32_t dcb_dhcsr = 0;
 625         int retval, timeout = 0;
 626
 627         /* soft_reset_halt is deprecated on cortex_m as the same functionality
 628          * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
 629          * As this reset only used VC_CORERESET it would only ever reset the cortex_m
 630          * core, not the peripherals */
 631         LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
 632
 633         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 634         retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
 635                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 636         if (retval != ERROR_OK)
 637                 return retval;
 638
 639         /* Request a core-only reset */
 640         retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 641                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 642         if (retval != ERROR_OK)
 643                 return retval;
 644         target->state = TARGET_RESET;
 645
 646         /* registers are now invalid */
 647         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 648
 649         while (timeout < 100) {
 650                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 651                 if (retval == ERROR_OK) {
 652                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
 653                                         &cortex_m->nvic_dfsr);
 654                         if (retval != ERROR_OK)
 655                                 return retval;
 656                         if ((dcb_dhcsr & S_HALT)
 657                                 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
 658                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 659                                         "DFSR 0x%08x",
 660                                         (unsigned) dcb_dhcsr,
 661                                         (unsigned) cortex_m->nvic_dfsr);
 662                                 cortex_m_poll(target);
 663                                 /* FIXME restore user's vector catch config */
 664                                 return ERROR_OK;
 665                         } else
 666                                 LOG_DEBUG("waiting for system reset-halt, "
 667                                         "DHCSR 0x%08x, %d ms",
 668                                         (unsigned) dcb_dhcsr, timeout);
 669                 }
 670                 timeout++;
 671                 alive_sleep(1);
 672         }
 673
 674         return ERROR_OK;
 675 }
 676
 677 void cortex_m_enable_breakpoints(struct target *target)
 678 {
 679         struct breakpoint *breakpoint = target->breakpoints;
 680
 681         /* set any pending breakpoints */
 682         while (breakpoint) {
 683                 if (!breakpoint->set)
 684                         cortex_m_set_breakpoint(target, breakpoint);
 685                 breakpoint = breakpoint->next;
 686         }
 687 }
 688
 689 static int cortex_m_resume(struct target *target, int current,
 690         uint32_t address, int handle_breakpoints, int debug_execution)
 691 {
 692         struct armv7m_common *armv7m = target_to_armv7m(target);
 693         struct breakpoint *breakpoint = NULL;
 694         uint32_t resume_pc;
 695         struct reg *r;
 696
 697         if (target->state != TARGET_HALTED) {
 698                 LOG_WARNING("target not halted");
 699                 return ERROR_TARGET_NOT_HALTED;
 700         }
 701
 702         if (!debug_execution) {
 703                 target_free_all_working_areas(target);
 704                 cortex_m_enable_breakpoints(target);
 705                 cortex_m_enable_watchpoints(target);
 706         }
 707
 708         if (debug_execution) {
 709                 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
 710
 711                 /* Disable interrupts */
 712                 /* We disable interrupts in the PRIMASK register instead of
 713                  * masking with C_MASKINTS.  This is probably the same issue
 714                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 715                  * in parallel with disabled interrupts can cause local faults
 716                  * to not be taken.
 717                  *
 718                  * REVISIT this clearly breaks non-debug execution, since the
 719                  * PRIMASK register state isn't saved/restored...  workaround
 720                  * by never resuming app code after debug execution.
 721                  */
 722                 buf_set_u32(r->value, 0, 1, 1);
 723                 r->dirty = true;
 724                 r->valid = true;
 725
 726                 /* Make sure we are in Thumb mode */
 727                 r = armv7m->arm.cpsr;
 728                 buf_set_u32(r->value, 24, 1, 1);
 729                 r->dirty = true;
 730                 r->valid = true;
 731         }
 732
 733         /* current = 1: continue on current pc, otherwise continue at <address> */
 734         r = armv7m->arm.pc;
 735         if (!current) {
 736                 buf_set_u32(r->value, 0, 32, address);
 737                 r->dirty = true;
 738                 r->valid = true;
 739         }
 740
 741         /* if we halted last time due to a bkpt instruction
 742          * then we have to manually step over it, otherwise
 743          * the core will break again */
 744
 745         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 746                 && !debug_execution)
 747                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 748
 749         resume_pc = buf_get_u32(r->value, 0, 32);
 750
 751         armv7m_restore_context(target);
 752
 753         /* the front-end may request us not to handle breakpoints */
 754         if (handle_breakpoints) {
 755                 /* Single step past breakpoint at current address */
 756                 breakpoint = breakpoint_find(target, resume_pc);
 757                 if (breakpoint) {
 758                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %" PRIu32 ")",
 759                                 breakpoint->address,
 760                                 breakpoint->unique_id);
 761                         cortex_m_unset_breakpoint(target, breakpoint);
 762                         cortex_m_single_step_core(target);
 763                         cortex_m_set_breakpoint(target, breakpoint);
 764                 }
 765         }
 766
 767         /* Restart core */
 768         cortex_m_write_debug_halt_mask(target, 0, C_HALT);
 769
 770         target->debug_reason = DBG_REASON_NOTHALTED;
 771
 772         /* registers are now invalid */
 773         register_cache_invalidate(armv7m->arm.core_cache);
 774
 775         if (!debug_execution) {
 776                 target->state = TARGET_RUNNING;
 777                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 778                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 779         } else {
 780                 target->state = TARGET_DEBUG_RUNNING;
 781                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 782                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 783         }
 784
 785         return ERROR_OK;
 786 }
 787
 788 /* int irqstepcount = 0; */
 789 static int cortex_m_step(struct target *target, int current,
 790         uint32_t address, int handle_breakpoints)
 791 {
 792         struct cortex_m_common *cortex_m = target_to_cm(target);
 793         struct armv7m_common *armv7m = &cortex_m->armv7m;
 794         struct adiv5_dap *swjdp = armv7m->arm.dap;
 795         struct breakpoint *breakpoint = NULL;
 796         struct reg *pc = armv7m->arm.pc;
 797         bool bkpt_inst_found = false;
 798         int retval;
 799         bool isr_timed_out = false;
 800
 801         if (target->state != TARGET_HALTED) {
 802                 LOG_WARNING("target not halted");
 803                 return ERROR_TARGET_NOT_HALTED;
 804         }
 805
 806         /* current = 1: continue on current pc, otherwise continue at <address> */
 807         if (!current)
 808                 buf_set_u32(pc->value, 0, 32, address);
 809
 810         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
 811
 812         /* the front-end may request us not to handle breakpoints */
 813         if (handle_breakpoints) {
 814                 breakpoint = breakpoint_find(target, pc_value);
 815                 if (breakpoint)
 816                         cortex_m_unset_breakpoint(target, breakpoint);
 817         }
 818
 819         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 820
 821         target->debug_reason = DBG_REASON_SINGLESTEP;
 822
 823         armv7m_restore_context(target);
 824
 825         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 826
 827         /* if no bkpt instruction is found at pc then we can perform
 828          * a normal step, otherwise we have to manually step over the bkpt
 829          * instruction - as such simulate a step */
 830         if (bkpt_inst_found == false) {
 831                 /* Automatic ISR masking mode off: Just step over the next instruction */
 832                 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
 833                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 834                 else {
 835                         /* Process interrupts during stepping in a way they don't interfere
 836                          * debugging.
 837                          *
 838                          * Principle:
 839                          *
 840                          * Set a temporary break point at the current pc and let the core run
 841                          * with interrupts enabled. Pending interrupts get served and we run
 842                          * into the breakpoint again afterwards. Then we step over the next
 843                          * instruction with interrupts disabled.
 844                          *
 845                          * If the pending interrupts don't complete within time, we leave the
 846                          * core running. This may happen if the interrupts trigger faster
 847                          * than the core can process them or the handler doesn't return.
 848                          *
 849                          * If no more breakpoints are available we simply do a step with
 850                          * interrupts enabled.
 851                          *
 852                          */
 853
 854                         /* 2012-09-29 ph
 855                          *
 856                          * If a break point is already set on the lower half word then a break point on
 857                          * the upper half word will not break again when the core is restarted. So we
 858                          * just step over the instruction with interrupts disabled.
 859                          *
 860                          * The documentation has no information about this, it was found by observation
 861                          * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
 862                          * suffer from this problem.
 863                          *
 864                          * To add some confusion: pc_value has bit 0 always set, while the breakpoint
 865                          * address has it always cleared. The former is done to indicate thumb mode
 866                          * to gdb.
 867                          *
 868                          */
 869                         if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
 870                                 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
 871                                 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
 872                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 873                                 /* Re-enable interrupts */
 874                                 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
 875                         }
 876                         else {
 877
 878                                 /* Set a temporary break point */
 879                                 if (breakpoint)
 880                                         retval = cortex_m_set_breakpoint(target, breakpoint);
 881                                 else
 882                                         retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value));
 883                                 bool tmp_bp_set = (retval == ERROR_OK);
 884
 885                                 /* No more breakpoints left, just do a step */
 886                                 if (!tmp_bp_set)
 887                                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 888                                 else {
 889                                         /* Start the core */
 890                                         LOG_DEBUG("Starting core to serve pending interrupts");
 891                                         int64_t t_start = timeval_ms();
 892                                         cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
 893
 894                                         /* Wait for pending handlers to complete or timeout */
 895                                         do {
 896                                                 retval = mem_ap_read_atomic_u32(swjdp,
 897                                                                 DCB_DHCSR,
 898                                                                 &cortex_m->dcb_dhcsr);
 899                                                 if (retval != ERROR_OK) {
 900                                                         target->state = TARGET_UNKNOWN;
 901                                                         return retval;
 902                                                 }
 903                                                 isr_timed_out = ((timeval_ms() - t_start) > 500);
 904                                         } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
 905
 906                                         /* only remove breakpoint if we created it */
 907                                         if (breakpoint)
 908                                                 cortex_m_unset_breakpoint(target, breakpoint);
 909                                         else {
 910                                                 /* Remove the temporary breakpoint */
 911                                                 breakpoint_remove(target, pc_value);
 912                                         }
 913
 914                                         if (isr_timed_out) {
 915                                                 LOG_DEBUG("Interrupt handlers didn't complete within time, "
 916                                                         "leaving target running");
 917                                         } else {
 918                                                 /* Step over next instruction with interrupts disabled */
 919                                                 cortex_m_write_debug_halt_mask(target,
 920                                                         C_HALT | C_MASKINTS,
 921                                                         0);
 922                                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 923                                                 /* Re-enable interrupts */
 924                                                 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
 925                                         }
 926                                 }
 927                         }
 928                 }
 929         }
 930
 931         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 932         if (retval != ERROR_OK)
 933                 return retval;
 934
 935         /* registers are now invalid */
 936         register_cache_invalidate(armv7m->arm.core_cache);
 937
 938         if (breakpoint)
 939                 cortex_m_set_breakpoint(target, breakpoint);
 940
 941         if (isr_timed_out) {
 942                 /* Leave the core running. The user has to stop execution manually. */
 943                 target->debug_reason = DBG_REASON_NOTHALTED;
 944                 target->state = TARGET_RUNNING;
 945                 return ERROR_OK;
 946         }
 947
 948         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 949                 " nvic_icsr = 0x%" PRIx32,
 950                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
 951
 952         retval = cortex_m_debug_entry(target);
 953         if (retval != ERROR_OK)
 954                 return retval;
 955         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 956
 957         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 958                 " nvic_icsr = 0x%" PRIx32,
 959                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
 960
 961         return ERROR_OK;
 962 }
 963
 964 static int cortex_m_assert_reset(struct target *target)
 965 {
 966         struct cortex_m_common *cortex_m = target_to_cm(target);
 967         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 968         enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
 969
 970         LOG_DEBUG("target->state: %s",
 971                 target_state_name(target));
 972
 973         enum reset_types jtag_reset_config = jtag_get_reset_config();
 974
 975         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
 976                 /* allow scripts to override the reset event */
 977
 978                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
 979                 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 980                 target->state = TARGET_RESET;
 981
 982                 return ERROR_OK;
 983         }
 984
 985         /* some cores support connecting while srst is asserted
 986          * use that mode is it has been configured */
 987
 988         bool srst_asserted = false;
 989
 990         if ((jtag_reset_config & RESET_HAS_SRST) &&
 991             (jtag_reset_config & RESET_SRST_NO_GATING)) {
 992                 adapter_assert_reset();
 993                 srst_asserted = true;
 994         }
 995
 996         /* Enable debug requests */
 997         int retval;
 998         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 999         if (retval != ERROR_OK)
1000                 return retval;
1001         if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
1002                 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
1003                 if (retval != ERROR_OK)
1004                         return retval;
1005         }
1006
1007         /* If the processor is sleeping in a WFI or WFE instruction, the
1008          * C_HALT bit must be asserted to regain control */
1009         if (cortex_m->dcb_dhcsr & S_SLEEP) {
1010                 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1011                 if (retval != ERROR_OK)
1012                         return retval;
1013         }
1014
1015         retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
1016         if (retval != ERROR_OK)
1017                 return retval;
1018
1019         if (!target->reset_halt) {
1020                 /* Set/Clear C_MASKINTS in a separate operation */
1021                 if (cortex_m->dcb_dhcsr & C_MASKINTS) {
1022                         retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
1023                                         DBGKEY | C_DEBUGEN | C_HALT);
1024                         if (retval != ERROR_OK)
1025                                 return retval;
1026                 }
1027
1028                 /* clear any debug flags before resuming */
1029                 cortex_m_clear_halt(target);
1030
1031                 /* clear C_HALT in dhcsr reg */
1032                 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1033         } else {
1034                 /* Halt in debug on reset; endreset_event() restores DEMCR.
1035                  *
1036                  * REVISIT catching BUSERR presumably helps to defend against
1037                  * bad vector table entries.  Should this include MMERR or
1038                  * other flags too?
1039                  */
1040                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
1041                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1042                 if (retval != ERROR_OK)
1043                         return retval;
1044         }
1045
1046         if (jtag_reset_config & RESET_HAS_SRST) {
1047                 /* default to asserting srst */
1048                 if (!srst_asserted)
1049                         adapter_assert_reset();
1050         } else {
1051                 /* Use a standard Cortex-M3 software reset mechanism.
1052                  * We default to using VECRESET as it is supported on all current cores.
1053                  * This has the disadvantage of not resetting the peripherals, so a
1054                  * reset-init event handler is needed to perform any peripheral resets.
1055                  */
1056                 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
1057                                 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1058                                 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1059                 if (retval != ERROR_OK)
1060                         return retval;
1061
1062                 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1063                         ? "SYSRESETREQ" : "VECTRESET");
1064
1065                 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1066                         LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1067                                 "handler to reset any peripherals or configure hardware srst support.");
1068                 }
1069
1070                 /*
1071                   SAM4L needs to execute security initalization
1072                   startup sequence before AP access would be enabled.
1073                   During the intialization CDBGPWRUPACK is pulled low and we
1074                   need to wait for it to be set to 1 again.
1075                 */
1076                 retval = dap_dp_poll_register(swjdp, DP_CTRL_STAT,
1077                                               CDBGPWRUPACK, CDBGPWRUPACK, 100);
1078                 if (retval != ERROR_OK) {
1079                         LOG_ERROR("Failed waitnig for CDBGPWRUPACK");
1080                         return ERROR_FAIL;
1081                 }
1082
1083                 {
1084                         /* I do not know why this is necessary, but it
1085                          * fixes strange effects (step/resume cause NMI
1086                          * after reset) on LM3S6918 -- Michael Schwingen
1087                          */
1088                         uint32_t tmp;
1089                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
1090                         if (retval != ERROR_OK)
1091                                 return retval;
1092                 }
1093         }
1094
1095         target->state = TARGET_RESET;
1096         jtag_add_sleep(50000);
1097
1098         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1099
1100         if (target->reset_halt) {
1101                 retval = target_halt(target);
1102                 if (retval != ERROR_OK)
1103                         return retval;
1104         }
1105
1106         return ERROR_OK;
1107 }
1108
1109 static int cortex_m_deassert_reset(struct target *target)
1110 {
1111         LOG_DEBUG("target->state: %s",
1112                 target_state_name(target));
1113
1114         /* deassert reset lines */
1115         adapter_deassert_reset();
1116
1117         return ERROR_OK;
1118 }
1119
1120 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1121 {
1122         int retval;
1123         int fp_num = 0;
1124         uint32_t hilo;
1125         struct cortex_m_common *cortex_m = target_to_cm(target);
1126         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1127
1128         if (breakpoint->set) {
1129                 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1130                 return ERROR_OK;
1131         }
1132
1133         if (cortex_m->auto_bp_type)
1134                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1135
1136         if (breakpoint->type == BKPT_HARD) {
1137                 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1138                         fp_num++;
1139                 if (fp_num >= cortex_m->fp_num_code) {
1140                         LOG_ERROR("Can not find free FPB Comparator!");
1141                         return ERROR_FAIL;
1142                 }
1143                 breakpoint->set = fp_num + 1;
1144                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1145                 comparator_list[fp_num].used = 1;
1146                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1147                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1148                         comparator_list[fp_num].fpcr_value);
1149                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1150                         fp_num,
1151                         comparator_list[fp_num].fpcr_value);
1152                 if (!cortex_m->fpb_enabled) {
1153                         LOG_DEBUG("FPB wasn't enabled, do it now");
1154                         retval = cortex_m_enable_fpb(target);
1155                         if (retval != ERROR_OK) {
1156                                 LOG_ERROR("Failed to enable the FPB");
1157                                 return retval;
1158                         }
1159
1160                         cortex_m->fpb_enabled = 1;
1161                 }
1162         } else if (breakpoint->type == BKPT_SOFT) {
1163                 uint8_t code[4];
1164
1165                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1166                  * semihosting; don't use that.  Otherwise the BKPT
1167                  * parameter is arbitrary.
1168                  */
1169                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1170                 retval = target_read_memory(target,
1171                                 breakpoint->address & 0xFFFFFFFE,
1172                                 breakpoint->length, 1,
1173                                 breakpoint->orig_instr);
1174                 if (retval != ERROR_OK)
1175                         return retval;
1176                 retval = target_write_memory(target,
1177                                 breakpoint->address & 0xFFFFFFFE,
1178                                 breakpoint->length, 1,
1179                                 code);
1180                 if (retval != ERROR_OK)
1181                         return retval;
1182                 breakpoint->set = true;
1183         }
1184
1185         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1186                 breakpoint->unique_id,
1187                 (int)(breakpoint->type),
1188                 breakpoint->address,
1189                 breakpoint->length,
1190                 breakpoint->set);
1191
1192         return ERROR_OK;
1193 }
1194
1195 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1196 {
1197         int retval;
1198         struct cortex_m_common *cortex_m = target_to_cm(target);
1199         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1200
1201         if (!breakpoint->set) {
1202                 LOG_WARNING("breakpoint not set");
1203                 return ERROR_OK;
1204         }
1205
1206         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1207                 breakpoint->unique_id,
1208                 (int)(breakpoint->type),
1209                 breakpoint->address,
1210                 breakpoint->length,
1211                 breakpoint->set);
1212
1213         if (breakpoint->type == BKPT_HARD) {
1214                 int fp_num = breakpoint->set - 1;
1215                 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1216                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1217                         return ERROR_OK;
1218                 }
1219                 comparator_list[fp_num].used = 0;
1220                 comparator_list[fp_num].fpcr_value = 0;
1221                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1222                         comparator_list[fp_num].fpcr_value);
1223         } else {
1224                 /* restore original instruction (kept in target endianness) */
1225                 if (breakpoint->length == 4) {
1226                         retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1227                                         breakpoint->orig_instr);
1228                         if (retval != ERROR_OK)
1229                                 return retval;
1230                 } else {
1231                         retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1232                                         breakpoint->orig_instr);
1233                         if (retval != ERROR_OK)
1234                                 return retval;
1235                 }
1236         }
1237         breakpoint->set = false;
1238
1239         return ERROR_OK;
1240 }
1241
1242 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1243 {
1244         struct cortex_m_common *cortex_m = target_to_cm(target);
1245
1246         if (cortex_m->auto_bp_type)
1247                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1248
1249         if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
1250                 if (breakpoint->type == BKPT_HARD) {
1251                         LOG_INFO("flash patch comparator requested outside code memory region");
1252                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1253                 }
1254
1255                 if (breakpoint->type == BKPT_SOFT) {
1256                         LOG_INFO("soft breakpoint requested in code (flash) memory region");
1257                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1258                 }
1259         }
1260
1261         if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
1262                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1263                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1264         }
1265
1266         if (breakpoint->length == 3) {
1267                 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1268                 breakpoint->length = 2;
1269         }
1270
1271         if ((breakpoint->length != 2)) {
1272                 LOG_INFO("only breakpoints of two bytes length supported");
1273                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1274         }
1275
1276         if (breakpoint->type == BKPT_HARD)
1277                 cortex_m->fp_code_available--;
1278
1279         return cortex_m_set_breakpoint(target, breakpoint);
1280 }
1281
1282 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1283 {
1284         struct cortex_m_common *cortex_m = target_to_cm(target);
1285
1286         /* REVISIT why check? FBP can be updated with core running ... */
1287         if (target->state != TARGET_HALTED) {
1288                 LOG_WARNING("target not halted");
1289                 return ERROR_TARGET_NOT_HALTED;
1290         }
1291
1292         if (cortex_m->auto_bp_type)
1293                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1294
1295         if (breakpoint->set)
1296                 cortex_m_unset_breakpoint(target, breakpoint);
1297
1298         if (breakpoint->type == BKPT_HARD)
1299                 cortex_m->fp_code_available++;
1300
1301         return ERROR_OK;
1302 }
1303
1304 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1305 {
1306         int dwt_num = 0;
1307         uint32_t mask, temp;
1308         struct cortex_m_common *cortex_m = target_to_cm(target);
1309
1310         /* watchpoint params were validated earlier */
1311         mask = 0;
1312         temp = watchpoint->length;
1313         while (temp) {
1314                 temp >>= 1;
1315                 mask++;
1316         }
1317         mask--;
1318
1319         /* REVISIT Don't fully trust these "not used" records ... users
1320          * may set up breakpoints by hand, e.g. dual-address data value
1321          * watchpoint using comparator #1; comparator #0 matching cycle
1322          * count; send data trace info through ITM and TPIU; etc
1323          */
1324         struct cortex_m_dwt_comparator *comparator;
1325
1326         for (comparator = cortex_m->dwt_comparator_list;
1327                 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1328                 comparator++, dwt_num++)
1329                 continue;
1330         if (dwt_num >= cortex_m->dwt_num_comp) {
1331                 LOG_ERROR("Can not find free DWT Comparator");
1332                 return ERROR_FAIL;
1333         }
1334         comparator->used = 1;
1335         watchpoint->set = dwt_num + 1;
1336
1337         comparator->comp = watchpoint->address;
1338         target_write_u32(target, comparator->dwt_comparator_address + 0,
1339                 comparator->comp);
1340
1341         comparator->mask = mask;
1342         target_write_u32(target, comparator->dwt_comparator_address + 4,
1343                 comparator->mask);
1344
1345         switch (watchpoint->rw) {
1346                 case WPT_READ:
1347                         comparator->function = 5;
1348                         break;
1349                 case WPT_WRITE:
1350                         comparator->function = 6;
1351                         break;
1352                 case WPT_ACCESS:
1353                         comparator->function = 7;
1354                         break;
1355         }
1356         target_write_u32(target, comparator->dwt_comparator_address + 8,
1357                 comparator->function);
1358
1359         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1360                 watchpoint->unique_id, dwt_num,
1361                 (unsigned) comparator->comp,
1362                 (unsigned) comparator->mask,
1363                 (unsigned) comparator->function);
1364         return ERROR_OK;
1365 }
1366
1367 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1368 {
1369         struct cortex_m_common *cortex_m = target_to_cm(target);
1370         struct cortex_m_dwt_comparator *comparator;
1371         int dwt_num;
1372
1373         if (!watchpoint->set) {
1374                 LOG_WARNING("watchpoint (wpid: %d) not set",
1375                         watchpoint->unique_id);
1376                 return ERROR_OK;
1377         }
1378
1379         dwt_num = watchpoint->set - 1;
1380
1381         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1382                 watchpoint->unique_id, dwt_num,
1383                 (unsigned) watchpoint->address);
1384
1385         if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1386                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1387                 return ERROR_OK;
1388         }
1389
1390         comparator = cortex_m->dwt_comparator_list + dwt_num;
1391         comparator->used = 0;
1392         comparator->function = 0;
1393         target_write_u32(target, comparator->dwt_comparator_address + 8,
1394                 comparator->function);
1395
1396         watchpoint->set = false;
1397
1398         return ERROR_OK;
1399 }
1400
1401 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1402 {
1403         struct cortex_m_common *cortex_m = target_to_cm(target);
1404
1405         if (cortex_m->dwt_comp_available < 1) {
1406                 LOG_DEBUG("no comparators?");
1407                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1408         }
1409
1410         /* hardware doesn't support data value masking */
1411         if (watchpoint->mask != ~(uint32_t)0) {
1412                 LOG_DEBUG("watchpoint value masks not supported");
1413                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1414         }
1415
1416         /* hardware allows address masks of up to 32K */
1417         unsigned mask;
1418
1419         for (mask = 0; mask < 16; mask++) {
1420                 if ((1u << mask) == watchpoint->length)
1421                         break;
1422         }
1423         if (mask == 16) {
1424                 LOG_DEBUG("unsupported watchpoint length");
1425                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1426         }
1427         if (watchpoint->address & ((1 << mask) - 1)) {
1428                 LOG_DEBUG("watchpoint address is unaligned");
1429                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1430         }
1431
1432         /* Caller doesn't seem to be able to describe watching for data
1433          * values of zero; that flags "no value".
1434          *
1435          * REVISIT This DWT may well be able to watch for specific data
1436          * values.  Requires comparator #1 to set DATAVMATCH and match
1437          * the data, and another comparator (DATAVADDR0) matching addr.
1438          */
1439         if (watchpoint->value) {
1440                 LOG_DEBUG("data value watchpoint not YET supported");
1441                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1442         }
1443
1444         cortex_m->dwt_comp_available--;
1445         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1446
1447         return ERROR_OK;
1448 }
1449
1450 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1451 {
1452         struct cortex_m_common *cortex_m = target_to_cm(target);
1453
1454         /* REVISIT why check? DWT can be updated with core running ... */
1455         if (target->state != TARGET_HALTED) {
1456                 LOG_WARNING("target not halted");
1457                 return ERROR_TARGET_NOT_HALTED;
1458         }
1459
1460         if (watchpoint->set)
1461                 cortex_m_unset_watchpoint(target, watchpoint);
1462
1463         cortex_m->dwt_comp_available++;
1464         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1465
1466         return ERROR_OK;
1467 }
1468
1469 void cortex_m_enable_watchpoints(struct target *target)
1470 {
1471         struct watchpoint *watchpoint = target->watchpoints;
1472
1473         /* set any pending watchpoints */
1474         while (watchpoint) {
1475                 if (!watchpoint->set)
1476                         cortex_m_set_watchpoint(target, watchpoint);
1477                 watchpoint = watchpoint->next;
1478         }
1479 }
1480
1481 static int cortex_m_load_core_reg_u32(struct target *target,
1482                 uint32_t num, uint32_t *value)
1483 {
1484         int retval;
1485
1486         /* NOTE:  we "know" here that the register identifiers used
1487          * in the v7m header match the Cortex-M3 Debug Core Register
1488          * Selector values for R0..R15, xPSR, MSP, and PSP.
1489          */
1490         switch (num) {
1491                 case 0 ... 18:
1492                         /* read a normal core register */
1493                         retval = cortexm_dap_read_coreregister_u32(target, value, num);
1494
1495                         if (retval != ERROR_OK) {
1496                                 LOG_ERROR("JTAG failure %i", retval);
1497                                 return ERROR_JTAG_DEVICE_ERROR;
1498                         }
1499                         LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
1500                         break;
1501
1502                 case ARMV7M_FPSCR:
1503                         /* Floating-point Status and Registers */
1504                         retval = target_write_u32(target, DCB_DCRSR, 0x21);
1505                         if (retval != ERROR_OK)
1506                                 return retval;
1507                         retval = target_read_u32(target, DCB_DCRDR, value);
1508                         if (retval != ERROR_OK)
1509                                 return retval;
1510                         LOG_DEBUG("load from FPSCR  value 0x%" PRIx32, *value);
1511                         break;
1512
1513                 case ARMV7M_S0 ... ARMV7M_S31:
1514                         /* Floating-point Status and Registers */
1515                         retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1516                         if (retval != ERROR_OK)
1517                                 return retval;
1518                         retval = target_read_u32(target, DCB_DCRDR, value);
1519                         if (retval != ERROR_OK)
1520                                 return retval;
1521                         LOG_DEBUG("load from FPU reg S%d  value 0x%" PRIx32,
1522                                   (int)(num - ARMV7M_S0), *value);
1523                         break;
1524
1525                 case ARMV7M_PRIMASK:
1526                 case ARMV7M_BASEPRI:
1527                 case ARMV7M_FAULTMASK:
1528                 case ARMV7M_CONTROL:
1529                         /* Cortex-M3 packages these four registers as bitfields
1530                          * in one Debug Core register.  So say r0 and r2 docs;
1531                          * it was removed from r1 docs, but still works.
1532                          */
1533                         cortexm_dap_read_coreregister_u32(target, value, 20);
1534
1535                         switch (num) {
1536                                 case ARMV7M_PRIMASK:
1537                                         *value = buf_get_u32((uint8_t *)value, 0, 1);
1538                                         break;
1539
1540                                 case ARMV7M_BASEPRI:
1541                                         *value = buf_get_u32((uint8_t *)value, 8, 8);
1542                                         break;
1543
1544                                 case ARMV7M_FAULTMASK:
1545                                         *value = buf_get_u32((uint8_t *)value, 16, 1);
1546                                         break;
1547
1548                                 case ARMV7M_CONTROL:
1549                                         *value = buf_get_u32((uint8_t *)value, 24, 2);
1550                                         break;
1551                         }
1552
1553                         LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1554                         break;
1555
1556                 default:
1557                         return ERROR_COMMAND_SYNTAX_ERROR;
1558         }
1559
1560         return ERROR_OK;
1561 }
1562
1563 static int cortex_m_store_core_reg_u32(struct target *target,
1564                 uint32_t num, uint32_t value)
1565 {
1566         int retval;
1567         uint32_t reg;
1568         struct armv7m_common *armv7m = target_to_armv7m(target);
1569
1570         /* NOTE:  we "know" here that the register identifiers used
1571          * in the v7m header match the Cortex-M3 Debug Core Register
1572          * Selector values for R0..R15, xPSR, MSP, and PSP.
1573          */
1574         switch (num) {
1575                 case 0 ... 18:
1576                         retval = cortexm_dap_write_coreregister_u32(target, value, num);
1577                         if (retval != ERROR_OK) {
1578                                 struct reg *r;
1579
1580                                 LOG_ERROR("JTAG failure");
1581                                 r = armv7m->arm.core_cache->reg_list + num;
1582                                 r->dirty = r->valid;
1583                                 return ERROR_JTAG_DEVICE_ERROR;
1584                         }
1585                         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1586                         break;
1587
1588                 case ARMV7M_FPSCR:
1589                         /* Floating-point Status and Registers */
1590                         retval = target_write_u32(target, DCB_DCRDR, value);
1591                         if (retval != ERROR_OK)
1592                                 return retval;
1593                         retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1594                         if (retval != ERROR_OK)
1595                                 return retval;
1596                         LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1597                         break;
1598
1599                 case ARMV7M_S0 ... ARMV7M_S31:
1600                         /* Floating-point Status and Registers */
1601                         retval = target_write_u32(target, DCB_DCRDR, value);
1602                         if (retval != ERROR_OK)
1603                                 return retval;
1604                         retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1605                         if (retval != ERROR_OK)
1606                                 return retval;
1607                         LOG_DEBUG("write FPU reg S%d  value 0x%" PRIx32,
1608                                   (int)(num - ARMV7M_S0), value);
1609                         break;
1610
1611                 case ARMV7M_PRIMASK:
1612                 case ARMV7M_BASEPRI:
1613                 case ARMV7M_FAULTMASK:
1614                 case ARMV7M_CONTROL:
1615                         /* Cortex-M3 packages these four registers as bitfields
1616                          * in one Debug Core register.  So say r0 and r2 docs;
1617                          * it was removed from r1 docs, but still works.
1618                          */
1619                         cortexm_dap_read_coreregister_u32(target, &reg, 20);
1620
1621                         switch (num) {
1622                                 case ARMV7M_PRIMASK:
1623                                         buf_set_u32((uint8_t *)&reg, 0, 1, value);
1624                                         break;
1625
1626                                 case ARMV7M_BASEPRI:
1627                                         buf_set_u32((uint8_t *)&reg, 8, 8, value);
1628                                         break;
1629
1630                                 case ARMV7M_FAULTMASK:
1631                                         buf_set_u32((uint8_t *)&reg, 16, 1, value);
1632                                         break;
1633
1634                                 case ARMV7M_CONTROL:
1635                                         buf_set_u32((uint8_t *)&reg, 24, 2, value);
1636                                         break;
1637                         }
1638
1639                         cortexm_dap_write_coreregister_u32(target, reg, 20);
1640
1641                         LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1642                         break;
1643
1644                 default:
1645                         return ERROR_COMMAND_SYNTAX_ERROR;
1646         }
1647
1648         return ERROR_OK;
1649 }
1650
1651 static int cortex_m_read_memory(struct target *target, uint32_t address,
1652         uint32_t size, uint32_t count, uint8_t *buffer)
1653 {
1654         struct armv7m_common *armv7m = target_to_armv7m(target);
1655         struct adiv5_dap *swjdp = armv7m->arm.dap;
1656
1657         if (armv7m->arm.is_armv6m) {
1658                 /* armv6m does not handle unaligned memory access */
1659                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1660                         return ERROR_TARGET_UNALIGNED_ACCESS;
1661         }
1662
1663         return mem_ap_read(swjdp, buffer, size, count, address, true);
1664 }
1665
1666 static int cortex_m_write_memory(struct target *target, uint32_t address,
1667         uint32_t size, uint32_t count, const uint8_t *buffer)
1668 {
1669         struct armv7m_common *armv7m = target_to_armv7m(target);
1670         struct adiv5_dap *swjdp = armv7m->arm.dap;
1671
1672         if (armv7m->arm.is_armv6m) {
1673                 /* armv6m does not handle unaligned memory access */
1674                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1675                         return ERROR_TARGET_UNALIGNED_ACCESS;
1676         }
1677
1678         return mem_ap_write(swjdp, buffer, size, count, address, true);
1679 }
1680
1681 static int cortex_m_init_target(struct command_context *cmd_ctx,
1682         struct target *target)
1683 {
1684         armv7m_build_reg_cache(target);
1685         return ERROR_OK;
1686 }
1687
1688 void cortex_m_deinit_target(struct target *target)
1689 {
1690         struct cortex_m_common *cortex_m = target_to_cm(target);
1691
1692         free(cortex_m->fp_comparator_list);
1693         cortex_m_dwt_free(target);
1694         free(cortex_m);
1695 }
1696
1697 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1698  * on r/w if the core is not running, and clear on resume or reset ... or
1699  * at least, in a post_restore_context() method.
1700  */
1701
1702 struct dwt_reg_state {
1703         struct target *target;
1704         uint32_t addr;
1705         uint8_t value[4];               /* scratch/cache */
1706 };
1707
1708 static int cortex_m_dwt_get_reg(struct reg *reg)
1709 {
1710         struct dwt_reg_state *state = reg->arch_info;
1711
1712         uint32_t tmp;
1713         int retval = target_read_u32(state->target, state->addr, &tmp);
1714         if (retval != ERROR_OK)
1715                 return retval;
1716
1717         buf_set_u32(state->value, 0, 32, tmp);
1718         return ERROR_OK;
1719 }
1720
1721 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1722 {
1723         struct dwt_reg_state *state = reg->arch_info;
1724
1725         return target_write_u32(state->target, state->addr,
1726                         buf_get_u32(buf, 0, reg->size));
1727 }
1728
1729 struct dwt_reg {
1730         uint32_t addr;
1731         char *name;
1732         unsigned size;
1733 };
1734
1735 static struct dwt_reg dwt_base_regs[] = {
1736         { DWT_CTRL, "dwt_ctrl", 32, },
1737         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1738          * increments while the core is asleep.
1739          */
1740         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1741         /* plus some 8 bit counters, useful for profiling with TPIU */
1742 };
1743
1744 static struct dwt_reg dwt_comp[] = {
1745 #define DWT_COMPARATOR(i) \
1746                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1747                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1748                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1749         DWT_COMPARATOR(0),
1750         DWT_COMPARATOR(1),
1751         DWT_COMPARATOR(2),
1752         DWT_COMPARATOR(3),
1753 #undef DWT_COMPARATOR
1754 };
1755
1756 static const struct reg_arch_type dwt_reg_type = {
1757         .get = cortex_m_dwt_get_reg,
1758         .set = cortex_m_dwt_set_reg,
1759 };
1760
1761 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1762 {
1763         struct dwt_reg_state *state;
1764
1765         state = calloc(1, sizeof *state);
1766         if (!state)
1767                 return;
1768         state->addr = d->addr;
1769         state->target = t;
1770
1771         r->name = d->name;
1772         r->size = d->size;
1773         r->value = state->value;
1774         r->arch_info = state;
1775         r->type = &dwt_reg_type;
1776 }
1777
1778 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1779 {
1780         uint32_t dwtcr;
1781         struct reg_cache *cache;
1782         struct cortex_m_dwt_comparator *comparator;
1783         int reg, i;
1784
1785         target_read_u32(target, DWT_CTRL, &dwtcr);
1786         if (!dwtcr) {
1787                 LOG_DEBUG("no DWT");
1788                 return;
1789         }
1790
1791         cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1792         cm->dwt_comp_available = cm->dwt_num_comp;
1793         cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1794                         sizeof(struct cortex_m_dwt_comparator));
1795         if (!cm->dwt_comparator_list) {
1796 fail0:
1797                 cm->dwt_num_comp = 0;
1798                 LOG_ERROR("out of mem");
1799                 return;
1800         }
1801
1802         cache = calloc(1, sizeof *cache);
1803         if (!cache) {
1804 fail1:
1805                 free(cm->dwt_comparator_list);
1806                 goto fail0;
1807         }
1808         cache->name = "Cortex-M DWT registers";
1809         cache->num_regs = 2 + cm->dwt_num_comp * 3;
1810         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1811         if (!cache->reg_list) {
1812                 free(cache);
1813                 goto fail1;
1814         }
1815
1816         for (reg = 0; reg < 2; reg++)
1817                 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1818                         dwt_base_regs + reg);
1819
1820         comparator = cm->dwt_comparator_list;
1821         for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1822                 int j;
1823
1824                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1825                 for (j = 0; j < 3; j++, reg++)
1826                         cortex_m_dwt_addreg(target, cache->reg_list + reg,
1827                                 dwt_comp + 3 * i + j);
1828
1829                 /* make sure we clear any watchpoints enabled on the target */
1830                 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1831         }
1832
1833         *register_get_last_cache_p(&target->reg_cache) = cache;
1834         cm->dwt_cache = cache;
1835
1836         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1837                 dwtcr, cm->dwt_num_comp,
1838                 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1839
1840         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1841          * implement single-address data value watchpoints ... so we
1842          * won't need to check it later, when asked to set one up.
1843          */
1844 }
1845
1846 static void cortex_m_dwt_free(struct target *target)
1847 {
1848         struct cortex_m_common *cm = target_to_cm(target);
1849         struct reg_cache *cache = cm->dwt_cache;
1850
1851         free(cm->dwt_comparator_list);
1852         cm->dwt_comparator_list = NULL;
1853
1854         if (cache) {
1855                 register_unlink_cache(&target->reg_cache, cache);
1856
1857                 if (cache->reg_list) {
1858                         for (size_t i = 0; i < cache->num_regs; i++)
1859                                 free(cache->reg_list[i].arch_info);
1860                         free(cache->reg_list);
1861                 }
1862                 free(cache);
1863         }
1864         cm->dwt_cache = NULL;
1865 }
1866
1867 #define MVFR0 0xe000ef40
1868 #define MVFR1 0xe000ef44
1869
1870 #define MVFR0_DEFAULT_M4 0x10110021
1871 #define MVFR1_DEFAULT_M4 0x11000011
1872
1873 int cortex_m_examine(struct target *target)
1874 {
1875         int retval;
1876         uint32_t cpuid, fpcr, mvfr0, mvfr1;
1877         int i;
1878         struct cortex_m_common *cortex_m = target_to_cm(target);
1879         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1880         struct armv7m_common *armv7m = target_to_armv7m(target);
1881
1882         /* stlink shares the examine handler but does not support
1883          * all its calls */
1884         if (!armv7m->stlink) {
1885                 retval = ahbap_debugport_init(swjdp);
1886                 if (retval != ERROR_OK)
1887                         return retval;
1888         }
1889
1890         if (!target_was_examined(target)) {
1891                 target_set_examined(target);
1892
1893                 /* Read from Device Identification Registers */
1894                 retval = target_read_u32(target, CPUID, &cpuid);
1895                 if (retval != ERROR_OK)
1896                         return retval;
1897
1898                 /* Get CPU Type */
1899                 i = (cpuid >> 4) & 0xf;
1900
1901                 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
1902                                 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1903                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1904
1905                 /* test for floating point feature on cortex-m4 */
1906                 if (i == 4) {
1907                         target_read_u32(target, MVFR0, &mvfr0);
1908                         target_read_u32(target, MVFR1, &mvfr1);
1909
1910                         if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
1911                                 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
1912                                 armv7m->fp_feature = FPv4_SP;
1913                         }
1914                 } else if (i == 0) {
1915                         /* Cortex-M0 does not support unaligned memory access */
1916                         armv7m->arm.is_armv6m = true;
1917                 }
1918
1919                 if (armv7m->fp_feature != FPv4_SP &&
1920                     armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
1921                         /* free unavailable FPU registers */
1922                         size_t idx;
1923                         for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
1924                              idx < armv7m->arm.core_cache->num_regs;
1925                              idx++)
1926                                 free(armv7m->arm.core_cache->reg_list[idx].value);
1927                         armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
1928                 }
1929
1930                 if (i == 4 || i == 3) {
1931                         /* Cortex-M3/M4 has 4096 bytes autoincrement range */
1932                         armv7m->dap.tar_autoincr_block = (1 << 12);
1933                 }
1934
1935                 /* NOTE: FPB and DWT are both optional. */
1936
1937                 /* Setup FPB */
1938                 target_read_u32(target, FP_CTRL, &fpcr);
1939                 cortex_m->auto_bp_type = 1;
1940                 /* bits [14:12] and [7:4] */
1941                 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
1942                 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
1943                 cortex_m->fp_code_available = cortex_m->fp_num_code;
1944                 free(cortex_m->fp_comparator_list);
1945                 cortex_m->fp_comparator_list = calloc(
1946                                 cortex_m->fp_num_code + cortex_m->fp_num_lit,
1947                                 sizeof(struct cortex_m_fp_comparator));
1948                 cortex_m->fpb_enabled = fpcr & 1;
1949                 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
1950                         cortex_m->fp_comparator_list[i].type =
1951                                 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1952                         cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1953
1954                         /* make sure we clear any breakpoints enabled on the target */
1955                         target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
1956                 }
1957                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
1958                         fpcr,
1959                         cortex_m->fp_num_code,
1960                         cortex_m->fp_num_lit);
1961
1962                 /* Setup DWT */
1963                 cortex_m_dwt_free(target);
1964                 cortex_m_dwt_setup(cortex_m, target);
1965
1966                 /* These hardware breakpoints only work for code in flash! */
1967                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1968                         target_name(target),
1969                         cortex_m->fp_num_code,
1970                         cortex_m->dwt_num_comp);
1971         }
1972
1973         return ERROR_OK;
1974 }
1975
1976 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
1977 {
1978         struct armv7m_common *armv7m = target_to_armv7m(target);
1979         struct adiv5_dap *swjdp = armv7m->arm.dap;
1980         uint16_t dcrdr;
1981         uint8_t buf[2];
1982         int retval;
1983
1984         retval = mem_ap_read(swjdp, buf, 2, 1, DCB_DCRDR, false);
1985         if (retval != ERROR_OK)
1986                 return retval;
1987
1988         dcrdr = target_buffer_get_u16(target, buf);
1989         *ctrl = (uint8_t)dcrdr;
1990         *value = (uint8_t)(dcrdr >> 8);
1991
1992         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1993
1994         /* write ack back to software dcc register
1995          * signify we have read data */
1996         if (dcrdr & (1 << 0)) {
1997                 target_buffer_set_u16(target, buf, 0);
1998                 retval = mem_ap_write(swjdp, buf, 2, 1, DCB_DCRDR, false);
1999                 if (retval != ERROR_OK)
2000                         return retval;
2001         }
2002
2003         return ERROR_OK;
2004 }
2005
2006 static int cortex_m_target_request_data(struct target *target,
2007         uint32_t size, uint8_t *buffer)
2008 {
2009         uint8_t data;
2010         uint8_t ctrl;
2011         uint32_t i;
2012
2013         for (i = 0; i < (size * 4); i++) {
2014                 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2015                 if (retval != ERROR_OK)
2016                         return retval;
2017                 buffer[i] = data;
2018         }
2019
2020         return ERROR_OK;
2021 }
2022
2023 static int cortex_m_handle_target_request(void *priv)
2024 {
2025         struct target *target = priv;
2026         if (!target_was_examined(target))
2027                 return ERROR_OK;
2028
2029         if (!target->dbg_msg_enabled)
2030                 return ERROR_OK;
2031
2032         if (target->state == TARGET_RUNNING) {
2033                 uint8_t data;
2034                 uint8_t ctrl;
2035                 int retval;
2036
2037                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2038                 if (retval != ERROR_OK)
2039                         return retval;
2040
2041                 /* check if we have data */
2042                 if (ctrl & (1 << 0)) {
2043                         uint32_t request;
2044
2045                         /* we assume target is quick enough */
2046                         request = data;
2047                         for (int i = 1; i <= 3; i++) {
2048                                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2049                                 if (retval != ERROR_OK)
2050                                         return retval;
2051                                 request |= ((uint32_t)data << (i * 8));
2052                         }
2053                         target_request(target, request);
2054                 }
2055         }
2056
2057         return ERROR_OK;
2058 }
2059
2060 static int cortex_m_init_arch_info(struct target *target,
2061         struct cortex_m_common *cortex_m, struct jtag_tap *tap)
2062 {
2063         int retval;
2064         struct armv7m_common *armv7m = &cortex_m->armv7m;
2065
2066         armv7m_init_arch_info(target, armv7m);
2067
2068         /* prepare JTAG information for the new target */
2069         cortex_m->jtag_info.tap = tap;
2070         cortex_m->jtag_info.scann_size = 4;
2071
2072         /* default reset mode is to use srst if fitted
2073          * if not it will use CORTEX_M3_RESET_VECTRESET */
2074         cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2075
2076         armv7m->arm.dap = &armv7m->dap;
2077
2078         /* Leave (only) generic DAP stuff for debugport_init(); */
2079         armv7m->dap.jtag_info = &cortex_m->jtag_info;
2080         armv7m->dap.memaccess_tck = 8;
2081
2082         /* Cortex-M3/M4 has 4096 bytes autoincrement range
2083          * but set a safe default to 1024 to support Cortex-M0
2084          * this will be changed in cortex_m3_examine if a M3/M4 is detected */
2085         armv7m->dap.tar_autoincr_block = (1 << 10);
2086
2087         /* register arch-specific functions */
2088         armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2089
2090         armv7m->post_debug_entry = NULL;
2091
2092         armv7m->pre_restore_context = NULL;
2093
2094         armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2095         armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2096
2097         target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
2098
2099         retval = arm_jtag_setup_connection(&cortex_m->jtag_info);
2100         if (retval != ERROR_OK)
2101                 return retval;
2102
2103         return ERROR_OK;
2104 }
2105
2106 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2107 {
2108         struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2109
2110         cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2111         cortex_m_init_arch_info(target, cortex_m, target->tap);
2112
2113         return ERROR_OK;
2114 }
2115
2116 /*--------------------------------------------------------------------------*/
2117
2118 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2119         struct cortex_m_common *cm)
2120 {
2121         if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2122                 command_print(cmd_ctx, "target is not a Cortex-M");
2123                 return ERROR_TARGET_INVALID;
2124         }
2125         return ERROR_OK;
2126 }
2127
2128 /*
2129  * Only stuff below this line should need to verify that its target
2130  * is a Cortex-M3.  Everything else should have indirected through the
2131  * cortexm3_target structure, which is only used with CM3 targets.
2132  */
2133
2134 static const struct {
2135         char name[10];
2136         unsigned mask;
2137 } vec_ids[] = {
2138         { "hard_err",   VC_HARDERR, },
2139         { "int_err",    VC_INTERR, },
2140         { "bus_err",    VC_BUSERR, },
2141         { "state_err",  VC_STATERR, },
2142         { "chk_err",    VC_CHKERR, },
2143         { "nocp_err",   VC_NOCPERR, },
2144         { "mm_err",     VC_MMERR, },
2145         { "reset",      VC_CORERESET, },
2146 };
2147
2148 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2149 {
2150         struct target *target = get_current_target(CMD_CTX);
2151         struct cortex_m_common *cortex_m = target_to_cm(target);
2152         struct armv7m_common *armv7m = &cortex_m->armv7m;
2153         struct adiv5_dap *swjdp = armv7m->arm.dap;
2154         uint32_t demcr = 0;
2155         int retval;
2156
2157         retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2158         if (retval != ERROR_OK)
2159                 return retval;
2160
2161         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2162         if (retval != ERROR_OK)
2163                 return retval;
2164
2165         if (CMD_ARGC > 0) {
2166                 unsigned catch = 0;
2167
2168                 if (CMD_ARGC == 1) {
2169                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2170                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2171                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2172                                         | VC_MMERR | VC_CORERESET;
2173                                 goto write;
2174                         } else if (strcmp(CMD_ARGV[0], "none") == 0)
2175                                 goto write;
2176                 }
2177                 while (CMD_ARGC-- > 0) {
2178                         unsigned i;
2179                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2180                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2181                                         continue;
2182                                 catch |= vec_ids[i].mask;
2183                                 break;
2184                         }
2185                         if (i == ARRAY_SIZE(vec_ids)) {
2186                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2187                                 return ERROR_COMMAND_SYNTAX_ERROR;
2188                         }
2189                 }
2190 write:
2191                 /* For now, armv7m->demcr only stores vector catch flags. */
2192                 armv7m->demcr = catch;
2193
2194                 demcr &= ~0xffff;
2195                 demcr |= catch;
2196
2197                 /* write, but don't assume it stuck (why not??) */
2198                 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2199                 if (retval != ERROR_OK)
2200                         return retval;
2201                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2202                 if (retval != ERROR_OK)
2203                         return retval;
2204
2205                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2206                  * Otherwise the vector catch hardware could fire when there's
2207                  * no debugger hooked up, causing much confusion...
2208                  */
2209         }
2210
2211         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2212                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2213                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2214         }
2215
2216         return ERROR_OK;
2217 }
2218
2219 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2220 {
2221         struct target *target = get_current_target(CMD_CTX);
2222         struct cortex_m_common *cortex_m = target_to_cm(target);
2223         int retval;
2224
2225         static const Jim_Nvp nvp_maskisr_modes[] = {
2226                 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2227                 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2228                 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2229                 { .name = NULL, .value = -1 },
2230         };
2231         const Jim_Nvp *n;
2232
2233
2234         retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2235         if (retval != ERROR_OK)
2236                 return retval;
2237
2238         if (target->state != TARGET_HALTED) {
2239                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2240                 return ERROR_OK;
2241         }
2242
2243         if (CMD_ARGC > 0) {
2244                 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2245                 if (n->name == NULL)
2246                         return ERROR_COMMAND_SYNTAX_ERROR;
2247                 cortex_m->isrmasking_mode = n->value;
2248
2249
2250                 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2251                         cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2252                 else
2253                         cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2254         }
2255
2256         n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2257         command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2258
2259         return ERROR_OK;
2260 }
2261
2262 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2263 {
2264         struct target *target = get_current_target(CMD_CTX);
2265         struct cortex_m_common *cortex_m = target_to_cm(target);
2266         int retval;
2267         char *reset_config;
2268
2269         retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2270         if (retval != ERROR_OK)
2271                 return retval;
2272
2273         if (CMD_ARGC > 0) {
2274                 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2275                         cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2276                 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2277                         cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2278         }
2279
2280         switch (cortex_m->soft_reset_config) {
2281                 case CORTEX_M_RESET_SYSRESETREQ:
2282                         reset_config = "sysresetreq";
2283                         break;
2284
2285                 case CORTEX_M_RESET_VECTRESET:
2286                         reset_config = "vectreset";
2287                         break;
2288
2289                 default:
2290                         reset_config = "unknown";
2291                         break;
2292         }
2293
2294         command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2295
2296         return ERROR_OK;
2297 }
2298
2299 static const struct command_registration cortex_m_exec_command_handlers[] = {
2300         {
2301                 .name = "maskisr",
2302                 .handler = handle_cortex_m_mask_interrupts_command,
2303                 .mode = COMMAND_EXEC,
2304                 .help = "mask cortex_m interrupts",
2305                 .usage = "['auto'|'on'|'off']",
2306         },
2307         {
2308                 .name = "vector_catch",
2309                 .handler = handle_cortex_m_vector_catch_command,
2310                 .mode = COMMAND_EXEC,
2311                 .help = "configure hardware vectors to trigger debug entry",
2312                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2313         },
2314         {
2315                 .name = "reset_config",
2316                 .handler = handle_cortex_m_reset_config_command,
2317                 .mode = COMMAND_ANY,
2318                 .help = "configure software reset handling",
2319                 .usage = "['srst'|'sysresetreq'|'vectreset']",
2320         },
2321         COMMAND_REGISTRATION_DONE
2322 };
2323 static const struct command_registration cortex_m_command_handlers[] = {
2324         {
2325                 .chain = armv7m_command_handlers,
2326         },
2327         {
2328                 .name = "cortex_m",
2329                 .mode = COMMAND_EXEC,
2330                 .help = "Cortex-M command group",
2331                 .usage = "",
2332                 .chain = cortex_m_exec_command_handlers,
2333         },
2334         COMMAND_REGISTRATION_DONE
2335 };
2336
2337 struct target_type cortexm_target = {
2338         .name = "cortex_m",
2339         .deprecated_name = "cortex_m3",
2340
2341         .poll = cortex_m_poll,
2342         .arch_state = armv7m_arch_state,
2343
2344         .target_request_data = cortex_m_target_request_data,
2345
2346         .halt = cortex_m_halt,
2347         .resume = cortex_m_resume,
2348         .step = cortex_m_step,
2349
2350         .assert_reset = cortex_m_assert_reset,
2351         .deassert_reset = cortex_m_deassert_reset,
2352         .soft_reset_halt = cortex_m_soft_reset_halt,
2353
2354         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2355
2356         .read_memory = cortex_m_read_memory,
2357         .write_memory = cortex_m_write_memory,
2358         .checksum_memory = armv7m_checksum_memory,
2359         .blank_check_memory = armv7m_blank_check_memory,
2360
2361         .run_algorithm = armv7m_run_algorithm,
2362         .start_algorithm = armv7m_start_algorithm,
2363         .wait_algorithm = armv7m_wait_algorithm,
2364
2365         .add_breakpoint = cortex_m_add_breakpoint,
2366         .remove_breakpoint = cortex_m_remove_breakpoint,
2367         .add_watchpoint = cortex_m_add_watchpoint,
2368         .remove_watchpoint = cortex_m_remove_watchpoint,
2369
2370         .commands = cortex_m_command_handlers,
2371         .target_create = cortex_m_target_create,
2372         .init_target = cortex_m_init_target,
2373         .examine = cortex_m_examine,
2374         .deinit_target = cortex_m_deinit_target,
2375 };