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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *                                                                         *
   7  *   Copyright (C) 2006 by Magnus Lundin                                   *
   8  *   lundin@mlu.mine.nu                                                    *
   9  *                                                                         *
  10  *   Copyright (C) 2008 by Spencer Oliver                                  *
  11  *   spen@spen-soft.co.uk                                                  *
  12  *                                                                         *
  13  *                                                                         *
  14  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  15  *                                                                         *
  16  ***************************************************************************/
  17 #ifdef HAVE_CONFIG_H
  18 #include "config.h"
  19 #endif
  20
  21 #include "jtag/interface.h"
  22 #include "breakpoints.h"
  23 #include "cortex_m.h"
  24 #include "target_request.h"
  25 #include "target_type.h"
  26 #include "arm_adi_v5.h"
  27 #include "arm_disassembler.h"
  28 #include "register.h"
  29 #include "arm_opcodes.h"
  30 #include "arm_semihosting.h"
  31 #include <helper/time_support.h>
  32 #include <rtt/rtt.h>
  33
  34 /* NOTE:  most of this should work fine for the Cortex-M1 and
  35  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  36  * Some differences:  M0/M1 doesn't have FPB remapping or the
  37  * DWT tracing/profiling support.  (So the cycle counter will
  38  * not be usable; the other stuff isn't currently used here.)
  39  *
  40  * Although there are some workarounds for errata seen only in r0p0
  41  * silicon, such old parts are hard to find and thus not much tested
  42  * any longer.
  43  */
  44
  45 /* Timeout for register r/w */
  46 #define DHCSR_S_REGRDY_TIMEOUT (500)
  47
  48 /* Supported Cortex-M Cores */
  49 static const struct cortex_m_part_info cortex_m_parts[] = {
  50         {
  51                 .partno = CORTEX_M0_PARTNO,
  52                 .name = "Cortex-M0",
  53                 .arch = ARM_ARCH_V6M,
  54         },
  55         {
  56                 .partno = CORTEX_M0P_PARTNO,
  57                 .name = "Cortex-M0+",
  58                 .arch = ARM_ARCH_V6M,
  59         },
  60         {
  61                 .partno = CORTEX_M1_PARTNO,
  62                 .name = "Cortex-M1",
  63                 .arch = ARM_ARCH_V6M,
  64         },
  65         {
  66                 .partno = CORTEX_M3_PARTNO,
  67                 .name = "Cortex-M3",
  68                 .arch = ARM_ARCH_V7M,
  69                 .flags = CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
  70         },
  71         {
  72                 .partno = CORTEX_M4_PARTNO,
  73                 .name = "Cortex-M4",
  74                 .arch = ARM_ARCH_V7M,
  75                 .flags = CORTEX_M_F_HAS_FPV4 | CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
  76         },
  77         {
  78                 .partno = CORTEX_M7_PARTNO,
  79                 .name = "Cortex-M7",
  80                 .arch = ARM_ARCH_V7M,
  81                 .flags = CORTEX_M_F_HAS_FPV5,
  82         },
  83         {
  84                 .partno = CORTEX_M23_PARTNO,
  85                 .name = "Cortex-M23",
  86                 .arch = ARM_ARCH_V8M,
  87         },
  88         {
  89                 .partno = CORTEX_M33_PARTNO,
  90                 .name = "Cortex-M33",
  91                 .arch = ARM_ARCH_V8M,
  92                 .flags = CORTEX_M_F_HAS_FPV5,
  93         },
  94         {
  95                 .partno = CORTEX_M35P_PARTNO,
  96                 .name = "Cortex-M35P",
  97                 .arch = ARM_ARCH_V8M,
  98                 .flags = CORTEX_M_F_HAS_FPV5,
  99         },
 100         {
 101                 .partno = CORTEX_M55_PARTNO,
 102                 .name = "Cortex-M55",
 103                 .arch = ARM_ARCH_V8M,
 104                 .flags = CORTEX_M_F_HAS_FPV5,
 105         },
 106 };
 107
 108 /* forward declarations */
 109 static int cortex_m_store_core_reg_u32(struct target *target,
 110                 uint32_t num, uint32_t value);
 111 static void cortex_m_dwt_free(struct target *target);
 112
 113 /** DCB DHCSR register contains S_RETIRE_ST and S_RESET_ST bits cleared
 114  *  on a read. Call this helper function each time DHCSR is read
 115  *  to preserve S_RESET_ST state in case of a reset event was detected.
 116  */
 117 static inline void cortex_m_cumulate_dhcsr_sticky(struct cortex_m_common *cortex_m,
 118                 uint32_t dhcsr)
 119 {
 120         cortex_m->dcb_dhcsr_cumulated_sticky |= dhcsr;
 121 }
 122
 123 /** Read DCB DHCSR register to cortex_m->dcb_dhcsr and cumulate
 124  * sticky bits in cortex_m->dcb_dhcsr_cumulated_sticky
 125  */
 126 static int cortex_m_read_dhcsr_atomic_sticky(struct target *target)
 127 {
 128         struct cortex_m_common *cortex_m = target_to_cm(target);
 129         struct armv7m_common *armv7m = target_to_armv7m(target);
 130
 131         int retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
 132                                 &cortex_m->dcb_dhcsr);
 133         if (retval != ERROR_OK)
 134                 return retval;
 135
 136         cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
 137         return ERROR_OK;
 138 }
 139
 140 static int cortex_m_load_core_reg_u32(struct target *target,
 141                 uint32_t regsel, uint32_t *value)
 142 {
 143         struct cortex_m_common *cortex_m = target_to_cm(target);
 144         struct armv7m_common *armv7m = target_to_armv7m(target);
 145         int retval;
 146         uint32_t dcrdr, tmp_value;
 147         int64_t then;
 148
 149         /* because the DCB_DCRDR is used for the emulated dcc channel
 150          * we have to save/restore the DCB_DCRDR when used */
 151         if (target->dbg_msg_enabled) {
 152                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
 153                 if (retval != ERROR_OK)
 154                         return retval;
 155         }
 156
 157         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
 158         if (retval != ERROR_OK)
 159                 return retval;
 160
 161         /* check if value from register is ready and pre-read it */
 162         then = timeval_ms();
 163         while (1) {
 164                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DHCSR,
 165                                                                  &cortex_m->dcb_dhcsr);
 166                 if (retval != ERROR_OK)
 167                         return retval;
 168                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR,
 169                                                                                 &tmp_value);
 170                 if (retval != ERROR_OK)
 171                         return retval;
 172                 cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
 173                 if (cortex_m->dcb_dhcsr & S_REGRDY)
 174                         break;
 175                 cortex_m->slow_register_read = true; /* Polling (still) needed. */
 176                 if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
 177                         LOG_TARGET_ERROR(target, "Timeout waiting for DCRDR transfer ready");
 178                         return ERROR_TIMEOUT_REACHED;
 179                 }
 180                 keep_alive();
 181         }
 182
 183         *value = tmp_value;
 184
 185         if (target->dbg_msg_enabled) {
 186                 /* restore DCB_DCRDR - this needs to be in a separate
 187                  * transaction otherwise the emulated DCC channel breaks */
 188                 if (retval == ERROR_OK)
 189                         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
 190         }
 191
 192         return retval;
 193 }
 194
 195 static int cortex_m_slow_read_all_regs(struct target *target)
 196 {
 197         struct cortex_m_common *cortex_m = target_to_cm(target);
 198         struct armv7m_common *armv7m = target_to_armv7m(target);
 199         const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
 200
 201         /* Opportunistically restore fast read, it'll revert to slow
 202          * if any register needed polling in cortex_m_load_core_reg_u32(). */
 203         cortex_m->slow_register_read = false;
 204
 205         for (unsigned int reg_id = 0; reg_id < num_regs; reg_id++) {
 206                 struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
 207                 if (r->exist) {
 208                         int retval = armv7m->arm.read_core_reg(target, r, reg_id, ARM_MODE_ANY);
 209                         if (retval != ERROR_OK)
 210                                 return retval;
 211                 }
 212         }
 213
 214         if (!cortex_m->slow_register_read)
 215                 LOG_TARGET_DEBUG(target, "Switching back to fast register reads");
 216
 217         return ERROR_OK;
 218 }
 219
 220 static int cortex_m_queue_reg_read(struct target *target, uint32_t regsel,
 221                 uint32_t *reg_value, uint32_t *dhcsr)
 222 {
 223         struct armv7m_common *armv7m = target_to_armv7m(target);
 224         int retval;
 225
 226         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
 227         if (retval != ERROR_OK)
 228                 return retval;
 229
 230         retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DHCSR, dhcsr);
 231         if (retval != ERROR_OK)
 232                 return retval;
 233
 234         return mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, reg_value);
 235 }
 236
 237 static int cortex_m_fast_read_all_regs(struct target *target)
 238 {
 239         struct cortex_m_common *cortex_m = target_to_cm(target);
 240         struct armv7m_common *armv7m = target_to_armv7m(target);
 241         int retval;
 242         uint32_t dcrdr;
 243
 244         /* because the DCB_DCRDR is used for the emulated dcc channel
 245          * we have to save/restore the DCB_DCRDR when used */
 246         if (target->dbg_msg_enabled) {
 247                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
 248                 if (retval != ERROR_OK)
 249                         return retval;
 250         }
 251
 252         const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
 253         const unsigned int n_r32 = ARMV7M_LAST_REG - ARMV7M_CORE_FIRST_REG + 1
 254                                                            + ARMV7M_FPU_LAST_REG - ARMV7M_FPU_FIRST_REG + 1;
 255         /* we need one 32-bit word for each register except FP D0..D15, which
 256          * need two words */
 257         uint32_t r_vals[n_r32];
 258         uint32_t dhcsr[n_r32];
 259
 260         unsigned int wi = 0; /* write index to r_vals and dhcsr arrays */
 261         unsigned int reg_id; /* register index in the reg_list, ARMV7M_R0... */
 262         for (reg_id = 0; reg_id < num_regs; reg_id++) {
 263                 struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
 264                 if (!r->exist)
 265                         continue;       /* skip non existent registers */
 266
 267                 if (r->size <= 8) {
 268                         /* Any 8-bit or shorter register is unpacked from a 32-bit
 269                          * container register. Skip it now. */
 270                         continue;
 271                 }
 272
 273                 uint32_t regsel = armv7m_map_id_to_regsel(reg_id);
 274                 retval = cortex_m_queue_reg_read(target, regsel, &r_vals[wi],
 275                                                                                  &dhcsr[wi]);
 276                 if (retval != ERROR_OK)
 277                         return retval;
 278                 wi++;
 279
 280                 assert(r->size == 32 || r->size == 64);
 281                 if (r->size == 32)
 282                         continue;       /* done with 32-bit register */
 283
 284                 assert(reg_id >= ARMV7M_FPU_FIRST_REG && reg_id <= ARMV7M_FPU_LAST_REG);
 285                 /* the odd part of FP register (S1, S3...) */
 286                 retval = cortex_m_queue_reg_read(target, regsel + 1, &r_vals[wi],
 287                                                                                          &dhcsr[wi]);
 288                 if (retval != ERROR_OK)
 289                         return retval;
 290                 wi++;
 291         }
 292
 293         assert(wi <= n_r32);
 294
 295         retval = dap_run(armv7m->debug_ap->dap);
 296         if (retval != ERROR_OK)
 297                 return retval;
 298
 299         if (target->dbg_msg_enabled) {
 300                 /* restore DCB_DCRDR - this needs to be in a separate
 301                  * transaction otherwise the emulated DCC channel breaks */
 302                 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
 303                 if (retval != ERROR_OK)
 304                         return retval;
 305         }
 306
 307         bool not_ready = false;
 308         for (unsigned int i = 0; i < wi; i++) {
 309                 if ((dhcsr[i] & S_REGRDY) == 0) {
 310                         not_ready = true;
 311                         LOG_TARGET_DEBUG(target, "Register %u was not ready during fast read", i);
 312                 }
 313                 cortex_m_cumulate_dhcsr_sticky(cortex_m, dhcsr[i]);
 314         }
 315
 316         if (not_ready) {
 317                 /* Any register was not ready,
 318                  * fall back to slow read with S_REGRDY polling */
 319                 return ERROR_TIMEOUT_REACHED;
 320         }
 321
 322         LOG_TARGET_DEBUG(target, "read %u 32-bit registers", wi);
 323
 324         unsigned int ri = 0; /* read index from r_vals array */
 325         for (reg_id = 0; reg_id < num_regs; reg_id++) {
 326                 struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
 327                 if (!r->exist)
 328                         continue;       /* skip non existent registers */
 329
 330                 r->dirty = false;
 331
 332                 unsigned int reg32_id;
 333                 uint32_t offset;
 334                 if (armv7m_map_reg_packing(reg_id, &reg32_id, &offset)) {
 335                         /* Unpack a partial register from 32-bit container register */
 336                         struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id];
 337
 338                         /* The container register ought to precede all regs unpacked
 339                          * from it in the reg_list. So the value should be ready
 340                          * to unpack */
 341                         assert(r32->valid);
 342                         buf_cpy(r32->value + offset, r->value, r->size);
 343
 344                 } else {
 345                         assert(r->size == 32 || r->size == 64);
 346                         buf_set_u32(r->value, 0, 32, r_vals[ri++]);
 347
 348                         if (r->size == 64) {
 349                                 assert(reg_id >= ARMV7M_FPU_FIRST_REG && reg_id <= ARMV7M_FPU_LAST_REG);
 350                                 /* the odd part of FP register (S1, S3...) */
 351                                 buf_set_u32(r->value + 4, 0, 32, r_vals[ri++]);
 352                         }
 353                 }
 354                 r->valid = true;
 355         }
 356         assert(ri == wi);
 357
 358         return retval;
 359 }
 360
 361 static int cortex_m_store_core_reg_u32(struct target *target,
 362                 uint32_t regsel, uint32_t value)
 363 {
 364         struct cortex_m_common *cortex_m = target_to_cm(target);
 365         struct armv7m_common *armv7m = target_to_armv7m(target);
 366         int retval;
 367         uint32_t dcrdr;
 368         int64_t then;
 369
 370         /* because the DCB_DCRDR is used for the emulated dcc channel
 371          * we have to save/restore the DCB_DCRDR when used */
 372         if (target->dbg_msg_enabled) {
 373                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
 374                 if (retval != ERROR_OK)
 375                         return retval;
 376         }
 377
 378         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
 379         if (retval != ERROR_OK)
 380                 return retval;
 381
 382         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WNR);
 383         if (retval != ERROR_OK)
 384                 return retval;
 385
 386         /* check if value is written into register */
 387         then = timeval_ms();
 388         while (1) {
 389                 retval = cortex_m_read_dhcsr_atomic_sticky(target);
 390                 if (retval != ERROR_OK)
 391                         return retval;
 392                 if (cortex_m->dcb_dhcsr & S_REGRDY)
 393                         break;
 394                 if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
 395                         LOG_TARGET_ERROR(target, "Timeout waiting for DCRDR transfer ready");
 396                         return ERROR_TIMEOUT_REACHED;
 397                 }
 398                 keep_alive();
 399         }
 400
 401         if (target->dbg_msg_enabled) {
 402                 /* restore DCB_DCRDR - this needs to be in a separate
 403                  * transaction otherwise the emulated DCC channel breaks */
 404                 if (retval == ERROR_OK)
 405                         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
 406         }
 407
 408         return retval;
 409 }
 410
 411 static int cortex_m_write_debug_halt_mask(struct target *target,
 412         uint32_t mask_on, uint32_t mask_off)
 413 {
 414         struct cortex_m_common *cortex_m = target_to_cm(target);
 415         struct armv7m_common *armv7m = &cortex_m->armv7m;
 416
 417         /* mask off status bits */
 418         cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
 419         /* create new register mask */
 420         cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 421
 422         return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
 423 }
 424
 425 static int cortex_m_set_maskints(struct target *target, bool mask)
 426 {
 427         struct cortex_m_common *cortex_m = target_to_cm(target);
 428         if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
 429                 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
 430         else
 431                 return ERROR_OK;
 432 }
 433
 434 static int cortex_m_set_maskints_for_halt(struct target *target)
 435 {
 436         struct cortex_m_common *cortex_m = target_to_cm(target);
 437         switch (cortex_m->isrmasking_mode) {
 438                 case CORTEX_M_ISRMASK_AUTO:
 439                         /* interrupts taken at resume, whether for step or run -> no mask */
 440                         return cortex_m_set_maskints(target, false);
 441
 442                 case CORTEX_M_ISRMASK_OFF:
 443                         /* interrupts never masked */
 444                         return cortex_m_set_maskints(target, false);
 445
 446                 case CORTEX_M_ISRMASK_ON:
 447                         /* interrupts always masked */
 448                         return cortex_m_set_maskints(target, true);
 449
 450                 case CORTEX_M_ISRMASK_STEPONLY:
 451                         /* interrupts masked for single step only -> mask now if MASKINTS
 452                          * erratum, otherwise only mask before stepping */
 453                         return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
 454         }
 455         return ERROR_OK;
 456 }
 457
 458 static int cortex_m_set_maskints_for_run(struct target *target)
 459 {
 460         switch (target_to_cm(target)->isrmasking_mode) {
 461                 case CORTEX_M_ISRMASK_AUTO:
 462                         /* interrupts taken at resume, whether for step or run -> no mask */
 463                         return cortex_m_set_maskints(target, false);
 464
 465                 case CORTEX_M_ISRMASK_OFF:
 466                         /* interrupts never masked */
 467                         return cortex_m_set_maskints(target, false);
 468
 469                 case CORTEX_M_ISRMASK_ON:
 470                         /* interrupts always masked */
 471                         return cortex_m_set_maskints(target, true);
 472
 473                 case CORTEX_M_ISRMASK_STEPONLY:
 474                         /* interrupts masked for single step only -> no mask */
 475                         return cortex_m_set_maskints(target, false);
 476         }
 477         return ERROR_OK;
 478 }
 479
 480 static int cortex_m_set_maskints_for_step(struct target *target)
 481 {
 482         switch (target_to_cm(target)->isrmasking_mode) {
 483                 case CORTEX_M_ISRMASK_AUTO:
 484                         /* the auto-interrupt should already be done -> mask */
 485                         return cortex_m_set_maskints(target, true);
 486
 487                 case CORTEX_M_ISRMASK_OFF:
 488                         /* interrupts never masked */
 489                         return cortex_m_set_maskints(target, false);
 490
 491                 case CORTEX_M_ISRMASK_ON:
 492                         /* interrupts always masked */
 493                         return cortex_m_set_maskints(target, true);
 494
 495                 case CORTEX_M_ISRMASK_STEPONLY:
 496                         /* interrupts masked for single step only -> mask */
 497                         return cortex_m_set_maskints(target, true);
 498         }
 499         return ERROR_OK;
 500 }
 501
 502 static int cortex_m_clear_halt(struct target *target)
 503 {
 504         struct cortex_m_common *cortex_m = target_to_cm(target);
 505         struct armv7m_common *armv7m = &cortex_m->armv7m;
 506         int retval;
 507
 508         /* clear step if any */
 509         cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
 510
 511         /* Read Debug Fault Status Register */
 512         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
 513         if (retval != ERROR_OK)
 514                 return retval;
 515
 516         /* Clear Debug Fault Status */
 517         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
 518         if (retval != ERROR_OK)
 519                 return retval;
 520         LOG_TARGET_DEBUG(target, "NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
 521
 522         return ERROR_OK;
 523 }
 524
 525 static int cortex_m_single_step_core(struct target *target)
 526 {
 527         struct cortex_m_common *cortex_m = target_to_cm(target);
 528         int retval;
 529
 530         /* Mask interrupts before clearing halt, if not done already.  This avoids
 531          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 532          * HALT can put the core into an unknown state.
 533          */
 534         if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
 535                 retval = cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
 536                 if (retval != ERROR_OK)
 537                         return retval;
 538         }
 539         retval = cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 540         if (retval != ERROR_OK)
 541                 return retval;
 542         LOG_TARGET_DEBUG(target, "single step");
 543
 544         /* restore dhcsr reg */
 545         cortex_m_clear_halt(target);
 546
 547         return ERROR_OK;
 548 }
 549
 550 static int cortex_m_enable_fpb(struct target *target)
 551 {
 552         int retval = target_write_u32(target, FP_CTRL, 3);
 553         if (retval != ERROR_OK)
 554                 return retval;
 555
 556         /* check the fpb is actually enabled */
 557         uint32_t fpctrl;
 558         retval = target_read_u32(target, FP_CTRL, &fpctrl);
 559         if (retval != ERROR_OK)
 560                 return retval;
 561
 562         if (fpctrl & 1)
 563                 return ERROR_OK;
 564
 565         return ERROR_FAIL;
 566 }
 567
 568 static int cortex_m_endreset_event(struct target *target)
 569 {
 570         int retval;
 571         uint32_t dcb_demcr;
 572         struct cortex_m_common *cortex_m = target_to_cm(target);
 573         struct armv7m_common *armv7m = &cortex_m->armv7m;
 574         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 575         struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
 576         struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
 577
 578         /* REVISIT The four debug monitor bits are currently ignored... */
 579         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
 580         if (retval != ERROR_OK)
 581                 return retval;
 582         LOG_TARGET_DEBUG(target, "DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
 583
 584         /* this register is used for emulated dcc channel */
 585         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
 586         if (retval != ERROR_OK)
 587                 return retval;
 588
 589         retval = cortex_m_read_dhcsr_atomic_sticky(target);
 590         if (retval != ERROR_OK)
 591                 return retval;
 592
 593         if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
 594                 /* Enable debug requests */
 595                 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
 596                 if (retval != ERROR_OK)
 597                         return retval;
 598         }
 599
 600         /* Restore proper interrupt masking setting for running CPU. */
 601         cortex_m_set_maskints_for_run(target);
 602
 603         /* Enable features controlled by ITM and DWT blocks, and catch only
 604          * the vectors we were told to pay attention to.
 605          *
 606          * Target firmware is responsible for all fault handling policy
 607          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 608          * or manual updates to the NVIC SHCSR and CCR registers.
 609          */
 610         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
 611         if (retval != ERROR_OK)
 612                 return retval;
 613
 614         /* Paranoia: evidently some (early?) chips don't preserve all the
 615          * debug state (including FPB, DWT, etc) across reset...
 616          */
 617
 618         /* Enable FPB */
 619         retval = cortex_m_enable_fpb(target);
 620         if (retval != ERROR_OK) {
 621                 LOG_TARGET_ERROR(target, "Failed to enable the FPB");
 622                 return retval;
 623         }
 624
 625         cortex_m->fpb_enabled = true;
 626
 627         /* Restore FPB registers */
 628         for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
 629                 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 630                 if (retval != ERROR_OK)
 631                         return retval;
 632         }
 633
 634         /* Restore DWT registers */
 635         for (unsigned int i = 0; i < cortex_m->dwt_num_comp; i++) {
 636                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 637                                 dwt_list[i].comp);
 638                 if (retval != ERROR_OK)
 639                         return retval;
 640                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 641                                 dwt_list[i].mask);
 642                 if (retval != ERROR_OK)
 643                         return retval;
 644                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 645                                 dwt_list[i].function);
 646                 if (retval != ERROR_OK)
 647                         return retval;
 648         }
 649         retval = dap_run(swjdp);
 650         if (retval != ERROR_OK)
 651                 return retval;
 652
 653         register_cache_invalidate(armv7m->arm.core_cache);
 654
 655         /* make sure we have latest dhcsr flags */
 656         retval = cortex_m_read_dhcsr_atomic_sticky(target);
 657         if (retval != ERROR_OK)
 658                 return retval;
 659
 660         return retval;
 661 }
 662
 663 static int cortex_m_examine_debug_reason(struct target *target)
 664 {
 665         struct cortex_m_common *cortex_m = target_to_cm(target);
 666
 667         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
 668          * only check the debug reason if we don't know it already */
 669
 670         if ((target->debug_reason != DBG_REASON_DBGRQ)
 671                 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
 672                 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
 673                         target->debug_reason = DBG_REASON_BREAKPOINT;
 674                         if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 675                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 676                 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 677                         target->debug_reason = DBG_REASON_WATCHPOINT;
 678                 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
 679                         target->debug_reason = DBG_REASON_BREAKPOINT;
 680                 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
 681                         target->debug_reason = DBG_REASON_DBGRQ;
 682                 else    /* HALTED */
 683                         target->debug_reason = DBG_REASON_UNDEFINED;
 684         }
 685
 686         return ERROR_OK;
 687 }
 688
 689 static int cortex_m_examine_exception_reason(struct target *target)
 690 {
 691         uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
 692         struct armv7m_common *armv7m = target_to_armv7m(target);
 693         struct adiv5_dap *swjdp = armv7m->arm.dap;
 694         int retval;
 695
 696         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
 697         if (retval != ERROR_OK)
 698                 return retval;
 699         switch (armv7m->exception_number) {
 700                 case 2: /* NMI */
 701                         break;
 702                 case 3: /* Hard Fault */
 703                         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
 704                         if (retval != ERROR_OK)
 705                                 return retval;
 706                         if (except_sr & 0x40000000) {
 707                                 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
 708                                 if (retval != ERROR_OK)
 709                                         return retval;
 710                         }
 711                         break;
 712                 case 4: /* Memory Management */
 713                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 714                         if (retval != ERROR_OK)
 715                                 return retval;
 716                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
 717                         if (retval != ERROR_OK)
 718                                 return retval;
 719                         break;
 720                 case 5: /* Bus Fault */
 721                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 722                         if (retval != ERROR_OK)
 723                                 return retval;
 724                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
 725                         if (retval != ERROR_OK)
 726                                 return retval;
 727                         break;
 728                 case 6: /* Usage Fault */
 729                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 730                         if (retval != ERROR_OK)
 731                                 return retval;
 732                         break;
 733                 case 7: /* Secure Fault */
 734                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
 735                         if (retval != ERROR_OK)
 736                                 return retval;
 737                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
 738                         if (retval != ERROR_OK)
 739                                 return retval;
 740                         break;
 741                 case 11:        /* SVCall */
 742                         break;
 743                 case 12:        /* Debug Monitor */
 744                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
 745                         if (retval != ERROR_OK)
 746                                 return retval;
 747                         break;
 748                 case 14:        /* PendSV */
 749                         break;
 750                 case 15:        /* SysTick */
 751                         break;
 752                 default:
 753                         except_sr = 0;
 754                         break;
 755         }
 756         retval = dap_run(swjdp);
 757         if (retval == ERROR_OK)
 758                 LOG_TARGET_DEBUG(target, "%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 759                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 760                         armv7m_exception_string(armv7m->exception_number),
 761                         shcsr, except_sr, cfsr, except_ar);
 762         return retval;
 763 }
 764
 765 static int cortex_m_debug_entry(struct target *target)
 766 {
 767         uint32_t xPSR;
 768         int retval;
 769         struct cortex_m_common *cortex_m = target_to_cm(target);
 770         struct armv7m_common *armv7m = &cortex_m->armv7m;
 771         struct arm *arm = &armv7m->arm;
 772         struct reg *r;
 773
 774         LOG_TARGET_DEBUG(target, " ");
 775
 776         /* Do this really early to minimize the window where the MASKINTS erratum
 777          * can pile up pending interrupts. */
 778         cortex_m_set_maskints_for_halt(target);
 779
 780         cortex_m_clear_halt(target);
 781
 782         retval = cortex_m_read_dhcsr_atomic_sticky(target);
 783         if (retval != ERROR_OK)
 784                 return retval;
 785
 786         retval = armv7m->examine_debug_reason(target);
 787         if (retval != ERROR_OK)
 788                 return retval;
 789
 790         /* examine PE security state */
 791         bool secure_state = false;
 792         if (armv7m->arm.arch == ARM_ARCH_V8M) {
 793                 uint32_t dscsr;
 794
 795                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
 796                 if (retval != ERROR_OK)
 797                         return retval;
 798
 799                 secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
 800         }
 801
 802         /* Load all registers to arm.core_cache */
 803         if (!cortex_m->slow_register_read) {
 804                 retval = cortex_m_fast_read_all_regs(target);
 805                 if (retval == ERROR_TIMEOUT_REACHED) {
 806                         cortex_m->slow_register_read = true;
 807                         LOG_TARGET_DEBUG(target, "Switched to slow register read");
 808                 }
 809         }
 810
 811         if (cortex_m->slow_register_read)
 812                 retval = cortex_m_slow_read_all_regs(target);
 813
 814         if (retval != ERROR_OK)
 815                 return retval;
 816
 817         r = arm->cpsr;
 818         xPSR = buf_get_u32(r->value, 0, 32);
 819
 820         /* Are we in an exception handler */
 821         if (xPSR & 0x1FF) {
 822                 armv7m->exception_number = (xPSR & 0x1FF);
 823
 824                 arm->core_mode = ARM_MODE_HANDLER;
 825                 arm->map = armv7m_msp_reg_map;
 826         } else {
 827                 unsigned control = buf_get_u32(arm->core_cache
 828                                 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
 829
 830                 /* is this thread privileged? */
 831                 arm->core_mode = control & 1
 832                         ? ARM_MODE_USER_THREAD
 833                         : ARM_MODE_THREAD;
 834
 835                 /* which stack is it using? */
 836                 if (control & 2)
 837                         arm->map = armv7m_psp_reg_map;
 838                 else
 839                         arm->map = armv7m_msp_reg_map;
 840
 841                 armv7m->exception_number = 0;
 842         }
 843
 844         if (armv7m->exception_number)
 845                 cortex_m_examine_exception_reason(target);
 846
 847         LOG_TARGET_DEBUG(target, "entered debug state in core mode: %s at PC 0x%" PRIx32
 848                         ", cpu in %s state, target->state: %s",
 849                 arm_mode_name(arm->core_mode),
 850                 buf_get_u32(arm->pc->value, 0, 32),
 851                 secure_state ? "Secure" : "Non-Secure",
 852                 target_state_name(target));
 853
 854         if (armv7m->post_debug_entry) {
 855                 retval = armv7m->post_debug_entry(target);
 856                 if (retval != ERROR_OK)
 857                         return retval;
 858         }
 859
 860         return ERROR_OK;
 861 }
 862
 863 static int cortex_m_poll(struct target *target)
 864 {
 865         int detected_failure = ERROR_OK;
 866         int retval = ERROR_OK;
 867         enum target_state prev_target_state = target->state;
 868         struct cortex_m_common *cortex_m = target_to_cm(target);
 869         struct armv7m_common *armv7m = &cortex_m->armv7m;
 870
 871         /* Read from Debug Halting Control and Status Register */
 872         retval = cortex_m_read_dhcsr_atomic_sticky(target);
 873         if (retval != ERROR_OK) {
 874                 target->state = TARGET_UNKNOWN;
 875                 return retval;
 876         }
 877
 878         /* Recover from lockup.  See ARMv7-M architecture spec,
 879          * section B1.5.15 "Unrecoverable exception cases".
 880          */
 881         if (cortex_m->dcb_dhcsr & S_LOCKUP) {
 882                 LOG_TARGET_ERROR(target, "clearing lockup after double fault");
 883                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 884                 target->debug_reason = DBG_REASON_DBGRQ;
 885
 886                 /* We have to execute the rest (the "finally" equivalent, but
 887                  * still throw this exception again).
 888                  */
 889                 detected_failure = ERROR_FAIL;
 890
 891                 /* refresh status bits */
 892                 retval = cortex_m_read_dhcsr_atomic_sticky(target);
 893                 if (retval != ERROR_OK)
 894                         return retval;
 895         }
 896
 897         if (cortex_m->dcb_dhcsr_cumulated_sticky & S_RESET_ST) {
 898                 cortex_m->dcb_dhcsr_cumulated_sticky &= ~S_RESET_ST;
 899                 if (target->state != TARGET_RESET) {
 900                         target->state = TARGET_RESET;
 901                         LOG_TARGET_INFO(target, "external reset detected");
 902                 }
 903                 return ERROR_OK;
 904         }
 905
 906         if (target->state == TARGET_RESET) {
 907                 /* Cannot switch context while running so endreset is
 908                  * called with target->state == TARGET_RESET
 909                  */
 910                 LOG_TARGET_DEBUG(target, "Exit from reset with dcb_dhcsr 0x%" PRIx32,
 911                         cortex_m->dcb_dhcsr);
 912                 retval = cortex_m_endreset_event(target);
 913                 if (retval != ERROR_OK) {
 914                         target->state = TARGET_UNKNOWN;
 915                         return retval;
 916                 }
 917                 target->state = TARGET_RUNNING;
 918                 prev_target_state = TARGET_RUNNING;
 919         }
 920
 921         if (cortex_m->dcb_dhcsr & S_HALT) {
 922                 target->state = TARGET_HALTED;
 923
 924                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
 925                         retval = cortex_m_debug_entry(target);
 926                         if (retval != ERROR_OK)
 927                                 return retval;
 928
 929                         if (arm_semihosting(target, &retval) != 0)
 930                                 return retval;
 931
 932                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 933                 }
 934                 if (prev_target_state == TARGET_DEBUG_RUNNING) {
 935                         retval = cortex_m_debug_entry(target);
 936                         if (retval != ERROR_OK)
 937                                 return retval;
 938
 939                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 940                 }
 941         }
 942
 943         if (target->state == TARGET_UNKNOWN) {
 944                 /* Check if processor is retiring instructions or sleeping.
 945                  * Unlike S_RESET_ST here we test if the target *is* running now,
 946                  * not if it has been running (possibly in the past). Instructions are
 947                  * typically processed much faster than OpenOCD polls DHCSR so S_RETIRE_ST
 948                  * is read always 1. That's the reason not to use dcb_dhcsr_cumulated_sticky.
 949                  */
 950                 if (cortex_m->dcb_dhcsr & S_RETIRE_ST || cortex_m->dcb_dhcsr & S_SLEEP) {
 951                         target->state = TARGET_RUNNING;
 952                         retval = ERROR_OK;
 953                 }
 954         }
 955
 956         /* Check that target is truly halted, since the target could be resumed externally */
 957         if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
 958                 /* registers are now invalid */
 959                 register_cache_invalidate(armv7m->arm.core_cache);
 960
 961                 target->state = TARGET_RUNNING;
 962                 LOG_TARGET_WARNING(target, "external resume detected");
 963                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 964                 retval = ERROR_OK;
 965         }
 966
 967         /* Did we detect a failure condition that we cleared? */
 968         if (detected_failure != ERROR_OK)
 969                 retval = detected_failure;
 970         return retval;
 971 }
 972
 973 static int cortex_m_halt(struct target *target)
 974 {
 975         LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
 976
 977         if (target->state == TARGET_HALTED) {
 978                 LOG_TARGET_DEBUG(target, "target was already halted");
 979                 return ERROR_OK;
 980         }
 981
 982         if (target->state == TARGET_UNKNOWN)
 983                 LOG_TARGET_WARNING(target, "target was in unknown state when halt was requested");
 984
 985         if (target->state == TARGET_RESET) {
 986                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 987                         LOG_TARGET_ERROR(target, "can't request a halt while in reset if nSRST pulls nTRST");
 988                         return ERROR_TARGET_FAILURE;
 989                 } else {
 990                         /* we came here in a reset_halt or reset_init sequence
 991                          * debug entry was already prepared in cortex_m3_assert_reset()
 992                          */
 993                         target->debug_reason = DBG_REASON_DBGRQ;
 994
 995                         return ERROR_OK;
 996                 }
 997         }
 998
 999         /* Write to Debug Halting Control and Status Register */
1000         cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1001
1002         /* Do this really early to minimize the window where the MASKINTS erratum
1003          * can pile up pending interrupts. */
1004         cortex_m_set_maskints_for_halt(target);
1005
1006         target->debug_reason = DBG_REASON_DBGRQ;
1007
1008         return ERROR_OK;
1009 }
1010
1011 static int cortex_m_soft_reset_halt(struct target *target)
1012 {
1013         struct cortex_m_common *cortex_m = target_to_cm(target);
1014         struct armv7m_common *armv7m = &cortex_m->armv7m;
1015         int retval, timeout = 0;
1016
1017         /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
1018          * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
1019          * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
1020          * core, not the peripherals */
1021         LOG_TARGET_DEBUG(target, "soft_reset_halt is discouraged, please use 'reset halt' instead.");
1022
1023         if (!cortex_m->vectreset_supported) {
1024                 LOG_TARGET_ERROR(target, "VECTRESET is not supported on this Cortex-M core");
1025                 return ERROR_FAIL;
1026         }
1027
1028         /* Set C_DEBUGEN */
1029         retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
1030         if (retval != ERROR_OK)
1031                 return retval;
1032
1033         /* Enter debug state on reset; restore DEMCR in endreset_event() */
1034         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
1035                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1036         if (retval != ERROR_OK)
1037                 return retval;
1038
1039         /* Request a core-only reset */
1040         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1041                         AIRCR_VECTKEY | AIRCR_VECTRESET);
1042         if (retval != ERROR_OK)
1043                 return retval;
1044         target->state = TARGET_RESET;
1045
1046         /* registers are now invalid */
1047         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1048
1049         while (timeout < 100) {
1050                 retval = cortex_m_read_dhcsr_atomic_sticky(target);
1051                 if (retval == ERROR_OK) {
1052                         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
1053                                         &cortex_m->nvic_dfsr);
1054                         if (retval != ERROR_OK)
1055                                 return retval;
1056                         if ((cortex_m->dcb_dhcsr & S_HALT)
1057                                 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
1058                                 LOG_TARGET_DEBUG(target, "system reset-halted, DHCSR 0x%08" PRIx32 ", DFSR 0x%08" PRIx32,
1059                                                 cortex_m->dcb_dhcsr, cortex_m->nvic_dfsr);
1060                                 cortex_m_poll(target);
1061                                 /* FIXME restore user's vector catch config */
1062                                 return ERROR_OK;
1063                         } else {
1064                                 LOG_TARGET_DEBUG(target, "waiting for system reset-halt, "
1065                                         "DHCSR 0x%08" PRIx32 ", %d ms",
1066                                         cortex_m->dcb_dhcsr, timeout);
1067                         }
1068                 }
1069                 timeout++;
1070                 alive_sleep(1);
1071         }
1072
1073         return ERROR_OK;
1074 }
1075
1076 void cortex_m_enable_breakpoints(struct target *target)
1077 {
1078         struct breakpoint *breakpoint = target->breakpoints;
1079
1080         /* set any pending breakpoints */
1081         while (breakpoint) {
1082                 if (!breakpoint->is_set)
1083                         cortex_m_set_breakpoint(target, breakpoint);
1084                 breakpoint = breakpoint->next;
1085         }
1086 }
1087
1088 static int cortex_m_resume(struct target *target, int current,
1089         target_addr_t address, int handle_breakpoints, int debug_execution)
1090 {
1091         struct armv7m_common *armv7m = target_to_armv7m(target);
1092         struct breakpoint *breakpoint = NULL;
1093         uint32_t resume_pc;
1094         struct reg *r;
1095
1096         if (target->state != TARGET_HALTED) {
1097                 LOG_TARGET_WARNING(target, "target not halted");
1098                 return ERROR_TARGET_NOT_HALTED;
1099         }
1100
1101         if (!debug_execution) {
1102                 target_free_all_working_areas(target);
1103                 cortex_m_enable_breakpoints(target);
1104                 cortex_m_enable_watchpoints(target);
1105         }
1106
1107         if (debug_execution) {
1108                 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
1109
1110                 /* Disable interrupts */
1111                 /* We disable interrupts in the PRIMASK register instead of
1112                  * masking with C_MASKINTS.  This is probably the same issue
1113                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
1114                  * in parallel with disabled interrupts can cause local faults
1115                  * to not be taken.
1116                  *
1117                  * This breaks non-debug (application) execution if not
1118                  * called from armv7m_start_algorithm() which saves registers.
1119                  */
1120                 buf_set_u32(r->value, 0, 1, 1);
1121                 r->dirty = true;
1122                 r->valid = true;
1123
1124                 /* Make sure we are in Thumb mode, set xPSR.T bit */
1125                 /* armv7m_start_algorithm() initializes entire xPSR register.
1126                  * This duplicity handles the case when cortex_m_resume()
1127                  * is used with the debug_execution flag directly,
1128                  * not called through armv7m_start_algorithm().
1129                  */
1130                 r = armv7m->arm.cpsr;
1131                 buf_set_u32(r->value, 24, 1, 1);
1132                 r->dirty = true;
1133                 r->valid = true;
1134         }
1135
1136         /* current = 1: continue on current pc, otherwise continue at <address> */
1137         r = armv7m->arm.pc;
1138         if (!current) {
1139                 buf_set_u32(r->value, 0, 32, address);
1140                 r->dirty = true;
1141                 r->valid = true;
1142         }
1143
1144         /* if we halted last time due to a bkpt instruction
1145          * then we have to manually step over it, otherwise
1146          * the core will break again */
1147
1148         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
1149                 && !debug_execution)
1150                 armv7m_maybe_skip_bkpt_inst(target, NULL);
1151
1152         resume_pc = buf_get_u32(r->value, 0, 32);
1153
1154         armv7m_restore_context(target);
1155
1156         /* the front-end may request us not to handle breakpoints */
1157         if (handle_breakpoints) {
1158                 /* Single step past breakpoint at current address */
1159                 breakpoint = breakpoint_find(target, resume_pc);
1160                 if (breakpoint) {
1161                         LOG_TARGET_DEBUG(target, "unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
1162                                 breakpoint->address,
1163                                 breakpoint->unique_id);
1164                         cortex_m_unset_breakpoint(target, breakpoint);
1165                         cortex_m_single_step_core(target);
1166                         cortex_m_set_breakpoint(target, breakpoint);
1167                 }
1168         }
1169
1170         /* Restart core */
1171         cortex_m_set_maskints_for_run(target);
1172         cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1173
1174         target->debug_reason = DBG_REASON_NOTHALTED;
1175
1176         /* registers are now invalid */
1177         register_cache_invalidate(armv7m->arm.core_cache);
1178
1179         if (!debug_execution) {
1180                 target->state = TARGET_RUNNING;
1181                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1182                 LOG_TARGET_DEBUG(target, "target resumed at 0x%" PRIx32 "", resume_pc);
1183         } else {
1184                 target->state = TARGET_DEBUG_RUNNING;
1185                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1186                 LOG_TARGET_DEBUG(target, "target debug resumed at 0x%" PRIx32 "", resume_pc);
1187         }
1188
1189         return ERROR_OK;
1190 }
1191
1192 /* int irqstepcount = 0; */
1193 static int cortex_m_step(struct target *target, int current,
1194         target_addr_t address, int handle_breakpoints)
1195 {
1196         struct cortex_m_common *cortex_m = target_to_cm(target);
1197         struct armv7m_common *armv7m = &cortex_m->armv7m;
1198         struct breakpoint *breakpoint = NULL;
1199         struct reg *pc = armv7m->arm.pc;
1200         bool bkpt_inst_found = false;
1201         int retval;
1202         bool isr_timed_out = false;
1203
1204         if (target->state != TARGET_HALTED) {
1205                 LOG_TARGET_WARNING(target, "target not halted");
1206                 return ERROR_TARGET_NOT_HALTED;
1207         }
1208
1209         /* current = 1: continue on current pc, otherwise continue at <address> */
1210         if (!current) {
1211                 buf_set_u32(pc->value, 0, 32, address);
1212                 pc->dirty = true;
1213                 pc->valid = true;
1214         }
1215
1216         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
1217
1218         /* the front-end may request us not to handle breakpoints */
1219         if (handle_breakpoints) {
1220                 breakpoint = breakpoint_find(target, pc_value);
1221                 if (breakpoint)
1222                         cortex_m_unset_breakpoint(target, breakpoint);
1223         }
1224
1225         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
1226
1227         target->debug_reason = DBG_REASON_SINGLESTEP;
1228
1229         armv7m_restore_context(target);
1230
1231         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1232
1233         /* if no bkpt instruction is found at pc then we can perform
1234          * a normal step, otherwise we have to manually step over the bkpt
1235          * instruction - as such simulate a step */
1236         if (bkpt_inst_found == false) {
1237                 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
1238                         /* Automatic ISR masking mode off: Just step over the next
1239                          * instruction, with interrupts on or off as appropriate. */
1240                         cortex_m_set_maskints_for_step(target);
1241                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1242                 } else {
1243                         /* Process interrupts during stepping in a way they don't interfere
1244                          * debugging.
1245                          *
1246                          * Principle:
1247                          *
1248                          * Set a temporary break point at the current pc and let the core run
1249                          * with interrupts enabled. Pending interrupts get served and we run
1250                          * into the breakpoint again afterwards. Then we step over the next
1251                          * instruction with interrupts disabled.
1252                          *
1253                          * If the pending interrupts don't complete within time, we leave the
1254                          * core running. This may happen if the interrupts trigger faster
1255                          * than the core can process them or the handler doesn't return.
1256                          *
1257                          * If no more breakpoints are available we simply do a step with
1258                          * interrupts enabled.
1259                          *
1260                          */
1261
1262                         /* 2012-09-29 ph
1263                          *
1264                          * If a break point is already set on the lower half word then a break point on
1265                          * the upper half word will not break again when the core is restarted. So we
1266                          * just step over the instruction with interrupts disabled.
1267                          *
1268                          * The documentation has no information about this, it was found by observation
1269                          * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
1270                          * suffer from this problem.
1271                          *
1272                          * To add some confusion: pc_value has bit 0 always set, while the breakpoint
1273                          * address has it always cleared. The former is done to indicate thumb mode
1274                          * to gdb.
1275                          *
1276                          */
1277                         if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
1278                                 LOG_TARGET_DEBUG(target, "Stepping over next instruction with interrupts disabled");
1279                                 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
1280                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1281                                 /* Re-enable interrupts if appropriate */
1282                                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1283                                 cortex_m_set_maskints_for_halt(target);
1284                         } else {
1285
1286                                 /* Set a temporary break point */
1287                                 if (breakpoint) {
1288                                         retval = cortex_m_set_breakpoint(target, breakpoint);
1289                                 } else {
1290                                         enum breakpoint_type type = BKPT_HARD;
1291                                         if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
1292                                                 /* FPB rev.1 cannot handle such addr, try BKPT instr */
1293                                                 type = BKPT_SOFT;
1294                                         }
1295                                         retval = breakpoint_add(target, pc_value, 2, type);
1296                                 }
1297
1298                                 bool tmp_bp_set = (retval == ERROR_OK);
1299
1300                                 /* No more breakpoints left, just do a step */
1301                                 if (!tmp_bp_set) {
1302                                         cortex_m_set_maskints_for_step(target);
1303                                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1304                                         /* Re-enable interrupts if appropriate */
1305                                         cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1306                                         cortex_m_set_maskints_for_halt(target);
1307                                 } else {
1308                                         /* Start the core */
1309                                         LOG_TARGET_DEBUG(target, "Starting core to serve pending interrupts");
1310                                         int64_t t_start = timeval_ms();
1311                                         cortex_m_set_maskints_for_run(target);
1312                                         cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
1313
1314                                         /* Wait for pending handlers to complete or timeout */
1315                                         do {
1316                                                 retval = cortex_m_read_dhcsr_atomic_sticky(target);
1317                                                 if (retval != ERROR_OK) {
1318                                                         target->state = TARGET_UNKNOWN;
1319                                                         return retval;
1320                                                 }
1321                                                 isr_timed_out = ((timeval_ms() - t_start) > 500);
1322                                         } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1323
1324                                         /* only remove breakpoint if we created it */
1325                                         if (breakpoint)
1326                                                 cortex_m_unset_breakpoint(target, breakpoint);
1327                                         else {
1328                                                 /* Remove the temporary breakpoint */
1329                                                 breakpoint_remove(target, pc_value);
1330                                         }
1331
1332                                         if (isr_timed_out) {
1333                                                 LOG_TARGET_DEBUG(target, "Interrupt handlers didn't complete within time, "
1334                                                         "leaving target running");
1335                                         } else {
1336                                                 /* Step over next instruction with interrupts disabled */
1337                                                 cortex_m_set_maskints_for_step(target);
1338                                                 cortex_m_write_debug_halt_mask(target,
1339                                                         C_HALT | C_MASKINTS,
1340                                                         0);
1341                                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1342                                                 /* Re-enable interrupts if appropriate */
1343                                                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1344                                                 cortex_m_set_maskints_for_halt(target);
1345                                         }
1346                                 }
1347                         }
1348                 }
1349         }
1350
1351         retval = cortex_m_read_dhcsr_atomic_sticky(target);
1352         if (retval != ERROR_OK)
1353                 return retval;
1354
1355         /* registers are now invalid */
1356         register_cache_invalidate(armv7m->arm.core_cache);
1357
1358         if (breakpoint)
1359                 cortex_m_set_breakpoint(target, breakpoint);
1360
1361         if (isr_timed_out) {
1362                 /* Leave the core running. The user has to stop execution manually. */
1363                 target->debug_reason = DBG_REASON_NOTHALTED;
1364                 target->state = TARGET_RUNNING;
1365                 return ERROR_OK;
1366         }
1367
1368         LOG_TARGET_DEBUG(target, "target stepped dcb_dhcsr = 0x%" PRIx32
1369                 " nvic_icsr = 0x%" PRIx32,
1370                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1371
1372         retval = cortex_m_debug_entry(target);
1373         if (retval != ERROR_OK)
1374                 return retval;
1375         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1376
1377         LOG_TARGET_DEBUG(target, "target stepped dcb_dhcsr = 0x%" PRIx32
1378                 " nvic_icsr = 0x%" PRIx32,
1379                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1380
1381         return ERROR_OK;
1382 }
1383
1384 static int cortex_m_assert_reset(struct target *target)
1385 {
1386         struct cortex_m_common *cortex_m = target_to_cm(target);
1387         struct armv7m_common *armv7m = &cortex_m->armv7m;
1388         enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1389
1390         LOG_TARGET_DEBUG(target, "target->state: %s",
1391                 target_state_name(target));
1392
1393         enum reset_types jtag_reset_config = jtag_get_reset_config();
1394
1395         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1396                 /* allow scripts to override the reset event */
1397
1398                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1399                 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1400                 target->state = TARGET_RESET;
1401
1402                 return ERROR_OK;
1403         }
1404
1405         /* some cores support connecting while srst is asserted
1406          * use that mode is it has been configured */
1407
1408         bool srst_asserted = false;
1409
1410         if (!target_was_examined(target)) {
1411                 if (jtag_reset_config & RESET_HAS_SRST) {
1412                         adapter_assert_reset();
1413                         if (target->reset_halt)
1414                                 LOG_TARGET_ERROR(target, "Target not examined, will not halt after reset!");
1415                         return ERROR_OK;
1416                 } else {
1417                         LOG_TARGET_ERROR(target, "Target not examined, reset NOT asserted!");
1418                         return ERROR_FAIL;
1419                 }
1420         }
1421
1422         if ((jtag_reset_config & RESET_HAS_SRST) &&
1423             (jtag_reset_config & RESET_SRST_NO_GATING)) {
1424                 adapter_assert_reset();
1425                 srst_asserted = true;
1426         }
1427
1428         /* Enable debug requests */
1429         int retval = cortex_m_read_dhcsr_atomic_sticky(target);
1430
1431         /* Store important errors instead of failing and proceed to reset assert */
1432
1433         if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1434                 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1435
1436         /* If the processor is sleeping in a WFI or WFE instruction, the
1437          * C_HALT bit must be asserted to regain control */
1438         if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1439                 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1440
1441         mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1442         /* Ignore less important errors */
1443
1444         if (!target->reset_halt) {
1445                 /* Set/Clear C_MASKINTS in a separate operation */
1446                 cortex_m_set_maskints_for_run(target);
1447
1448                 /* clear any debug flags before resuming */
1449                 cortex_m_clear_halt(target);
1450
1451                 /* clear C_HALT in dhcsr reg */
1452                 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1453         } else {
1454                 /* Halt in debug on reset; endreset_event() restores DEMCR.
1455                  *
1456                  * REVISIT catching BUSERR presumably helps to defend against
1457                  * bad vector table entries.  Should this include MMERR or
1458                  * other flags too?
1459                  */
1460                 int retval2;
1461                 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1462                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1463                 if (retval != ERROR_OK || retval2 != ERROR_OK)
1464                         LOG_TARGET_INFO(target, "AP write error, reset will not halt");
1465         }
1466
1467         if (jtag_reset_config & RESET_HAS_SRST) {
1468                 /* default to asserting srst */
1469                 if (!srst_asserted)
1470                         adapter_assert_reset();
1471
1472                 /* srst is asserted, ignore AP access errors */
1473                 retval = ERROR_OK;
1474         } else {
1475                 /* Use a standard Cortex-M3 software reset mechanism.
1476                  * We default to using VECTRESET as it is supported on all current cores
1477                  * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1478                  * This has the disadvantage of not resetting the peripherals, so a
1479                  * reset-init event handler is needed to perform any peripheral resets.
1480                  */
1481                 if (!cortex_m->vectreset_supported
1482                                 && reset_config == CORTEX_M_RESET_VECTRESET) {
1483                         reset_config = CORTEX_M_RESET_SYSRESETREQ;
1484                         LOG_TARGET_WARNING(target, "VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1485                         LOG_TARGET_WARNING(target, "Set 'cortex_m reset_config sysresetreq'.");
1486                 }
1487
1488                 LOG_TARGET_DEBUG(target, "Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1489                         ? "SYSRESETREQ" : "VECTRESET");
1490
1491                 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1492                         LOG_TARGET_WARNING(target, "Only resetting the Cortex-M core, use a reset-init event "
1493                                 "handler to reset any peripherals or configure hardware srst support.");
1494                 }
1495
1496                 int retval3;
1497                 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1498                                 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1499                                 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1500                 if (retval3 != ERROR_OK)
1501                         LOG_TARGET_DEBUG(target, "Ignoring AP write error right after reset");
1502
1503                 retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1504                 if (retval3 != ERROR_OK) {
1505                         LOG_TARGET_ERROR(target, "DP initialisation failed");
1506                         /* The error return value must not be propagated in this case.
1507                          * SYSRESETREQ or VECTRESET have been possibly triggered
1508                          * so reset processing should continue */
1509                 } else {
1510                         /* I do not know why this is necessary, but it
1511                          * fixes strange effects (step/resume cause NMI
1512                          * after reset) on LM3S6918 -- Michael Schwingen
1513                          */
1514                         uint32_t tmp;
1515                         mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1516                 }
1517         }
1518
1519         target->state = TARGET_RESET;
1520         jtag_sleep(50000);
1521
1522         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1523
1524         /* now return stored error code if any */
1525         if (retval != ERROR_OK)
1526                 return retval;
1527
1528         if (target->reset_halt) {
1529                 retval = target_halt(target);
1530                 if (retval != ERROR_OK)
1531                         return retval;
1532         }
1533
1534         return ERROR_OK;
1535 }
1536
1537 static int cortex_m_deassert_reset(struct target *target)
1538 {
1539         struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1540
1541         LOG_TARGET_DEBUG(target, "target->state: %s",
1542                 target_state_name(target));
1543
1544         /* deassert reset lines */
1545         adapter_deassert_reset();
1546
1547         enum reset_types jtag_reset_config = jtag_get_reset_config();
1548
1549         if ((jtag_reset_config & RESET_HAS_SRST) &&
1550             !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1551                 target_was_examined(target)) {
1552
1553                 int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1554                 if (retval != ERROR_OK) {
1555                         LOG_TARGET_ERROR(target, "DP initialisation failed");
1556                         return retval;
1557                 }
1558         }
1559
1560         return ERROR_OK;
1561 }
1562
1563 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1564 {
1565         int retval;
1566         unsigned int fp_num = 0;
1567         struct cortex_m_common *cortex_m = target_to_cm(target);
1568         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1569
1570         if (breakpoint->is_set) {
1571                 LOG_TARGET_WARNING(target, "breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1572                 return ERROR_OK;
1573         }
1574
1575         if (breakpoint->type == BKPT_HARD) {
1576                 uint32_t fpcr_value;
1577                 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1578                         fp_num++;
1579                 if (fp_num >= cortex_m->fp_num_code) {
1580                         LOG_TARGET_ERROR(target, "Can not find free FPB Comparator!");
1581                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1582                 }
1583                 breakpoint_hw_set(breakpoint, fp_num);
1584                 fpcr_value = breakpoint->address | 1;
1585                 if (cortex_m->fp_rev == 0) {
1586                         if (breakpoint->address > 0x1FFFFFFF) {
1587                                 LOG_TARGET_ERROR(target, "Cortex-M Flash Patch Breakpoint rev.1 "
1588                                                 "cannot handle HW breakpoint above address 0x1FFFFFFE");
1589                                 return ERROR_FAIL;
1590                         }
1591                         uint32_t hilo;
1592                         hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1593                         fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1594                 } else if (cortex_m->fp_rev > 1) {
1595                         LOG_TARGET_ERROR(target, "Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1596                         return ERROR_FAIL;
1597                 }
1598                 comparator_list[fp_num].used = true;
1599                 comparator_list[fp_num].fpcr_value = fpcr_value;
1600                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1601                         comparator_list[fp_num].fpcr_value);
1602                 LOG_TARGET_DEBUG(target, "fpc_num %i fpcr_value 0x%" PRIx32 "",
1603                         fp_num,
1604                         comparator_list[fp_num].fpcr_value);
1605                 if (!cortex_m->fpb_enabled) {
1606                         LOG_TARGET_DEBUG(target, "FPB wasn't enabled, do it now");
1607                         retval = cortex_m_enable_fpb(target);
1608                         if (retval != ERROR_OK) {
1609                                 LOG_TARGET_ERROR(target, "Failed to enable the FPB");
1610                                 return retval;
1611                         }
1612
1613                         cortex_m->fpb_enabled = true;
1614                 }
1615         } else if (breakpoint->type == BKPT_SOFT) {
1616                 uint8_t code[4];
1617
1618                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1619                  * semihosting; don't use that.  Otherwise the BKPT
1620                  * parameter is arbitrary.
1621                  */
1622                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1623                 retval = target_read_memory(target,
1624                                 breakpoint->address & 0xFFFFFFFE,
1625                                 breakpoint->length, 1,
1626                                 breakpoint->orig_instr);
1627                 if (retval != ERROR_OK)
1628                         return retval;
1629                 retval = target_write_memory(target,
1630                                 breakpoint->address & 0xFFFFFFFE,
1631                                 breakpoint->length, 1,
1632                                 code);
1633                 if (retval != ERROR_OK)
1634                         return retval;
1635                 breakpoint->is_set = true;
1636         }
1637
1638         LOG_TARGET_DEBUG(target, "BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (n=%u)",
1639                 breakpoint->unique_id,
1640                 (int)(breakpoint->type),
1641                 breakpoint->address,
1642                 breakpoint->length,
1643                 (breakpoint->type == BKPT_SOFT) ? 0 : breakpoint->number);
1644
1645         return ERROR_OK;
1646 }
1647
1648 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1649 {
1650         int retval;
1651         struct cortex_m_common *cortex_m = target_to_cm(target);
1652         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1653
1654         if (!breakpoint->is_set) {
1655                 LOG_TARGET_WARNING(target, "breakpoint not set");
1656                 return ERROR_OK;
1657         }
1658
1659         LOG_TARGET_DEBUG(target, "BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (n=%u)",
1660                 breakpoint->unique_id,
1661                 (int)(breakpoint->type),
1662                 breakpoint->address,
1663                 breakpoint->length,
1664                 (breakpoint->type == BKPT_SOFT) ? 0 : breakpoint->number);
1665
1666         if (breakpoint->type == BKPT_HARD) {
1667                 unsigned int fp_num = breakpoint->number;
1668                 if (fp_num >= cortex_m->fp_num_code) {
1669                         LOG_TARGET_DEBUG(target, "Invalid FP Comparator number in breakpoint");
1670                         return ERROR_OK;
1671                 }
1672                 comparator_list[fp_num].used = false;
1673                 comparator_list[fp_num].fpcr_value = 0;
1674                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1675                         comparator_list[fp_num].fpcr_value);
1676         } else {
1677                 /* restore original instruction (kept in target endianness) */
1678                 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1679                                         breakpoint->length, 1,
1680                                         breakpoint->orig_instr);
1681                 if (retval != ERROR_OK)
1682                         return retval;
1683         }
1684         breakpoint->is_set = false;
1685
1686         return ERROR_OK;
1687 }
1688
1689 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1690 {
1691         if (breakpoint->length == 3) {
1692                 LOG_TARGET_DEBUG(target, "Using a two byte breakpoint for 32bit Thumb-2 request");
1693                 breakpoint->length = 2;
1694         }
1695
1696         if ((breakpoint->length != 2)) {
1697                 LOG_TARGET_INFO(target, "only breakpoints of two bytes length supported");
1698                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1699         }
1700
1701         return cortex_m_set_breakpoint(target, breakpoint);
1702 }
1703
1704 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1705 {
1706         if (!breakpoint->is_set)
1707                 return ERROR_OK;
1708
1709         return cortex_m_unset_breakpoint(target, breakpoint);
1710 }
1711
1712 static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1713 {
1714         unsigned int dwt_num = 0;
1715         struct cortex_m_common *cortex_m = target_to_cm(target);
1716
1717         /* REVISIT Don't fully trust these "not used" records ... users
1718          * may set up breakpoints by hand, e.g. dual-address data value
1719          * watchpoint using comparator #1; comparator #0 matching cycle
1720          * count; send data trace info through ITM and TPIU; etc
1721          */
1722         struct cortex_m_dwt_comparator *comparator;
1723
1724         for (comparator = cortex_m->dwt_comparator_list;
1725                 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1726                 comparator++, dwt_num++)
1727                 continue;
1728         if (dwt_num >= cortex_m->dwt_num_comp) {
1729                 LOG_TARGET_ERROR(target, "Can not find free DWT Comparator");
1730                 return ERROR_FAIL;
1731         }
1732         comparator->used = true;
1733         watchpoint_set(watchpoint, dwt_num);
1734
1735         comparator->comp = watchpoint->address;
1736         target_write_u32(target, comparator->dwt_comparator_address + 0,
1737                 comparator->comp);
1738
1739         if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1740                 uint32_t mask = 0, temp;
1741
1742                 /* watchpoint params were validated earlier */
1743                 temp = watchpoint->length;
1744                 while (temp) {
1745                         temp >>= 1;
1746                         mask++;
1747                 }
1748                 mask--;
1749
1750                 comparator->mask = mask;
1751                 target_write_u32(target, comparator->dwt_comparator_address + 4,
1752                         comparator->mask);
1753
1754                 switch (watchpoint->rw) {
1755                 case WPT_READ:
1756                         comparator->function = 5;
1757                         break;
1758                 case WPT_WRITE:
1759                         comparator->function = 6;
1760                         break;
1761                 case WPT_ACCESS:
1762                         comparator->function = 7;
1763                         break;
1764                 }
1765         } else {
1766                 uint32_t data_size = watchpoint->length >> 1;
1767                 comparator->mask = (watchpoint->length >> 1) | 1;
1768
1769                 switch (watchpoint->rw) {
1770                 case WPT_ACCESS:
1771                         comparator->function = 4;
1772                         break;
1773                 case WPT_WRITE:
1774                         comparator->function = 5;
1775                         break;
1776                 case WPT_READ:
1777                         comparator->function = 6;
1778                         break;
1779                 }
1780                 comparator->function = comparator->function | (1 << 4) |
1781                                 (data_size << 10);
1782         }
1783
1784         target_write_u32(target, comparator->dwt_comparator_address + 8,
1785                 comparator->function);
1786
1787         LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1788                 watchpoint->unique_id, dwt_num,
1789                 (unsigned) comparator->comp,
1790                 (unsigned) comparator->mask,
1791                 (unsigned) comparator->function);
1792         return ERROR_OK;
1793 }
1794
1795 static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1796 {
1797         struct cortex_m_common *cortex_m = target_to_cm(target);
1798         struct cortex_m_dwt_comparator *comparator;
1799
1800         if (!watchpoint->is_set) {
1801                 LOG_TARGET_WARNING(target, "watchpoint (wpid: %d) not set",
1802                         watchpoint->unique_id);
1803                 return ERROR_OK;
1804         }
1805
1806         unsigned int dwt_num = watchpoint->number;
1807
1808         LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%u address: 0x%08x clear",
1809                 watchpoint->unique_id, dwt_num,
1810                 (unsigned) watchpoint->address);
1811
1812         if (dwt_num >= cortex_m->dwt_num_comp) {
1813                 LOG_TARGET_DEBUG(target, "Invalid DWT Comparator number in watchpoint");
1814                 return ERROR_OK;
1815         }
1816
1817         comparator = cortex_m->dwt_comparator_list + dwt_num;
1818         comparator->used = false;
1819         comparator->function = 0;
1820         target_write_u32(target, comparator->dwt_comparator_address + 8,
1821                 comparator->function);
1822
1823         watchpoint->is_set = false;
1824
1825         return ERROR_OK;
1826 }
1827
1828 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1829 {
1830         struct cortex_m_common *cortex_m = target_to_cm(target);
1831
1832         if (cortex_m->dwt_comp_available < 1) {
1833                 LOG_TARGET_DEBUG(target, "no comparators?");
1834                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1835         }
1836
1837         /* hardware doesn't support data value masking */
1838         if (watchpoint->mask != ~(uint32_t)0) {
1839                 LOG_TARGET_DEBUG(target, "watchpoint value masks not supported");
1840                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1841         }
1842
1843         /* hardware allows address masks of up to 32K */
1844         unsigned mask;
1845
1846         for (mask = 0; mask < 16; mask++) {
1847                 if ((1u << mask) == watchpoint->length)
1848                         break;
1849         }
1850         if (mask == 16) {
1851                 LOG_TARGET_DEBUG(target, "unsupported watchpoint length");
1852                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1853         }
1854         if (watchpoint->address & ((1 << mask) - 1)) {
1855                 LOG_TARGET_DEBUG(target, "watchpoint address is unaligned");
1856                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1857         }
1858
1859         /* Caller doesn't seem to be able to describe watching for data
1860          * values of zero; that flags "no value".
1861          *
1862          * REVISIT This DWT may well be able to watch for specific data
1863          * values.  Requires comparator #1 to set DATAVMATCH and match
1864          * the data, and another comparator (DATAVADDR0) matching addr.
1865          */
1866         if (watchpoint->value) {
1867                 LOG_TARGET_DEBUG(target, "data value watchpoint not YET supported");
1868                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1869         }
1870
1871         cortex_m->dwt_comp_available--;
1872         LOG_TARGET_DEBUG(target, "dwt_comp_available: %d", cortex_m->dwt_comp_available);
1873
1874         return ERROR_OK;
1875 }
1876
1877 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1878 {
1879         struct cortex_m_common *cortex_m = target_to_cm(target);
1880
1881         /* REVISIT why check? DWT can be updated with core running ... */
1882         if (target->state != TARGET_HALTED) {
1883                 LOG_TARGET_WARNING(target, "target not halted");
1884                 return ERROR_TARGET_NOT_HALTED;
1885         }
1886
1887         if (watchpoint->is_set)
1888                 cortex_m_unset_watchpoint(target, watchpoint);
1889
1890         cortex_m->dwt_comp_available++;
1891         LOG_TARGET_DEBUG(target, "dwt_comp_available: %d", cortex_m->dwt_comp_available);
1892
1893         return ERROR_OK;
1894 }
1895
1896 int cortex_m_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1897 {
1898         if (target->debug_reason != DBG_REASON_WATCHPOINT)
1899                 return ERROR_FAIL;
1900
1901         struct cortex_m_common *cortex_m = target_to_cm(target);
1902
1903         for (struct watchpoint *wp = target->watchpoints; wp; wp = wp->next) {
1904                 if (!wp->is_set)
1905                         continue;
1906
1907                 unsigned int dwt_num = wp->number;
1908                 struct cortex_m_dwt_comparator *comparator = cortex_m->dwt_comparator_list + dwt_num;
1909
1910                 uint32_t dwt_function;
1911                 int retval = target_read_u32(target, comparator->dwt_comparator_address + 8, &dwt_function);
1912                 if (retval != ERROR_OK)
1913                         return ERROR_FAIL;
1914
1915                 /* check the MATCHED bit */
1916                 if (dwt_function & BIT(24)) {
1917                         *hit_watchpoint = wp;
1918                         return ERROR_OK;
1919                 }
1920         }
1921
1922         return ERROR_FAIL;
1923 }
1924
1925 void cortex_m_enable_watchpoints(struct target *target)
1926 {
1927         struct watchpoint *watchpoint = target->watchpoints;
1928
1929         /* set any pending watchpoints */
1930         while (watchpoint) {
1931                 if (!watchpoint->is_set)
1932                         cortex_m_set_watchpoint(target, watchpoint);
1933                 watchpoint = watchpoint->next;
1934         }
1935 }
1936
1937 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1938         uint32_t size, uint32_t count, uint8_t *buffer)
1939 {
1940         struct armv7m_common *armv7m = target_to_armv7m(target);
1941
1942         if (armv7m->arm.arch == ARM_ARCH_V6M) {
1943                 /* armv6m does not handle unaligned memory access */
1944                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1945                         return ERROR_TARGET_UNALIGNED_ACCESS;
1946         }
1947
1948         return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1949 }
1950
1951 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1952         uint32_t size, uint32_t count, const uint8_t *buffer)
1953 {
1954         struct armv7m_common *armv7m = target_to_armv7m(target);
1955
1956         if (armv7m->arm.arch == ARM_ARCH_V6M) {
1957                 /* armv6m does not handle unaligned memory access */
1958                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1959                         return ERROR_TARGET_UNALIGNED_ACCESS;
1960         }
1961
1962         return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1963 }
1964
1965 static int cortex_m_init_target(struct command_context *cmd_ctx,
1966         struct target *target)
1967 {
1968         armv7m_build_reg_cache(target);
1969         arm_semihosting_init(target);
1970         return ERROR_OK;
1971 }
1972
1973 void cortex_m_deinit_target(struct target *target)
1974 {
1975         struct cortex_m_common *cortex_m = target_to_cm(target);
1976         struct armv7m_common *armv7m = target_to_armv7m(target);
1977
1978         if (!armv7m->is_hla_target && armv7m->debug_ap)
1979                 dap_put_ap(armv7m->debug_ap);
1980
1981         free(cortex_m->fp_comparator_list);
1982
1983         cortex_m_dwt_free(target);
1984         armv7m_free_reg_cache(target);
1985
1986         free(target->private_config);
1987         free(cortex_m);
1988 }
1989
1990 int cortex_m_profiling(struct target *target, uint32_t *samples,
1991                               uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1992 {
1993         struct timeval timeout, now;
1994         struct armv7m_common *armv7m = target_to_armv7m(target);
1995         uint32_t reg_value;
1996         int retval;
1997
1998         retval = target_read_u32(target, DWT_PCSR, &reg_value);
1999         if (retval != ERROR_OK) {
2000                 LOG_TARGET_ERROR(target, "Error while reading PCSR");
2001                 return retval;
2002         }
2003         if (reg_value == 0) {
2004                 LOG_TARGET_INFO(target, "PCSR sampling not supported on this processor.");
2005                 return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
2006         }
2007
2008         gettimeofday(&timeout, NULL);
2009         timeval_add_time(&timeout, seconds, 0);
2010
2011         LOG_TARGET_INFO(target, "Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
2012
2013         /* Make sure the target is running */
2014         target_poll(target);
2015         if (target->state == TARGET_HALTED)
2016                 retval = target_resume(target, 1, 0, 0, 0);
2017
2018         if (retval != ERROR_OK) {
2019                 LOG_TARGET_ERROR(target, "Error while resuming target");
2020                 return retval;
2021         }
2022
2023         uint32_t sample_count = 0;
2024
2025         for (;;) {
2026                 if (armv7m && armv7m->debug_ap) {
2027                         uint32_t read_count = max_num_samples - sample_count;
2028                         if (read_count > 1024)
2029                                 read_count = 1024;
2030
2031                         retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
2032                                                 (void *)&samples[sample_count],
2033                                                 4, read_count, DWT_PCSR);
2034                         sample_count += read_count;
2035                 } else {
2036                         target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
2037                 }
2038
2039                 if (retval != ERROR_OK) {
2040                         LOG_TARGET_ERROR(target, "Error while reading PCSR");
2041                         return retval;
2042                 }
2043
2044
2045                 gettimeofday(&now, NULL);
2046                 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
2047                         LOG_TARGET_INFO(target, "Profiling completed. %" PRIu32 " samples.", sample_count);
2048                         break;
2049                 }
2050         }
2051
2052         *num_samples = sample_count;
2053         return retval;
2054 }
2055
2056
2057 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
2058  * on r/w if the core is not running, and clear on resume or reset ... or
2059  * at least, in a post_restore_context() method.
2060  */
2061
2062 struct dwt_reg_state {
2063         struct target *target;
2064         uint32_t addr;
2065         uint8_t value[4];               /* scratch/cache */
2066 };
2067
2068 static int cortex_m_dwt_get_reg(struct reg *reg)
2069 {
2070         struct dwt_reg_state *state = reg->arch_info;
2071
2072         uint32_t tmp;
2073         int retval = target_read_u32(state->target, state->addr, &tmp);
2074         if (retval != ERROR_OK)
2075                 return retval;
2076
2077         buf_set_u32(state->value, 0, 32, tmp);
2078         return ERROR_OK;
2079 }
2080
2081 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
2082 {
2083         struct dwt_reg_state *state = reg->arch_info;
2084
2085         return target_write_u32(state->target, state->addr,
2086                         buf_get_u32(buf, 0, reg->size));
2087 }
2088
2089 struct dwt_reg {
2090         uint32_t addr;
2091         const char *name;
2092         unsigned size;
2093 };
2094
2095 static const struct dwt_reg dwt_base_regs[] = {
2096         { DWT_CTRL, "dwt_ctrl", 32, },
2097         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
2098          * increments while the core is asleep.
2099          */
2100         { DWT_CYCCNT, "dwt_cyccnt", 32, },
2101         /* plus some 8 bit counters, useful for profiling with TPIU */
2102 };
2103
2104 static const struct dwt_reg dwt_comp[] = {
2105 #define DWT_COMPARATOR(i) \
2106                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
2107                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
2108                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
2109         DWT_COMPARATOR(0),
2110         DWT_COMPARATOR(1),
2111         DWT_COMPARATOR(2),
2112         DWT_COMPARATOR(3),
2113         DWT_COMPARATOR(4),
2114         DWT_COMPARATOR(5),
2115         DWT_COMPARATOR(6),
2116         DWT_COMPARATOR(7),
2117         DWT_COMPARATOR(8),
2118         DWT_COMPARATOR(9),
2119         DWT_COMPARATOR(10),
2120         DWT_COMPARATOR(11),
2121         DWT_COMPARATOR(12),
2122         DWT_COMPARATOR(13),
2123         DWT_COMPARATOR(14),
2124         DWT_COMPARATOR(15),
2125 #undef DWT_COMPARATOR
2126 };
2127
2128 static const struct reg_arch_type dwt_reg_type = {
2129         .get = cortex_m_dwt_get_reg,
2130         .set = cortex_m_dwt_set_reg,
2131 };
2132
2133 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
2134 {
2135         struct dwt_reg_state *state;
2136
2137         state = calloc(1, sizeof(*state));
2138         if (!state)
2139                 return;
2140         state->addr = d->addr;
2141         state->target = t;
2142
2143         r->name = d->name;
2144         r->size = d->size;
2145         r->value = state->value;
2146         r->arch_info = state;
2147         r->type = &dwt_reg_type;
2148 }
2149
2150 static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
2151 {
2152         uint32_t dwtcr;
2153         struct reg_cache *cache;
2154         struct cortex_m_dwt_comparator *comparator;
2155         int reg;
2156
2157         target_read_u32(target, DWT_CTRL, &dwtcr);
2158         LOG_TARGET_DEBUG(target, "DWT_CTRL: 0x%" PRIx32, dwtcr);
2159         if (!dwtcr) {
2160                 LOG_TARGET_DEBUG(target, "no DWT");
2161                 return;
2162         }
2163
2164         target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
2165         LOG_TARGET_DEBUG(target, "DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
2166
2167         cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
2168         cm->dwt_comp_available = cm->dwt_num_comp;
2169         cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
2170                         sizeof(struct cortex_m_dwt_comparator));
2171         if (!cm->dwt_comparator_list) {
2172 fail0:
2173                 cm->dwt_num_comp = 0;
2174                 LOG_TARGET_ERROR(target, "out of mem");
2175                 return;
2176         }
2177
2178         cache = calloc(1, sizeof(*cache));
2179         if (!cache) {
2180 fail1:
2181                 free(cm->dwt_comparator_list);
2182                 goto fail0;
2183         }
2184         cache->name = "Cortex-M DWT registers";
2185         cache->num_regs = 2 + cm->dwt_num_comp * 3;
2186         cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
2187         if (!cache->reg_list) {
2188                 free(cache);
2189                 goto fail1;
2190         }
2191
2192         for (reg = 0; reg < 2; reg++)
2193                 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2194                         dwt_base_regs + reg);
2195
2196         comparator = cm->dwt_comparator_list;
2197         for (unsigned int i = 0; i < cm->dwt_num_comp; i++, comparator++) {
2198                 int j;
2199
2200                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
2201                 for (j = 0; j < 3; j++, reg++)
2202                         cortex_m_dwt_addreg(target, cache->reg_list + reg,
2203                                 dwt_comp + 3 * i + j);
2204
2205                 /* make sure we clear any watchpoints enabled on the target */
2206                 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
2207         }
2208
2209         *register_get_last_cache_p(&target->reg_cache) = cache;
2210         cm->dwt_cache = cache;
2211
2212         LOG_TARGET_DEBUG(target, "DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
2213                 dwtcr, cm->dwt_num_comp,
2214                 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
2215
2216         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
2217          * implement single-address data value watchpoints ... so we
2218          * won't need to check it later, when asked to set one up.
2219          */
2220 }
2221
2222 static void cortex_m_dwt_free(struct target *target)
2223 {
2224         struct cortex_m_common *cm = target_to_cm(target);
2225         struct reg_cache *cache = cm->dwt_cache;
2226
2227         free(cm->dwt_comparator_list);
2228         cm->dwt_comparator_list = NULL;
2229         cm->dwt_num_comp = 0;
2230
2231         if (cache) {
2232                 register_unlink_cache(&target->reg_cache, cache);
2233
2234                 if (cache->reg_list) {
2235                         for (size_t i = 0; i < cache->num_regs; i++)
2236                                 free(cache->reg_list[i].arch_info);
2237                         free(cache->reg_list);
2238                 }
2239                 free(cache);
2240         }
2241         cm->dwt_cache = NULL;
2242 }
2243
2244 #define MVFR0 0xe000ef40
2245 #define MVFR1 0xe000ef44
2246
2247 #define MVFR0_DEFAULT_M4 0x10110021
2248 #define MVFR1_DEFAULT_M4 0x11000011
2249
2250 #define MVFR0_DEFAULT_M7_SP 0x10110021
2251 #define MVFR0_DEFAULT_M7_DP 0x10110221
2252 #define MVFR1_DEFAULT_M7_SP 0x11000011
2253 #define MVFR1_DEFAULT_M7_DP 0x12000011
2254
2255 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
2256                 struct adiv5_ap **debug_ap)
2257 {
2258         if (dap_find_get_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
2259                 return ERROR_OK;
2260
2261         return dap_find_get_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
2262 }
2263
2264 int cortex_m_examine(struct target *target)
2265 {
2266         int retval;
2267         uint32_t cpuid, fpcr, mvfr0, mvfr1;
2268         struct cortex_m_common *cortex_m = target_to_cm(target);
2269         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2270         struct armv7m_common *armv7m = target_to_armv7m(target);
2271
2272         /* hla_target shares the examine handler but does not support
2273          * all its calls */
2274         if (!armv7m->is_hla_target) {
2275                 if (armv7m->debug_ap) {
2276                         dap_put_ap(armv7m->debug_ap);
2277                         armv7m->debug_ap = NULL;
2278                 }
2279
2280                 if (cortex_m->apsel == DP_APSEL_INVALID) {
2281                         /* Search for the MEM-AP */
2282                         retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
2283                         if (retval != ERROR_OK) {
2284                                 LOG_TARGET_ERROR(target, "Could not find MEM-AP to control the core");
2285                                 return retval;
2286                         }
2287                 } else {
2288                         armv7m->debug_ap = dap_get_ap(swjdp, cortex_m->apsel);
2289                         if (!armv7m->debug_ap) {
2290                                 LOG_ERROR("Cannot get AP");
2291                                 return ERROR_FAIL;
2292                         }
2293                 }
2294
2295                 armv7m->debug_ap->memaccess_tck = 8;
2296
2297                 retval = mem_ap_init(armv7m->debug_ap);
2298                 if (retval != ERROR_OK)
2299                         return retval;
2300         }
2301
2302         if (!target_was_examined(target)) {
2303                 target_set_examined(target);
2304
2305                 /* Read from Device Identification Registers */
2306                 retval = target_read_u32(target, CPUID, &cpuid);
2307                 if (retval != ERROR_OK)
2308                         return retval;
2309
2310                 /* Get ARCH and CPU types */
2311                 const enum cortex_m_partno core_partno = (cpuid & ARM_CPUID_PARTNO_MASK) >> ARM_CPUID_PARTNO_POS;
2312
2313                 for (unsigned int n = 0; n < ARRAY_SIZE(cortex_m_parts); n++) {
2314                         if (core_partno == cortex_m_parts[n].partno) {
2315                                 cortex_m->core_info = &cortex_m_parts[n];
2316                                 break;
2317                         }
2318                 }
2319
2320                 if (!cortex_m->core_info) {
2321                         LOG_TARGET_ERROR(target, "Cortex-M PARTNO 0x%x is unrecognized", core_partno);
2322                         return ERROR_FAIL;
2323                 }
2324
2325                 armv7m->arm.arch = cortex_m->core_info->arch;
2326
2327                 LOG_TARGET_INFO(target, "%s r%" PRId8 "p%" PRId8 " processor detected",
2328                                 cortex_m->core_info->name,
2329                                 (uint8_t)((cpuid >> 20) & 0xf),
2330                                 (uint8_t)((cpuid >> 0) & 0xf));
2331
2332                 cortex_m->maskints_erratum = false;
2333                 if (core_partno == CORTEX_M7_PARTNO) {
2334                         uint8_t rev, patch;
2335                         rev = (cpuid >> 20) & 0xf;
2336                         patch = (cpuid >> 0) & 0xf;
2337                         if ((rev == 0) && (patch < 2)) {
2338                                 LOG_TARGET_WARNING(target, "Silicon bug: single stepping may enter pending exception handler!");
2339                                 cortex_m->maskints_erratum = true;
2340                         }
2341                 }
2342                 LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32 "", cpuid);
2343
2344                 if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV4) {
2345                         target_read_u32(target, MVFR0, &mvfr0);
2346                         target_read_u32(target, MVFR1, &mvfr1);
2347
2348                         /* test for floating point feature on Cortex-M4 */
2349                         if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2350                                 LOG_TARGET_DEBUG(target, "%s floating point feature FPv4_SP found", cortex_m->core_info->name);
2351                                 armv7m->fp_feature = FPV4_SP;
2352                         }
2353                 } else if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV5) {
2354                         target_read_u32(target, MVFR0, &mvfr0);
2355                         target_read_u32(target, MVFR1, &mvfr1);
2356
2357                         /* test for floating point features on Cortex-M7 */
2358                         if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2359                                 LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_SP found", cortex_m->core_info->name);
2360                                 armv7m->fp_feature = FPV5_SP;
2361                         } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2362                                 LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_DP found", cortex_m->core_info->name);
2363                                 armv7m->fp_feature = FPV5_DP;
2364                         }
2365                 }
2366
2367                 /* VECTRESET is supported only on ARMv7-M cores */
2368                 cortex_m->vectreset_supported = armv7m->arm.arch == ARM_ARCH_V7M;
2369
2370                 /* Check for FPU, otherwise mark FPU register as non-existent */
2371                 if (armv7m->fp_feature == FP_NONE)
2372                         for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
2373                                 armv7m->arm.core_cache->reg_list[idx].exist = false;
2374
2375                 if (armv7m->arm.arch != ARM_ARCH_V8M)
2376                         for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
2377                                 armv7m->arm.core_cache->reg_list[idx].exist = false;
2378
2379                 if (!armv7m->is_hla_target) {
2380                         if (cortex_m->core_info->flags & CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K)
2381                                 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2382                                  * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2383                                 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2384                 }
2385
2386                 retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
2387                 if (retval != ERROR_OK)
2388                         return retval;
2389                 cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
2390
2391                 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
2392                         /* Enable debug requests */
2393                         uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
2394
2395                         retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
2396                         if (retval != ERROR_OK)
2397                                 return retval;
2398                         cortex_m->dcb_dhcsr = dhcsr;
2399                 }
2400
2401                 /* Configure trace modules */
2402                 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2403                 if (retval != ERROR_OK)
2404                         return retval;
2405
2406                 if (armv7m->trace_config.itm_deferred_config)
2407                         armv7m_trace_itm_config(target);
2408
2409                 /* NOTE: FPB and DWT are both optional. */
2410
2411                 /* Setup FPB */
2412                 target_read_u32(target, FP_CTRL, &fpcr);
2413                 /* bits [14:12] and [7:4] */
2414                 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2415                 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2416                 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2417                    Revision is zero base, fp_rev == 1 means Rev.2 ! */
2418                 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2419                 free(cortex_m->fp_comparator_list);
2420                 cortex_m->fp_comparator_list = calloc(
2421                                 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2422                                 sizeof(struct cortex_m_fp_comparator));
2423                 cortex_m->fpb_enabled = fpcr & 1;
2424                 for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2425                         cortex_m->fp_comparator_list[i].type =
2426                                 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2427                         cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2428
2429                         /* make sure we clear any breakpoints enabled on the target */
2430                         target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2431                 }
2432                 LOG_TARGET_DEBUG(target, "FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2433                         fpcr,
2434                         cortex_m->fp_num_code,
2435                         cortex_m->fp_num_lit);
2436
2437                 /* Setup DWT */
2438                 cortex_m_dwt_free(target);
2439                 cortex_m_dwt_setup(cortex_m, target);
2440
2441                 /* These hardware breakpoints only work for code in flash! */
2442                 LOG_TARGET_INFO(target, "target has %d breakpoints, %d watchpoints",
2443                         cortex_m->fp_num_code,
2444                         cortex_m->dwt_num_comp);
2445         }
2446
2447         return ERROR_OK;
2448 }
2449
2450 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2451 {
2452         struct armv7m_common *armv7m = target_to_armv7m(target);
2453         uint16_t dcrdr;
2454         uint8_t buf[2];
2455         int retval;
2456
2457         retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2458         if (retval != ERROR_OK)
2459                 return retval;
2460
2461         dcrdr = target_buffer_get_u16(target, buf);
2462         *ctrl = (uint8_t)dcrdr;
2463         *value = (uint8_t)(dcrdr >> 8);
2464
2465         LOG_TARGET_DEBUG(target, "data 0x%x ctrl 0x%x", *value, *ctrl);
2466
2467         /* write ack back to software dcc register
2468          * signify we have read data */
2469         if (dcrdr & (1 << 0)) {
2470                 target_buffer_set_u16(target, buf, 0);
2471                 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2472                 if (retval != ERROR_OK)
2473                         return retval;
2474         }
2475
2476         return ERROR_OK;
2477 }
2478
2479 static int cortex_m_target_request_data(struct target *target,
2480         uint32_t size, uint8_t *buffer)
2481 {
2482         uint8_t data;
2483         uint8_t ctrl;
2484         uint32_t i;
2485
2486         for (i = 0; i < (size * 4); i++) {
2487                 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2488                 if (retval != ERROR_OK)
2489                         return retval;
2490                 buffer[i] = data;
2491         }
2492
2493         return ERROR_OK;
2494 }
2495
2496 static int cortex_m_handle_target_request(void *priv)
2497 {
2498         struct target *target = priv;
2499         if (!target_was_examined(target))
2500                 return ERROR_OK;
2501
2502         if (!target->dbg_msg_enabled)
2503                 return ERROR_OK;
2504
2505         if (target->state == TARGET_RUNNING) {
2506                 uint8_t data;
2507                 uint8_t ctrl;
2508                 int retval;
2509
2510                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2511                 if (retval != ERROR_OK)
2512                         return retval;
2513
2514                 /* check if we have data */
2515                 if (ctrl & (1 << 0)) {
2516                         uint32_t request;
2517
2518                         /* we assume target is quick enough */
2519                         request = data;
2520                         for (int i = 1; i <= 3; i++) {
2521                                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2522                                 if (retval != ERROR_OK)
2523                                         return retval;
2524                                 request |= ((uint32_t)data << (i * 8));
2525                         }
2526                         target_request(target, request);
2527                 }
2528         }
2529
2530         return ERROR_OK;
2531 }
2532
2533 static int cortex_m_init_arch_info(struct target *target,
2534         struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2535 {
2536         struct armv7m_common *armv7m = &cortex_m->armv7m;
2537
2538         armv7m_init_arch_info(target, armv7m);
2539
2540         /* default reset mode is to use srst if fitted
2541          * if not it will use CORTEX_M3_RESET_VECTRESET */
2542         cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2543
2544         armv7m->arm.dap = dap;
2545
2546         /* register arch-specific functions */
2547         armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2548
2549         armv7m->post_debug_entry = NULL;
2550
2551         armv7m->pre_restore_context = NULL;
2552
2553         armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2554         armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2555
2556         target_register_timer_callback(cortex_m_handle_target_request, 1,
2557                 TARGET_TIMER_TYPE_PERIODIC, target);
2558
2559         return ERROR_OK;
2560 }
2561
2562 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2563 {
2564         struct adiv5_private_config *pc;
2565
2566         pc = (struct adiv5_private_config *)target->private_config;
2567         if (adiv5_verify_config(pc) != ERROR_OK)
2568                 return ERROR_FAIL;
2569
2570         struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2571         if (!cortex_m) {
2572                 LOG_TARGET_ERROR(target, "No memory creating target");
2573                 return ERROR_FAIL;
2574         }
2575
2576         cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2577         cortex_m->apsel = pc->ap_num;
2578
2579         cortex_m_init_arch_info(target, cortex_m, pc->dap);
2580
2581         return ERROR_OK;
2582 }
2583
2584 /*--------------------------------------------------------------------------*/
2585
2586 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2587         struct cortex_m_common *cm)
2588 {
2589         if (!is_cortex_m_with_dap_access(cm)) {
2590                 command_print(cmd, "target is not a Cortex-M");
2591                 return ERROR_TARGET_INVALID;
2592         }
2593         return ERROR_OK;
2594 }
2595
2596 /*
2597  * Only stuff below this line should need to verify that its target
2598  * is a Cortex-M3.  Everything else should have indirected through the
2599  * cortexm3_target structure, which is only used with CM3 targets.
2600  */
2601
2602 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2603 {
2604         struct target *target = get_current_target(CMD_CTX);
2605         struct cortex_m_common *cortex_m = target_to_cm(target);
2606         struct armv7m_common *armv7m = &cortex_m->armv7m;
2607         uint32_t demcr = 0;
2608         int retval;
2609
2610         static const struct {
2611                 char name[10];
2612                 unsigned mask;
2613         } vec_ids[] = {
2614                 { "hard_err",   VC_HARDERR, },
2615                 { "int_err",    VC_INTERR, },
2616                 { "bus_err",    VC_BUSERR, },
2617                 { "state_err",  VC_STATERR, },
2618                 { "chk_err",    VC_CHKERR, },
2619                 { "nocp_err",   VC_NOCPERR, },
2620                 { "mm_err",     VC_MMERR, },
2621                 { "reset",      VC_CORERESET, },
2622         };
2623
2624         retval = cortex_m_verify_pointer(CMD, cortex_m);
2625         if (retval != ERROR_OK)
2626                 return retval;
2627
2628         if (!target_was_examined(target)) {
2629                 LOG_TARGET_ERROR(target, "Target not examined yet");
2630                 return ERROR_FAIL;
2631         }
2632
2633         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2634         if (retval != ERROR_OK)
2635                 return retval;
2636
2637         if (CMD_ARGC > 0) {
2638                 unsigned catch = 0;
2639
2640                 if (CMD_ARGC == 1) {
2641                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2642                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2643                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2644                                         | VC_MMERR | VC_CORERESET;
2645                                 goto write;
2646                         } else if (strcmp(CMD_ARGV[0], "none") == 0)
2647                                 goto write;
2648                 }
2649                 while (CMD_ARGC-- > 0) {
2650                         unsigned i;
2651                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2652                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2653                                         continue;
2654                                 catch |= vec_ids[i].mask;
2655                                 break;
2656                         }
2657                         if (i == ARRAY_SIZE(vec_ids)) {
2658                                 LOG_TARGET_ERROR(target, "No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2659                                 return ERROR_COMMAND_SYNTAX_ERROR;
2660                         }
2661                 }
2662 write:
2663                 /* For now, armv7m->demcr only stores vector catch flags. */
2664                 armv7m->demcr = catch;
2665
2666                 demcr &= ~0xffff;
2667                 demcr |= catch;
2668
2669                 /* write, but don't assume it stuck (why not??) */
2670                 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2671                 if (retval != ERROR_OK)
2672                         return retval;
2673                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2674                 if (retval != ERROR_OK)
2675                         return retval;
2676
2677                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2678                  * Otherwise the vector catch hardware could fire when there's
2679                  * no debugger hooked up, causing much confusion...
2680                  */
2681         }
2682
2683         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2684                 command_print(CMD, "%9s: %s", vec_ids[i].name,
2685                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2686         }
2687
2688         return ERROR_OK;
2689 }
2690
2691 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2692 {
2693         struct target *target = get_current_target(CMD_CTX);
2694         struct cortex_m_common *cortex_m = target_to_cm(target);
2695         int retval;
2696
2697         static const struct jim_nvp nvp_maskisr_modes[] = {
2698                 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2699                 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2700                 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2701                 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2702                 { .name = NULL, .value = -1 },
2703         };
2704         const struct jim_nvp *n;
2705
2706
2707         retval = cortex_m_verify_pointer(CMD, cortex_m);
2708         if (retval != ERROR_OK)
2709                 return retval;
2710
2711         if (target->state != TARGET_HALTED) {
2712                 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2713                 return ERROR_OK;
2714         }
2715
2716         if (CMD_ARGC > 0) {
2717                 n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2718                 if (!n->name)
2719                         return ERROR_COMMAND_SYNTAX_ERROR;
2720                 cortex_m->isrmasking_mode = n->value;
2721                 cortex_m_set_maskints_for_halt(target);
2722         }
2723
2724         n = jim_nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2725         command_print(CMD, "cortex_m interrupt mask %s", n->name);
2726
2727         return ERROR_OK;
2728 }
2729
2730 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2731 {
2732         struct target *target = get_current_target(CMD_CTX);
2733         struct cortex_m_common *cortex_m = target_to_cm(target);
2734         int retval;
2735         char *reset_config;
2736
2737         retval = cortex_m_verify_pointer(CMD, cortex_m);
2738         if (retval != ERROR_OK)
2739                 return retval;
2740
2741         if (CMD_ARGC > 0) {
2742                 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2743                         cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2744
2745                 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2746                         if (target_was_examined(target)
2747                                         && !cortex_m->vectreset_supported)
2748                                 LOG_TARGET_WARNING(target, "VECTRESET is not supported on your Cortex-M core!");
2749                         else
2750                                 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2751
2752                 } else
2753                         return ERROR_COMMAND_SYNTAX_ERROR;
2754         }
2755
2756         switch (cortex_m->soft_reset_config) {
2757                 case CORTEX_M_RESET_SYSRESETREQ:
2758                         reset_config = "sysresetreq";
2759                         break;
2760
2761                 case CORTEX_M_RESET_VECTRESET:
2762                         reset_config = "vectreset";
2763                         break;
2764
2765                 default:
2766                         reset_config = "unknown";
2767                         break;
2768         }
2769
2770         command_print(CMD, "cortex_m reset_config %s", reset_config);
2771
2772         return ERROR_OK;
2773 }
2774
2775 static const struct command_registration cortex_m_exec_command_handlers[] = {
2776         {
2777                 .name = "maskisr",
2778                 .handler = handle_cortex_m_mask_interrupts_command,
2779                 .mode = COMMAND_EXEC,
2780                 .help = "mask cortex_m interrupts",
2781                 .usage = "['auto'|'on'|'off'|'steponly']",
2782         },
2783         {
2784                 .name = "vector_catch",
2785                 .handler = handle_cortex_m_vector_catch_command,
2786                 .mode = COMMAND_EXEC,
2787                 .help = "configure hardware vectors to trigger debug entry",
2788                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2789         },
2790         {
2791                 .name = "reset_config",
2792                 .handler = handle_cortex_m_reset_config_command,
2793                 .mode = COMMAND_ANY,
2794                 .help = "configure software reset handling",
2795                 .usage = "['sysresetreq'|'vectreset']",
2796         },
2797         COMMAND_REGISTRATION_DONE
2798 };
2799 static const struct command_registration cortex_m_command_handlers[] = {
2800         {
2801                 .chain = armv7m_command_handlers,
2802         },
2803         {
2804                 .chain = armv7m_trace_command_handlers,
2805         },
2806         /* START_DEPRECATED_TPIU */
2807         {
2808                 .chain = arm_tpiu_deprecated_command_handlers,
2809         },
2810         /* END_DEPRECATED_TPIU */
2811         {
2812                 .name = "cortex_m",
2813                 .mode = COMMAND_EXEC,
2814                 .help = "Cortex-M command group",
2815                 .usage = "",
2816                 .chain = cortex_m_exec_command_handlers,
2817         },
2818         {
2819                 .chain = rtt_target_command_handlers,
2820         },
2821         COMMAND_REGISTRATION_DONE
2822 };
2823
2824 struct target_type cortexm_target = {
2825         .name = "cortex_m",
2826
2827         .poll = cortex_m_poll,
2828         .arch_state = armv7m_arch_state,
2829
2830         .target_request_data = cortex_m_target_request_data,
2831
2832         .halt = cortex_m_halt,
2833         .resume = cortex_m_resume,
2834         .step = cortex_m_step,
2835
2836         .assert_reset = cortex_m_assert_reset,
2837         .deassert_reset = cortex_m_deassert_reset,
2838         .soft_reset_halt = cortex_m_soft_reset_halt,
2839
2840         .get_gdb_arch = arm_get_gdb_arch,
2841         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2842
2843         .read_memory = cortex_m_read_memory,
2844         .write_memory = cortex_m_write_memory,
2845         .checksum_memory = armv7m_checksum_memory,
2846         .blank_check_memory = armv7m_blank_check_memory,
2847
2848         .run_algorithm = armv7m_run_algorithm,
2849         .start_algorithm = armv7m_start_algorithm,
2850         .wait_algorithm = armv7m_wait_algorithm,
2851
2852         .add_breakpoint = cortex_m_add_breakpoint,
2853         .remove_breakpoint = cortex_m_remove_breakpoint,
2854         .add_watchpoint = cortex_m_add_watchpoint,
2855         .remove_watchpoint = cortex_m_remove_watchpoint,
2856         .hit_watchpoint = cortex_m_hit_watchpoint,
2857
2858         .commands = cortex_m_command_handlers,
2859         .target_create = cortex_m_target_create,
2860         .target_jim_configure = adiv5_jim_configure,
2861         .init_target = cortex_m_init_target,
2862         .examine = cortex_m_examine,
2863         .deinit_target = cortex_m_deinit_target,
2864
2865         .profiling = cortex_m_profiling,
2866 };