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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  *                                                                         *
  24  *                                                                         *
  25  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  26  *                                                                         *
  27  ***************************************************************************/
  28 #ifdef HAVE_CONFIG_H
  29 #include "config.h"
  30 #endif
  31
  32 #include "jtag/interface.h"
  33 #include "breakpoints.h"
  34 #include "cortex_m.h"
  35 #include "target_request.h"
  36 #include "target_type.h"
  37 #include "arm_disassembler.h"
  38 #include "register.h"
  39 #include "arm_opcodes.h"
  40 #include "arm_semihosting.h"
  41 #include <helper/time_support.h>
  42
  43 /* NOTE:  most of this should work fine for the Cortex-M1 and
  44  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  45  * Some differences:  M0/M1 doesn't have FPB remapping or the
  46  * DWT tracing/profiling support.  (So the cycle counter will
  47  * not be usable; the other stuff isn't currently used here.)
  48  *
  49  * Although there are some workarounds for errata seen only in r0p0
  50  * silicon, such old parts are hard to find and thus not much tested
  51  * any longer.
  52  */
  53
  54 /* forward declarations */
  55 static int cortex_m_store_core_reg_u32(struct target *target,
  56                 uint32_t num, uint32_t value);
  57 static void cortex_m_dwt_free(struct target *target);
  58
  59 static int cortex_m_load_core_reg_u32(struct target *target,
  60                 uint32_t regsel, uint32_t *value)
  61 {
  62         struct armv7m_common *armv7m = target_to_armv7m(target);
  63         int retval;
  64         uint32_t dcrdr;
  65
  66         /* because the DCB_DCRDR is used for the emulated dcc channel
  67          * we have to save/restore the DCB_DCRDR when used */
  68         if (target->dbg_msg_enabled) {
  69                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
  70                 if (retval != ERROR_OK)
  71                         return retval;
  72         }
  73
  74         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
  75         if (retval != ERROR_OK)
  76                 return retval;
  77
  78         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
  79         if (retval != ERROR_OK)
  80                 return retval;
  81
  82         if (target->dbg_msg_enabled) {
  83                 /* restore DCB_DCRDR - this needs to be in a separate
  84                  * transaction otherwise the emulated DCC channel breaks */
  85                 if (retval == ERROR_OK)
  86                         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
  87         }
  88
  89         return retval;
  90 }
  91
  92 static int cortex_m_store_core_reg_u32(struct target *target,
  93                 uint32_t regsel, uint32_t value)
  94 {
  95         struct armv7m_common *armv7m = target_to_armv7m(target);
  96         int retval;
  97         uint32_t dcrdr;
  98
  99         /* because the DCB_DCRDR is used for the emulated dcc channel
 100          * we have to save/restore the DCB_DCRDR when used */
 101         if (target->dbg_msg_enabled) {
 102                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
 103                 if (retval != ERROR_OK)
 104                         return retval;
 105         }
 106
 107         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
 108         if (retval != ERROR_OK)
 109                 return retval;
 110
 111         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WnR);
 112         if (retval != ERROR_OK)
 113                 return retval;
 114
 115         if (target->dbg_msg_enabled) {
 116                 /* restore DCB_DCRDR - this needs to be in a separate
 117                  * transaction otherwise the emulated DCC channel breaks */
 118                 if (retval == ERROR_OK)
 119                         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
 120         }
 121
 122         return retval;
 123 }
 124
 125 static int cortex_m_write_debug_halt_mask(struct target *target,
 126         uint32_t mask_on, uint32_t mask_off)
 127 {
 128         struct cortex_m_common *cortex_m = target_to_cm(target);
 129         struct armv7m_common *armv7m = &cortex_m->armv7m;
 130
 131         /* mask off status bits */
 132         cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
 133         /* create new register mask */
 134         cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 135
 136         return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
 137 }
 138
 139 static int cortex_m_set_maskints(struct target *target, bool mask)
 140 {
 141         struct cortex_m_common *cortex_m = target_to_cm(target);
 142         if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
 143                 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
 144         else
 145                 return ERROR_OK;
 146 }
 147
 148 static int cortex_m_set_maskints_for_halt(struct target *target)
 149 {
 150         struct cortex_m_common *cortex_m = target_to_cm(target);
 151         switch (cortex_m->isrmasking_mode) {
 152                 case CORTEX_M_ISRMASK_AUTO:
 153                         /* interrupts taken at resume, whether for step or run -> no mask */
 154                         return cortex_m_set_maskints(target, false);
 155
 156                 case CORTEX_M_ISRMASK_OFF:
 157                         /* interrupts never masked */
 158                         return cortex_m_set_maskints(target, false);
 159
 160                 case CORTEX_M_ISRMASK_ON:
 161                         /* interrupts always masked */
 162                         return cortex_m_set_maskints(target, true);
 163
 164                 case CORTEX_M_ISRMASK_STEPONLY:
 165                         /* interrupts masked for single step only -> mask now if MASKINTS
 166                          * erratum, otherwise only mask before stepping */
 167                         return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
 168         }
 169         return ERROR_OK;
 170 }
 171
 172 static int cortex_m_set_maskints_for_run(struct target *target)
 173 {
 174         switch (target_to_cm(target)->isrmasking_mode) {
 175                 case CORTEX_M_ISRMASK_AUTO:
 176                         /* interrupts taken at resume, whether for step or run -> no mask */
 177                         return cortex_m_set_maskints(target, false);
 178
 179                 case CORTEX_M_ISRMASK_OFF:
 180                         /* interrupts never masked */
 181                         return cortex_m_set_maskints(target, false);
 182
 183                 case CORTEX_M_ISRMASK_ON:
 184                         /* interrupts always masked */
 185                         return cortex_m_set_maskints(target, true);
 186
 187                 case CORTEX_M_ISRMASK_STEPONLY:
 188                         /* interrupts masked for single step only -> no mask */
 189                         return cortex_m_set_maskints(target, false);
 190         }
 191         return ERROR_OK;
 192 }
 193
 194 static int cortex_m_set_maskints_for_step(struct target *target)
 195 {
 196         switch (target_to_cm(target)->isrmasking_mode) {
 197                 case CORTEX_M_ISRMASK_AUTO:
 198                         /* the auto-interrupt should already be done -> mask */
 199                         return cortex_m_set_maskints(target, true);
 200
 201                 case CORTEX_M_ISRMASK_OFF:
 202                         /* interrupts never masked */
 203                         return cortex_m_set_maskints(target, false);
 204
 205                 case CORTEX_M_ISRMASK_ON:
 206                         /* interrupts always masked */
 207                         return cortex_m_set_maskints(target, true);
 208
 209                 case CORTEX_M_ISRMASK_STEPONLY:
 210                         /* interrupts masked for single step only -> mask */
 211                         return cortex_m_set_maskints(target, true);
 212         }
 213         return ERROR_OK;
 214 }
 215
 216 static int cortex_m_clear_halt(struct target *target)
 217 {
 218         struct cortex_m_common *cortex_m = target_to_cm(target);
 219         struct armv7m_common *armv7m = &cortex_m->armv7m;
 220         int retval;
 221
 222         /* clear step if any */
 223         cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
 224
 225         /* Read Debug Fault Status Register */
 226         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
 227         if (retval != ERROR_OK)
 228                 return retval;
 229
 230         /* Clear Debug Fault Status */
 231         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
 232         if (retval != ERROR_OK)
 233                 return retval;
 234         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
 235
 236         return ERROR_OK;
 237 }
 238
 239 static int cortex_m_single_step_core(struct target *target)
 240 {
 241         struct cortex_m_common *cortex_m = target_to_cm(target);
 242         struct armv7m_common *armv7m = &cortex_m->armv7m;
 243         int retval;
 244
 245         /* Mask interrupts before clearing halt, if not done already.  This avoids
 246          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 247          * HALT can put the core into an unknown state.
 248          */
 249         if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
 250                 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
 251                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 252                 if (retval != ERROR_OK)
 253                         return retval;
 254         }
 255         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
 256                         DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 257         if (retval != ERROR_OK)
 258                 return retval;
 259         LOG_DEBUG(" ");
 260
 261         /* restore dhcsr reg */
 262         cortex_m_clear_halt(target);
 263
 264         return ERROR_OK;
 265 }
 266
 267 static int cortex_m_enable_fpb(struct target *target)
 268 {
 269         int retval = target_write_u32(target, FP_CTRL, 3);
 270         if (retval != ERROR_OK)
 271                 return retval;
 272
 273         /* check the fpb is actually enabled */
 274         uint32_t fpctrl;
 275         retval = target_read_u32(target, FP_CTRL, &fpctrl);
 276         if (retval != ERROR_OK)
 277                 return retval;
 278
 279         if (fpctrl & 1)
 280                 return ERROR_OK;
 281
 282         return ERROR_FAIL;
 283 }
 284
 285 static int cortex_m_endreset_event(struct target *target)
 286 {
 287         int i;
 288         int retval;
 289         uint32_t dcb_demcr;
 290         struct cortex_m_common *cortex_m = target_to_cm(target);
 291         struct armv7m_common *armv7m = &cortex_m->armv7m;
 292         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 293         struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
 294         struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
 295
 296         /* REVISIT The four debug monitor bits are currently ignored... */
 297         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
 298         if (retval != ERROR_OK)
 299                 return retval;
 300         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
 301
 302         /* this register is used for emulated dcc channel */
 303         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
 304         if (retval != ERROR_OK)
 305                 return retval;
 306
 307         /* Enable debug requests */
 308         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 309         if (retval != ERROR_OK)
 310                 return retval;
 311         if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
 312                 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
 313                 if (retval != ERROR_OK)
 314                         return retval;
 315         }
 316
 317         /* Restore proper interrupt masking setting for running CPU. */
 318         cortex_m_set_maskints_for_run(target);
 319
 320         /* Enable features controlled by ITM and DWT blocks, and catch only
 321          * the vectors we were told to pay attention to.
 322          *
 323          * Target firmware is responsible for all fault handling policy
 324          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 325          * or manual updates to the NVIC SHCSR and CCR registers.
 326          */
 327         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
 328         if (retval != ERROR_OK)
 329                 return retval;
 330
 331         /* Paranoia: evidently some (early?) chips don't preserve all the
 332          * debug state (including FPB, DWT, etc) across reset...
 333          */
 334
 335         /* Enable FPB */
 336         retval = cortex_m_enable_fpb(target);
 337         if (retval != ERROR_OK) {
 338                 LOG_ERROR("Failed to enable the FPB");
 339                 return retval;
 340         }
 341
 342         cortex_m->fpb_enabled = true;
 343
 344         /* Restore FPB registers */
 345         for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
 346                 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 347                 if (retval != ERROR_OK)
 348                         return retval;
 349         }
 350
 351         /* Restore DWT registers */
 352         for (i = 0; i < cortex_m->dwt_num_comp; i++) {
 353                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 354                                 dwt_list[i].comp);
 355                 if (retval != ERROR_OK)
 356                         return retval;
 357                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 358                                 dwt_list[i].mask);
 359                 if (retval != ERROR_OK)
 360                         return retval;
 361                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 362                                 dwt_list[i].function);
 363                 if (retval != ERROR_OK)
 364                         return retval;
 365         }
 366         retval = dap_run(swjdp);
 367         if (retval != ERROR_OK)
 368                 return retval;
 369
 370         register_cache_invalidate(armv7m->arm.core_cache);
 371
 372         /* make sure we have latest dhcsr flags */
 373         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 374
 375         return retval;
 376 }
 377
 378 static int cortex_m_examine_debug_reason(struct target *target)
 379 {
 380         struct cortex_m_common *cortex_m = target_to_cm(target);
 381
 382         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
 383          * only check the debug reason if we don't know it already */
 384
 385         if ((target->debug_reason != DBG_REASON_DBGRQ)
 386                 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
 387                 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
 388                         target->debug_reason = DBG_REASON_BREAKPOINT;
 389                         if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 390                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 391                 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 392                         target->debug_reason = DBG_REASON_WATCHPOINT;
 393                 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
 394                         target->debug_reason = DBG_REASON_BREAKPOINT;
 395                 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
 396                         target->debug_reason = DBG_REASON_DBGRQ;
 397                 else    /* HALTED */
 398                         target->debug_reason = DBG_REASON_UNDEFINED;
 399         }
 400
 401         return ERROR_OK;
 402 }
 403
 404 static int cortex_m_examine_exception_reason(struct target *target)
 405 {
 406         uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
 407         struct armv7m_common *armv7m = target_to_armv7m(target);
 408         struct adiv5_dap *swjdp = armv7m->arm.dap;
 409         int retval;
 410
 411         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
 412         if (retval != ERROR_OK)
 413                 return retval;
 414         switch (armv7m->exception_number) {
 415                 case 2: /* NMI */
 416                         break;
 417                 case 3: /* Hard Fault */
 418                         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
 419                         if (retval != ERROR_OK)
 420                                 return retval;
 421                         if (except_sr & 0x40000000) {
 422                                 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
 423                                 if (retval != ERROR_OK)
 424                                         return retval;
 425                         }
 426                         break;
 427                 case 4: /* Memory Management */
 428                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 429                         if (retval != ERROR_OK)
 430                                 return retval;
 431                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
 432                         if (retval != ERROR_OK)
 433                                 return retval;
 434                         break;
 435                 case 5: /* Bus Fault */
 436                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 437                         if (retval != ERROR_OK)
 438                                 return retval;
 439                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
 440                         if (retval != ERROR_OK)
 441                                 return retval;
 442                         break;
 443                 case 6: /* Usage Fault */
 444                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 445                         if (retval != ERROR_OK)
 446                                 return retval;
 447                         break;
 448                 case 7: /* Secure Fault */
 449                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
 450                         if (retval != ERROR_OK)
 451                                 return retval;
 452                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
 453                         if (retval != ERROR_OK)
 454                                 return retval;
 455                         break;
 456                 case 11:        /* SVCall */
 457                         break;
 458                 case 12:        /* Debug Monitor */
 459                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
 460                         if (retval != ERROR_OK)
 461                                 return retval;
 462                         break;
 463                 case 14:        /* PendSV */
 464                         break;
 465                 case 15:        /* SysTick */
 466                         break;
 467                 default:
 468                         except_sr = 0;
 469                         break;
 470         }
 471         retval = dap_run(swjdp);
 472         if (retval == ERROR_OK)
 473                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 474                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 475                         armv7m_exception_string(armv7m->exception_number),
 476                         shcsr, except_sr, cfsr, except_ar);
 477         return retval;
 478 }
 479
 480 static int cortex_m_debug_entry(struct target *target)
 481 {
 482         int i;
 483         uint32_t xPSR;
 484         int retval;
 485         struct cortex_m_common *cortex_m = target_to_cm(target);
 486         struct armv7m_common *armv7m = &cortex_m->armv7m;
 487         struct arm *arm = &armv7m->arm;
 488         struct reg *r;
 489
 490         LOG_DEBUG(" ");
 491
 492         /* Do this really early to minimize the window where the MASKINTS erratum
 493          * can pile up pending interrupts. */
 494         cortex_m_set_maskints_for_halt(target);
 495
 496         cortex_m_clear_halt(target);
 497         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 498         if (retval != ERROR_OK)
 499                 return retval;
 500
 501         retval = armv7m->examine_debug_reason(target);
 502         if (retval != ERROR_OK)
 503                 return retval;
 504
 505         /* examine PE security state */
 506         bool secure_state = false;
 507         if (armv7m->arm.is_armv8m) {
 508                 uint32_t dscsr;
 509
 510                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
 511                 if (retval != ERROR_OK)
 512                         return retval;
 513
 514                 secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
 515         }
 516
 517         /* Examine target state and mode
 518          * First load register accessible through core debug port */
 519         int num_regs = arm->core_cache->num_regs;
 520
 521         for (i = 0; i < num_regs; i++) {
 522                 r = &armv7m->arm.core_cache->reg_list[i];
 523                 if (!r->valid)
 524                         arm->read_core_reg(target, r, i, ARM_MODE_ANY);
 525         }
 526
 527         r = arm->cpsr;
 528         xPSR = buf_get_u32(r->value, 0, 32);
 529
 530         /* Are we in an exception handler */
 531         if (xPSR & 0x1FF) {
 532                 armv7m->exception_number = (xPSR & 0x1FF);
 533
 534                 arm->core_mode = ARM_MODE_HANDLER;
 535                 arm->map = armv7m_msp_reg_map;
 536         } else {
 537                 unsigned control = buf_get_u32(arm->core_cache
 538                                 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
 539
 540                 /* is this thread privileged? */
 541                 arm->core_mode = control & 1
 542                         ? ARM_MODE_USER_THREAD
 543                         : ARM_MODE_THREAD;
 544
 545                 /* which stack is it using? */
 546                 if (control & 2)
 547                         arm->map = armv7m_psp_reg_map;
 548                 else
 549                         arm->map = armv7m_msp_reg_map;
 550
 551                 armv7m->exception_number = 0;
 552         }
 553
 554         if (armv7m->exception_number)
 555                 cortex_m_examine_exception_reason(target);
 556
 557         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
 558                 arm_mode_name(arm->core_mode),
 559                 buf_get_u32(arm->pc->value, 0, 32),
 560                 secure_state ? "Secure" : "Non-Secure",
 561                 target_state_name(target));
 562
 563         if (armv7m->post_debug_entry) {
 564                 retval = armv7m->post_debug_entry(target);
 565                 if (retval != ERROR_OK)
 566                         return retval;
 567         }
 568
 569         return ERROR_OK;
 570 }
 571
 572 static int cortex_m_poll(struct target *target)
 573 {
 574         int detected_failure = ERROR_OK;
 575         int retval = ERROR_OK;
 576         enum target_state prev_target_state = target->state;
 577         struct cortex_m_common *cortex_m = target_to_cm(target);
 578         struct armv7m_common *armv7m = &cortex_m->armv7m;
 579
 580         /* Read from Debug Halting Control and Status Register */
 581         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 582         if (retval != ERROR_OK) {
 583                 target->state = TARGET_UNKNOWN;
 584                 return retval;
 585         }
 586
 587         /* Recover from lockup.  See ARMv7-M architecture spec,
 588          * section B1.5.15 "Unrecoverable exception cases".
 589          */
 590         if (cortex_m->dcb_dhcsr & S_LOCKUP) {
 591                 LOG_ERROR("%s -- clearing lockup after double fault",
 592                         target_name(target));
 593                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 594                 target->debug_reason = DBG_REASON_DBGRQ;
 595
 596                 /* We have to execute the rest (the "finally" equivalent, but
 597                  * still throw this exception again).
 598                  */
 599                 detected_failure = ERROR_FAIL;
 600
 601                 /* refresh status bits */
 602                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 603                 if (retval != ERROR_OK)
 604                         return retval;
 605         }
 606
 607         if (cortex_m->dcb_dhcsr & S_RESET_ST) {
 608                 if (target->state != TARGET_RESET) {
 609                         target->state = TARGET_RESET;
 610                         LOG_INFO("%s: external reset detected", target_name(target));
 611                 }
 612                 return ERROR_OK;
 613         }
 614
 615         if (target->state == TARGET_RESET) {
 616                 /* Cannot switch context while running so endreset is
 617                  * called with target->state == TARGET_RESET
 618                  */
 619                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 620                         cortex_m->dcb_dhcsr);
 621                 retval = cortex_m_endreset_event(target);
 622                 if (retval != ERROR_OK) {
 623                         target->state = TARGET_UNKNOWN;
 624                         return retval;
 625                 }
 626                 target->state = TARGET_RUNNING;
 627                 prev_target_state = TARGET_RUNNING;
 628         }
 629
 630         if (cortex_m->dcb_dhcsr & S_HALT) {
 631                 target->state = TARGET_HALTED;
 632
 633                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
 634                         retval = cortex_m_debug_entry(target);
 635                         if (retval != ERROR_OK)
 636                                 return retval;
 637
 638                         if (arm_semihosting(target, &retval) != 0)
 639                                 return retval;
 640
 641                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 642                 }
 643                 if (prev_target_state == TARGET_DEBUG_RUNNING) {
 644                         LOG_DEBUG(" ");
 645                         retval = cortex_m_debug_entry(target);
 646                         if (retval != ERROR_OK)
 647                                 return retval;
 648
 649                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 650                 }
 651         }
 652
 653         if (target->state == TARGET_UNKNOWN) {
 654                 /* check if processor is retiring instructions or sleeping */
 655                 if (cortex_m->dcb_dhcsr & S_RETIRE_ST || cortex_m->dcb_dhcsr & S_SLEEP) {
 656                         target->state = TARGET_RUNNING;
 657                         retval = ERROR_OK;
 658                 }
 659         }
 660
 661         /* Check that target is truly halted, since the target could be resumed externally */
 662         if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
 663                 /* registers are now invalid */
 664                 register_cache_invalidate(armv7m->arm.core_cache);
 665
 666                 target->state = TARGET_RUNNING;
 667                 LOG_WARNING("%s: external resume detected", target_name(target));
 668                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 669                 retval = ERROR_OK;
 670         }
 671
 672         /* Did we detect a failure condition that we cleared? */
 673         if (detected_failure != ERROR_OK)
 674                 retval = detected_failure;
 675         return retval;
 676 }
 677
 678 static int cortex_m_halt(struct target *target)
 679 {
 680         LOG_DEBUG("target->state: %s",
 681                 target_state_name(target));
 682
 683         if (target->state == TARGET_HALTED) {
 684                 LOG_DEBUG("target was already halted");
 685                 return ERROR_OK;
 686         }
 687
 688         if (target->state == TARGET_UNKNOWN)
 689                 LOG_WARNING("target was in unknown state when halt was requested");
 690
 691         if (target->state == TARGET_RESET) {
 692                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 693                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 694                         return ERROR_TARGET_FAILURE;
 695                 } else {
 696                         /* we came here in a reset_halt or reset_init sequence
 697                          * debug entry was already prepared in cortex_m3_assert_reset()
 698                          */
 699                         target->debug_reason = DBG_REASON_DBGRQ;
 700
 701                         return ERROR_OK;
 702                 }
 703         }
 704
 705         /* Write to Debug Halting Control and Status Register */
 706         cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 707
 708         /* Do this really early to minimize the window where the MASKINTS erratum
 709          * can pile up pending interrupts. */
 710         cortex_m_set_maskints_for_halt(target);
 711
 712         target->debug_reason = DBG_REASON_DBGRQ;
 713
 714         return ERROR_OK;
 715 }
 716
 717 static int cortex_m_soft_reset_halt(struct target *target)
 718 {
 719         struct cortex_m_common *cortex_m = target_to_cm(target);
 720         struct armv7m_common *armv7m = &cortex_m->armv7m;
 721         uint32_t dcb_dhcsr = 0;
 722         int retval, timeout = 0;
 723
 724         /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
 725          * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
 726          * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
 727          * core, not the peripherals */
 728         LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
 729
 730         /* Set C_DEBUGEN */
 731         retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
 732         if (retval != ERROR_OK)
 733                 return retval;
 734
 735         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 736         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
 737                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 738         if (retval != ERROR_OK)
 739                 return retval;
 740
 741         /* Request a core-only reset */
 742         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
 743                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 744         if (retval != ERROR_OK)
 745                 return retval;
 746         target->state = TARGET_RESET;
 747
 748         /* registers are now invalid */
 749         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 750
 751         while (timeout < 100) {
 752                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
 753                 if (retval == ERROR_OK) {
 754                         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
 755                                         &cortex_m->nvic_dfsr);
 756                         if (retval != ERROR_OK)
 757                                 return retval;
 758                         if ((dcb_dhcsr & S_HALT)
 759                                 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
 760                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 761                                         "DFSR 0x%08x",
 762                                         (unsigned) dcb_dhcsr,
 763                                         (unsigned) cortex_m->nvic_dfsr);
 764                                 cortex_m_poll(target);
 765                                 /* FIXME restore user's vector catch config */
 766                                 return ERROR_OK;
 767                         } else
 768                                 LOG_DEBUG("waiting for system reset-halt, "
 769                                         "DHCSR 0x%08x, %d ms",
 770                                         (unsigned) dcb_dhcsr, timeout);
 771                 }
 772                 timeout++;
 773                 alive_sleep(1);
 774         }
 775
 776         return ERROR_OK;
 777 }
 778
 779 void cortex_m_enable_breakpoints(struct target *target)
 780 {
 781         struct breakpoint *breakpoint = target->breakpoints;
 782
 783         /* set any pending breakpoints */
 784         while (breakpoint) {
 785                 if (!breakpoint->set)
 786                         cortex_m_set_breakpoint(target, breakpoint);
 787                 breakpoint = breakpoint->next;
 788         }
 789 }
 790
 791 static int cortex_m_resume(struct target *target, int current,
 792         target_addr_t address, int handle_breakpoints, int debug_execution)
 793 {
 794         struct armv7m_common *armv7m = target_to_armv7m(target);
 795         struct breakpoint *breakpoint = NULL;
 796         uint32_t resume_pc;
 797         struct reg *r;
 798
 799         if (target->state != TARGET_HALTED) {
 800                 LOG_WARNING("target not halted");
 801                 return ERROR_TARGET_NOT_HALTED;
 802         }
 803
 804         if (!debug_execution) {
 805                 target_free_all_working_areas(target);
 806                 cortex_m_enable_breakpoints(target);
 807                 cortex_m_enable_watchpoints(target);
 808         }
 809
 810         if (debug_execution) {
 811                 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
 812
 813                 /* Disable interrupts */
 814                 /* We disable interrupts in the PRIMASK register instead of
 815                  * masking with C_MASKINTS.  This is probably the same issue
 816                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 817                  * in parallel with disabled interrupts can cause local faults
 818                  * to not be taken.
 819                  *
 820                  * REVISIT this clearly breaks non-debug execution, since the
 821                  * PRIMASK register state isn't saved/restored...  workaround
 822                  * by never resuming app code after debug execution.
 823                  */
 824                 buf_set_u32(r->value, 0, 1, 1);
 825                 r->dirty = true;
 826                 r->valid = true;
 827
 828                 /* Make sure we are in Thumb mode */
 829                 r = armv7m->arm.cpsr;
 830                 buf_set_u32(r->value, 24, 1, 1);
 831                 r->dirty = true;
 832                 r->valid = true;
 833         }
 834
 835         /* current = 1: continue on current pc, otherwise continue at <address> */
 836         r = armv7m->arm.pc;
 837         if (!current) {
 838                 buf_set_u32(r->value, 0, 32, address);
 839                 r->dirty = true;
 840                 r->valid = true;
 841         }
 842
 843         /* if we halted last time due to a bkpt instruction
 844          * then we have to manually step over it, otherwise
 845          * the core will break again */
 846
 847         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 848                 && !debug_execution)
 849                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 850
 851         resume_pc = buf_get_u32(r->value, 0, 32);
 852
 853         armv7m_restore_context(target);
 854
 855         /* the front-end may request us not to handle breakpoints */
 856         if (handle_breakpoints) {
 857                 /* Single step past breakpoint at current address */
 858                 breakpoint = breakpoint_find(target, resume_pc);
 859                 if (breakpoint) {
 860                         LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
 861                                 breakpoint->address,
 862                                 breakpoint->unique_id);
 863                         cortex_m_unset_breakpoint(target, breakpoint);
 864                         cortex_m_single_step_core(target);
 865                         cortex_m_set_breakpoint(target, breakpoint);
 866                 }
 867         }
 868
 869         /* Restart core */
 870         cortex_m_set_maskints_for_run(target);
 871         cortex_m_write_debug_halt_mask(target, 0, C_HALT);
 872
 873         target->debug_reason = DBG_REASON_NOTHALTED;
 874
 875         /* registers are now invalid */
 876         register_cache_invalidate(armv7m->arm.core_cache);
 877
 878         if (!debug_execution) {
 879                 target->state = TARGET_RUNNING;
 880                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 881                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 882         } else {
 883                 target->state = TARGET_DEBUG_RUNNING;
 884                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 885                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 886         }
 887
 888         return ERROR_OK;
 889 }
 890
 891 /* int irqstepcount = 0; */
 892 static int cortex_m_step(struct target *target, int current,
 893         target_addr_t address, int handle_breakpoints)
 894 {
 895         struct cortex_m_common *cortex_m = target_to_cm(target);
 896         struct armv7m_common *armv7m = &cortex_m->armv7m;
 897         struct breakpoint *breakpoint = NULL;
 898         struct reg *pc = armv7m->arm.pc;
 899         bool bkpt_inst_found = false;
 900         int retval;
 901         bool isr_timed_out = false;
 902
 903         if (target->state != TARGET_HALTED) {
 904                 LOG_WARNING("target not halted");
 905                 return ERROR_TARGET_NOT_HALTED;
 906         }
 907
 908         /* current = 1: continue on current pc, otherwise continue at <address> */
 909         if (!current)
 910                 buf_set_u32(pc->value, 0, 32, address);
 911
 912         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
 913
 914         /* the front-end may request us not to handle breakpoints */
 915         if (handle_breakpoints) {
 916                 breakpoint = breakpoint_find(target, pc_value);
 917                 if (breakpoint)
 918                         cortex_m_unset_breakpoint(target, breakpoint);
 919         }
 920
 921         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 922
 923         target->debug_reason = DBG_REASON_SINGLESTEP;
 924
 925         armv7m_restore_context(target);
 926
 927         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 928
 929         /* if no bkpt instruction is found at pc then we can perform
 930          * a normal step, otherwise we have to manually step over the bkpt
 931          * instruction - as such simulate a step */
 932         if (bkpt_inst_found == false) {
 933                 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
 934                         /* Automatic ISR masking mode off: Just step over the next
 935                          * instruction, with interrupts on or off as appropriate. */
 936                         cortex_m_set_maskints_for_step(target);
 937                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 938                 } else {
 939                         /* Process interrupts during stepping in a way they don't interfere
 940                          * debugging.
 941                          *
 942                          * Principle:
 943                          *
 944                          * Set a temporary break point at the current pc and let the core run
 945                          * with interrupts enabled. Pending interrupts get served and we run
 946                          * into the breakpoint again afterwards. Then we step over the next
 947                          * instruction with interrupts disabled.
 948                          *
 949                          * If the pending interrupts don't complete within time, we leave the
 950                          * core running. This may happen if the interrupts trigger faster
 951                          * than the core can process them or the handler doesn't return.
 952                          *
 953                          * If no more breakpoints are available we simply do a step with
 954                          * interrupts enabled.
 955                          *
 956                          */
 957
 958                         /* 2012-09-29 ph
 959                          *
 960                          * If a break point is already set on the lower half word then a break point on
 961                          * the upper half word will not break again when the core is restarted. So we
 962                          * just step over the instruction with interrupts disabled.
 963                          *
 964                          * The documentation has no information about this, it was found by observation
 965                          * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
 966                          * suffer from this problem.
 967                          *
 968                          * To add some confusion: pc_value has bit 0 always set, while the breakpoint
 969                          * address has it always cleared. The former is done to indicate thumb mode
 970                          * to gdb.
 971                          *
 972                          */
 973                         if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
 974                                 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
 975                                 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
 976                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 977                                 /* Re-enable interrupts if appropriate */
 978                                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 979                                 cortex_m_set_maskints_for_halt(target);
 980                         } else {
 981
 982                                 /* Set a temporary break point */
 983                                 if (breakpoint) {
 984                                         retval = cortex_m_set_breakpoint(target, breakpoint);
 985                                 } else {
 986                                         enum breakpoint_type type = BKPT_HARD;
 987                                         if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
 988                                                 /* FPB rev.1 cannot handle such addr, try BKPT instr */
 989                                                 type = BKPT_SOFT;
 990                                         }
 991                                         retval = breakpoint_add(target, pc_value, 2, type);
 992                                 }
 993
 994                                 bool tmp_bp_set = (retval == ERROR_OK);
 995
 996                                 /* No more breakpoints left, just do a step */
 997                                 if (!tmp_bp_set) {
 998                                         cortex_m_set_maskints_for_step(target);
 999                                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1000                                         /* Re-enable interrupts if appropriate */
1001                                         cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1002                                         cortex_m_set_maskints_for_halt(target);
1003                                 } else {
1004                                         /* Start the core */
1005                                         LOG_DEBUG("Starting core to serve pending interrupts");
1006                                         int64_t t_start = timeval_ms();
1007                                         cortex_m_set_maskints_for_run(target);
1008                                         cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
1009
1010                                         /* Wait for pending handlers to complete or timeout */
1011                                         do {
1012                                                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
1013                                                                 DCB_DHCSR,
1014                                                                 &cortex_m->dcb_dhcsr);
1015                                                 if (retval != ERROR_OK) {
1016                                                         target->state = TARGET_UNKNOWN;
1017                                                         return retval;
1018                                                 }
1019                                                 isr_timed_out = ((timeval_ms() - t_start) > 500);
1020                                         } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1021
1022                                         /* only remove breakpoint if we created it */
1023                                         if (breakpoint)
1024                                                 cortex_m_unset_breakpoint(target, breakpoint);
1025                                         else {
1026                                                 /* Remove the temporary breakpoint */
1027                                                 breakpoint_remove(target, pc_value);
1028                                         }
1029
1030                                         if (isr_timed_out) {
1031                                                 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1032                                                         "leaving target running");
1033                                         } else {
1034                                                 /* Step over next instruction with interrupts disabled */
1035                                                 cortex_m_set_maskints_for_step(target);
1036                                                 cortex_m_write_debug_halt_mask(target,
1037                                                         C_HALT | C_MASKINTS,
1038                                                         0);
1039                                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1040                                                 /* Re-enable interrupts if appropriate */
1041                                                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1042                                                 cortex_m_set_maskints_for_halt(target);
1043                                         }
1044                                 }
1045                         }
1046                 }
1047         }
1048
1049         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1050         if (retval != ERROR_OK)
1051                 return retval;
1052
1053         /* registers are now invalid */
1054         register_cache_invalidate(armv7m->arm.core_cache);
1055
1056         if (breakpoint)
1057                 cortex_m_set_breakpoint(target, breakpoint);
1058
1059         if (isr_timed_out) {
1060                 /* Leave the core running. The user has to stop execution manually. */
1061                 target->debug_reason = DBG_REASON_NOTHALTED;
1062                 target->state = TARGET_RUNNING;
1063                 return ERROR_OK;
1064         }
1065
1066         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1067                 " nvic_icsr = 0x%" PRIx32,
1068                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1069
1070         retval = cortex_m_debug_entry(target);
1071         if (retval != ERROR_OK)
1072                 return retval;
1073         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1074
1075         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1076                 " nvic_icsr = 0x%" PRIx32,
1077                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1078
1079         return ERROR_OK;
1080 }
1081
1082 static int cortex_m_assert_reset(struct target *target)
1083 {
1084         struct cortex_m_common *cortex_m = target_to_cm(target);
1085         struct armv7m_common *armv7m = &cortex_m->armv7m;
1086         enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1087
1088         LOG_DEBUG("target->state: %s",
1089                 target_state_name(target));
1090
1091         enum reset_types jtag_reset_config = jtag_get_reset_config();
1092
1093         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1094                 /* allow scripts to override the reset event */
1095
1096                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1097                 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1098                 target->state = TARGET_RESET;
1099
1100                 return ERROR_OK;
1101         }
1102
1103         /* some cores support connecting while srst is asserted
1104          * use that mode is it has been configured */
1105
1106         bool srst_asserted = false;
1107
1108         if (!target_was_examined(target)) {
1109                 if (jtag_reset_config & RESET_HAS_SRST) {
1110                         adapter_assert_reset();
1111                         if (target->reset_halt)
1112                                 LOG_ERROR("Target not examined, will not halt after reset!");
1113                         return ERROR_OK;
1114                 } else {
1115                         LOG_ERROR("Target not examined, reset NOT asserted!");
1116                         return ERROR_FAIL;
1117                 }
1118         }
1119
1120         if ((jtag_reset_config & RESET_HAS_SRST) &&
1121             (jtag_reset_config & RESET_SRST_NO_GATING)) {
1122                 adapter_assert_reset();
1123                 srst_asserted = true;
1124         }
1125
1126         /* Enable debug requests */
1127         int retval;
1128         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1129         /* Store important errors instead of failing and proceed to reset assert */
1130
1131         if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1132                 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1133
1134         /* If the processor is sleeping in a WFI or WFE instruction, the
1135          * C_HALT bit must be asserted to regain control */
1136         if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1137                 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1138
1139         mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1140         /* Ignore less important errors */
1141
1142         if (!target->reset_halt) {
1143                 /* Set/Clear C_MASKINTS in a separate operation */
1144                 cortex_m_set_maskints_for_run(target);
1145
1146                 /* clear any debug flags before resuming */
1147                 cortex_m_clear_halt(target);
1148
1149                 /* clear C_HALT in dhcsr reg */
1150                 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1151         } else {
1152                 /* Halt in debug on reset; endreset_event() restores DEMCR.
1153                  *
1154                  * REVISIT catching BUSERR presumably helps to defend against
1155                  * bad vector table entries.  Should this include MMERR or
1156                  * other flags too?
1157                  */
1158                 int retval2;
1159                 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1160                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1161                 if (retval != ERROR_OK || retval2 != ERROR_OK)
1162                         LOG_INFO("AP write error, reset will not halt");
1163         }
1164
1165         if (jtag_reset_config & RESET_HAS_SRST) {
1166                 /* default to asserting srst */
1167                 if (!srst_asserted)
1168                         adapter_assert_reset();
1169
1170                 /* srst is asserted, ignore AP access errors */
1171                 retval = ERROR_OK;
1172         } else {
1173                 /* Use a standard Cortex-M3 software reset mechanism.
1174                  * We default to using VECRESET as it is supported on all current cores
1175                  * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1176                  * This has the disadvantage of not resetting the peripherals, so a
1177                  * reset-init event handler is needed to perform any peripheral resets.
1178                  */
1179                 if (!cortex_m->vectreset_supported
1180                                 && reset_config == CORTEX_M_RESET_VECTRESET) {
1181                         reset_config = CORTEX_M_RESET_SYSRESETREQ;
1182                         LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1183                         LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1184                 }
1185
1186                 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1187                         ? "SYSRESETREQ" : "VECTRESET");
1188
1189                 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1190                         LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1191                                 "handler to reset any peripherals or configure hardware srst support.");
1192                 }
1193
1194                 int retval3;
1195                 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1196                                 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1197                                 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1198                 if (retval3 != ERROR_OK)
1199                         LOG_DEBUG("Ignoring AP write error right after reset");
1200
1201                 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1202                 if (retval3 != ERROR_OK)
1203                         LOG_ERROR("DP initialisation failed");
1204
1205                 else {
1206                         /* I do not know why this is necessary, but it
1207                          * fixes strange effects (step/resume cause NMI
1208                          * after reset) on LM3S6918 -- Michael Schwingen
1209                          */
1210                         uint32_t tmp;
1211                         mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1212                 }
1213         }
1214
1215         target->state = TARGET_RESET;
1216         jtag_sleep(50000);
1217
1218         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1219
1220         /* now return stored error code if any */
1221         if (retval != ERROR_OK)
1222                 return retval;
1223
1224         if (target->reset_halt) {
1225                 retval = target_halt(target);
1226                 if (retval != ERROR_OK)
1227                         return retval;
1228         }
1229
1230         return ERROR_OK;
1231 }
1232
1233 static int cortex_m_deassert_reset(struct target *target)
1234 {
1235         struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1236
1237         LOG_DEBUG("target->state: %s",
1238                 target_state_name(target));
1239
1240         /* deassert reset lines */
1241         adapter_deassert_reset();
1242
1243         enum reset_types jtag_reset_config = jtag_get_reset_config();
1244
1245         if ((jtag_reset_config & RESET_HAS_SRST) &&
1246             !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1247                 target_was_examined(target)) {
1248                 int retval = dap_dp_init(armv7m->debug_ap->dap);
1249                 if (retval != ERROR_OK) {
1250                         LOG_ERROR("DP initialisation failed");
1251                         return retval;
1252                 }
1253         }
1254
1255         return ERROR_OK;
1256 }
1257
1258 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1259 {
1260         int retval;
1261         int fp_num = 0;
1262         struct cortex_m_common *cortex_m = target_to_cm(target);
1263         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1264
1265         if (breakpoint->set) {
1266                 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1267                 return ERROR_OK;
1268         }
1269
1270         if (breakpoint->type == BKPT_HARD) {
1271                 uint32_t fpcr_value;
1272                 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1273                         fp_num++;
1274                 if (fp_num >= cortex_m->fp_num_code) {
1275                         LOG_ERROR("Can not find free FPB Comparator!");
1276                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1277                 }
1278                 breakpoint->set = fp_num + 1;
1279                 fpcr_value = breakpoint->address | 1;
1280                 if (cortex_m->fp_rev == 0) {
1281                         if (breakpoint->address > 0x1FFFFFFF) {
1282                                 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1283                                 return ERROR_FAIL;
1284                         }
1285                         uint32_t hilo;
1286                         hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1287                         fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1288                 } else if (cortex_m->fp_rev > 1) {
1289                         LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1290                         return ERROR_FAIL;
1291                 }
1292                 comparator_list[fp_num].used = true;
1293                 comparator_list[fp_num].fpcr_value = fpcr_value;
1294                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1295                         comparator_list[fp_num].fpcr_value);
1296                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1297                         fp_num,
1298                         comparator_list[fp_num].fpcr_value);
1299                 if (!cortex_m->fpb_enabled) {
1300                         LOG_DEBUG("FPB wasn't enabled, do it now");
1301                         retval = cortex_m_enable_fpb(target);
1302                         if (retval != ERROR_OK) {
1303                                 LOG_ERROR("Failed to enable the FPB");
1304                                 return retval;
1305                         }
1306
1307                         cortex_m->fpb_enabled = true;
1308                 }
1309         } else if (breakpoint->type == BKPT_SOFT) {
1310                 uint8_t code[4];
1311
1312                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1313                  * semihosting; don't use that.  Otherwise the BKPT
1314                  * parameter is arbitrary.
1315                  */
1316                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1317                 retval = target_read_memory(target,
1318                                 breakpoint->address & 0xFFFFFFFE,
1319                                 breakpoint->length, 1,
1320                                 breakpoint->orig_instr);
1321                 if (retval != ERROR_OK)
1322                         return retval;
1323                 retval = target_write_memory(target,
1324                                 breakpoint->address & 0xFFFFFFFE,
1325                                 breakpoint->length, 1,
1326                                 code);
1327                 if (retval != ERROR_OK)
1328                         return retval;
1329                 breakpoint->set = true;
1330         }
1331
1332         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1333                 breakpoint->unique_id,
1334                 (int)(breakpoint->type),
1335                 breakpoint->address,
1336                 breakpoint->length,
1337                 breakpoint->set);
1338
1339         return ERROR_OK;
1340 }
1341
1342 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1343 {
1344         int retval;
1345         struct cortex_m_common *cortex_m = target_to_cm(target);
1346         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1347
1348         if (!breakpoint->set) {
1349                 LOG_WARNING("breakpoint not set");
1350                 return ERROR_OK;
1351         }
1352
1353         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1354                 breakpoint->unique_id,
1355                 (int)(breakpoint->type),
1356                 breakpoint->address,
1357                 breakpoint->length,
1358                 breakpoint->set);
1359
1360         if (breakpoint->type == BKPT_HARD) {
1361                 int fp_num = breakpoint->set - 1;
1362                 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1363                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1364                         return ERROR_OK;
1365                 }
1366                 comparator_list[fp_num].used = false;
1367                 comparator_list[fp_num].fpcr_value = 0;
1368                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1369                         comparator_list[fp_num].fpcr_value);
1370         } else {
1371                 /* restore original instruction (kept in target endianness) */
1372                 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1373                                         breakpoint->length, 1,
1374                                         breakpoint->orig_instr);
1375                 if (retval != ERROR_OK)
1376                         return retval;
1377         }
1378         breakpoint->set = false;
1379
1380         return ERROR_OK;
1381 }
1382
1383 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1384 {
1385         if (breakpoint->length == 3) {
1386                 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1387                 breakpoint->length = 2;
1388         }
1389
1390         if ((breakpoint->length != 2)) {
1391                 LOG_INFO("only breakpoints of two bytes length supported");
1392                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1393         }
1394
1395         return cortex_m_set_breakpoint(target, breakpoint);
1396 }
1397
1398 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1399 {
1400         if (!breakpoint->set)
1401                 return ERROR_OK;
1402
1403         return cortex_m_unset_breakpoint(target, breakpoint);
1404 }
1405
1406 static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1407 {
1408         int dwt_num = 0;
1409         struct cortex_m_common *cortex_m = target_to_cm(target);
1410
1411         /* REVISIT Don't fully trust these "not used" records ... users
1412          * may set up breakpoints by hand, e.g. dual-address data value
1413          * watchpoint using comparator #1; comparator #0 matching cycle
1414          * count; send data trace info through ITM and TPIU; etc
1415          */
1416         struct cortex_m_dwt_comparator *comparator;
1417
1418         for (comparator = cortex_m->dwt_comparator_list;
1419                 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1420                 comparator++, dwt_num++)
1421                 continue;
1422         if (dwt_num >= cortex_m->dwt_num_comp) {
1423                 LOG_ERROR("Can not find free DWT Comparator");
1424                 return ERROR_FAIL;
1425         }
1426         comparator->used = true;
1427         watchpoint->set = dwt_num + 1;
1428
1429         comparator->comp = watchpoint->address;
1430         target_write_u32(target, comparator->dwt_comparator_address + 0,
1431                 comparator->comp);
1432
1433         if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1434                 uint32_t mask = 0, temp;
1435
1436                 /* watchpoint params were validated earlier */
1437                 temp = watchpoint->length;
1438                 while (temp) {
1439                         temp >>= 1;
1440                         mask++;
1441                 }
1442                 mask--;
1443
1444                 comparator->mask = mask;
1445                 target_write_u32(target, comparator->dwt_comparator_address + 4,
1446                         comparator->mask);
1447
1448                 switch (watchpoint->rw) {
1449                 case WPT_READ:
1450                         comparator->function = 5;
1451                         break;
1452                 case WPT_WRITE:
1453                         comparator->function = 6;
1454                         break;
1455                 case WPT_ACCESS:
1456                         comparator->function = 7;
1457                         break;
1458                 }
1459         } else {
1460                 uint32_t data_size = watchpoint->length >> 1;
1461                 comparator->mask = (watchpoint->length >> 1) | 1;
1462
1463                 switch (watchpoint->rw) {
1464                 case WPT_ACCESS:
1465                         comparator->function = 4;
1466                         break;
1467                 case WPT_WRITE:
1468                         comparator->function = 5;
1469                         break;
1470                 case WPT_READ:
1471                         comparator->function = 6;
1472                         break;
1473                 }
1474                 comparator->function = comparator->function | (1 << 4) |
1475                                 (data_size << 10);
1476         }
1477
1478         target_write_u32(target, comparator->dwt_comparator_address + 8,
1479                 comparator->function);
1480
1481         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1482                 watchpoint->unique_id, dwt_num,
1483                 (unsigned) comparator->comp,
1484                 (unsigned) comparator->mask,
1485                 (unsigned) comparator->function);
1486         return ERROR_OK;
1487 }
1488
1489 static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1490 {
1491         struct cortex_m_common *cortex_m = target_to_cm(target);
1492         struct cortex_m_dwt_comparator *comparator;
1493         int dwt_num;
1494
1495         if (!watchpoint->set) {
1496                 LOG_WARNING("watchpoint (wpid: %d) not set",
1497                         watchpoint->unique_id);
1498                 return ERROR_OK;
1499         }
1500
1501         dwt_num = watchpoint->set - 1;
1502
1503         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1504                 watchpoint->unique_id, dwt_num,
1505                 (unsigned) watchpoint->address);
1506
1507         if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1508                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1509                 return ERROR_OK;
1510         }
1511
1512         comparator = cortex_m->dwt_comparator_list + dwt_num;
1513         comparator->used = false;
1514         comparator->function = 0;
1515         target_write_u32(target, comparator->dwt_comparator_address + 8,
1516                 comparator->function);
1517
1518         watchpoint->set = false;
1519
1520         return ERROR_OK;
1521 }
1522
1523 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1524 {
1525         struct cortex_m_common *cortex_m = target_to_cm(target);
1526
1527         if (cortex_m->dwt_comp_available < 1) {
1528                 LOG_DEBUG("no comparators?");
1529                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1530         }
1531
1532         /* hardware doesn't support data value masking */
1533         if (watchpoint->mask != ~(uint32_t)0) {
1534                 LOG_DEBUG("watchpoint value masks not supported");
1535                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1536         }
1537
1538         /* hardware allows address masks of up to 32K */
1539         unsigned mask;
1540
1541         for (mask = 0; mask < 16; mask++) {
1542                 if ((1u << mask) == watchpoint->length)
1543                         break;
1544         }
1545         if (mask == 16) {
1546                 LOG_DEBUG("unsupported watchpoint length");
1547                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1548         }
1549         if (watchpoint->address & ((1 << mask) - 1)) {
1550                 LOG_DEBUG("watchpoint address is unaligned");
1551                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1552         }
1553
1554         /* Caller doesn't seem to be able to describe watching for data
1555          * values of zero; that flags "no value".
1556          *
1557          * REVISIT This DWT may well be able to watch for specific data
1558          * values.  Requires comparator #1 to set DATAVMATCH and match
1559          * the data, and another comparator (DATAVADDR0) matching addr.
1560          */
1561         if (watchpoint->value) {
1562                 LOG_DEBUG("data value watchpoint not YET supported");
1563                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1564         }
1565
1566         cortex_m->dwt_comp_available--;
1567         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1568
1569         return ERROR_OK;
1570 }
1571
1572 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1573 {
1574         struct cortex_m_common *cortex_m = target_to_cm(target);
1575
1576         /* REVISIT why check? DWT can be updated with core running ... */
1577         if (target->state != TARGET_HALTED) {
1578                 LOG_WARNING("target not halted");
1579                 return ERROR_TARGET_NOT_HALTED;
1580         }
1581
1582         if (watchpoint->set)
1583                 cortex_m_unset_watchpoint(target, watchpoint);
1584
1585         cortex_m->dwt_comp_available++;
1586         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1587
1588         return ERROR_OK;
1589 }
1590
1591 void cortex_m_enable_watchpoints(struct target *target)
1592 {
1593         struct watchpoint *watchpoint = target->watchpoints;
1594
1595         /* set any pending watchpoints */
1596         while (watchpoint) {
1597                 if (!watchpoint->set)
1598                         cortex_m_set_watchpoint(target, watchpoint);
1599                 watchpoint = watchpoint->next;
1600         }
1601 }
1602
1603 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1604         uint32_t size, uint32_t count, uint8_t *buffer)
1605 {
1606         struct armv7m_common *armv7m = target_to_armv7m(target);
1607
1608         if (armv7m->arm.is_armv6m) {
1609                 /* armv6m does not handle unaligned memory access */
1610                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1611                         return ERROR_TARGET_UNALIGNED_ACCESS;
1612         }
1613
1614         return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1615 }
1616
1617 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1618         uint32_t size, uint32_t count, const uint8_t *buffer)
1619 {
1620         struct armv7m_common *armv7m = target_to_armv7m(target);
1621
1622         if (armv7m->arm.is_armv6m) {
1623                 /* armv6m does not handle unaligned memory access */
1624                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1625                         return ERROR_TARGET_UNALIGNED_ACCESS;
1626         }
1627
1628         return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1629 }
1630
1631 static int cortex_m_init_target(struct command_context *cmd_ctx,
1632         struct target *target)
1633 {
1634         armv7m_build_reg_cache(target);
1635         arm_semihosting_init(target);
1636         return ERROR_OK;
1637 }
1638
1639 void cortex_m_deinit_target(struct target *target)
1640 {
1641         struct cortex_m_common *cortex_m = target_to_cm(target);
1642
1643         free(cortex_m->fp_comparator_list);
1644
1645         cortex_m_dwt_free(target);
1646         armv7m_free_reg_cache(target);
1647
1648         free(target->private_config);
1649         free(cortex_m);
1650 }
1651
1652 int cortex_m_profiling(struct target *target, uint32_t *samples,
1653                               uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1654 {
1655         struct timeval timeout, now;
1656         struct armv7m_common *armv7m = target_to_armv7m(target);
1657         uint32_t reg_value;
1658         int retval;
1659
1660         retval = target_read_u32(target, DWT_PCSR, &reg_value);
1661         if (retval != ERROR_OK) {
1662                 LOG_ERROR("Error while reading PCSR");
1663                 return retval;
1664         }
1665         if (reg_value == 0) {
1666                 LOG_INFO("PCSR sampling not supported on this processor.");
1667                 return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
1668         }
1669
1670         gettimeofday(&timeout, NULL);
1671         timeval_add_time(&timeout, seconds, 0);
1672
1673         LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1674
1675         /* Make sure the target is running */
1676         target_poll(target);
1677         if (target->state == TARGET_HALTED)
1678                 retval = target_resume(target, 1, 0, 0, 0);
1679
1680         if (retval != ERROR_OK) {
1681                 LOG_ERROR("Error while resuming target");
1682                 return retval;
1683         }
1684
1685         uint32_t sample_count = 0;
1686
1687         for (;;) {
1688                 if (armv7m && armv7m->debug_ap) {
1689                         uint32_t read_count = max_num_samples - sample_count;
1690                         if (read_count > 1024)
1691                                 read_count = 1024;
1692
1693                         retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1694                                                 (void *)&samples[sample_count],
1695                                                 4, read_count, DWT_PCSR);
1696                         sample_count += read_count;
1697                 } else {
1698                         target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1699                 }
1700
1701                 if (retval != ERROR_OK) {
1702                         LOG_ERROR("Error while reading PCSR");
1703                         return retval;
1704                 }
1705
1706
1707                 gettimeofday(&now, NULL);
1708                 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1709                         LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1710                         break;
1711                 }
1712         }
1713
1714         *num_samples = sample_count;
1715         return retval;
1716 }
1717
1718
1719 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1720  * on r/w if the core is not running, and clear on resume or reset ... or
1721  * at least, in a post_restore_context() method.
1722  */
1723
1724 struct dwt_reg_state {
1725         struct target *target;
1726         uint32_t addr;
1727         uint8_t value[4];               /* scratch/cache */
1728 };
1729
1730 static int cortex_m_dwt_get_reg(struct reg *reg)
1731 {
1732         struct dwt_reg_state *state = reg->arch_info;
1733
1734         uint32_t tmp;
1735         int retval = target_read_u32(state->target, state->addr, &tmp);
1736         if (retval != ERROR_OK)
1737                 return retval;
1738
1739         buf_set_u32(state->value, 0, 32, tmp);
1740         return ERROR_OK;
1741 }
1742
1743 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1744 {
1745         struct dwt_reg_state *state = reg->arch_info;
1746
1747         return target_write_u32(state->target, state->addr,
1748                         buf_get_u32(buf, 0, reg->size));
1749 }
1750
1751 struct dwt_reg {
1752         uint32_t addr;
1753         const char *name;
1754         unsigned size;
1755 };
1756
1757 static const struct dwt_reg dwt_base_regs[] = {
1758         { DWT_CTRL, "dwt_ctrl", 32, },
1759         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1760          * increments while the core is asleep.
1761          */
1762         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1763         /* plus some 8 bit counters, useful for profiling with TPIU */
1764 };
1765
1766 static const struct dwt_reg dwt_comp[] = {
1767 #define DWT_COMPARATOR(i) \
1768                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1769                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1770                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1771         DWT_COMPARATOR(0),
1772         DWT_COMPARATOR(1),
1773         DWT_COMPARATOR(2),
1774         DWT_COMPARATOR(3),
1775         DWT_COMPARATOR(4),
1776         DWT_COMPARATOR(5),
1777         DWT_COMPARATOR(6),
1778         DWT_COMPARATOR(7),
1779         DWT_COMPARATOR(8),
1780         DWT_COMPARATOR(9),
1781         DWT_COMPARATOR(10),
1782         DWT_COMPARATOR(11),
1783         DWT_COMPARATOR(12),
1784         DWT_COMPARATOR(13),
1785         DWT_COMPARATOR(14),
1786         DWT_COMPARATOR(15),
1787 #undef DWT_COMPARATOR
1788 };
1789
1790 static const struct reg_arch_type dwt_reg_type = {
1791         .get = cortex_m_dwt_get_reg,
1792         .set = cortex_m_dwt_set_reg,
1793 };
1794
1795 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1796 {
1797         struct dwt_reg_state *state;
1798
1799         state = calloc(1, sizeof(*state));
1800         if (!state)
1801                 return;
1802         state->addr = d->addr;
1803         state->target = t;
1804
1805         r->name = d->name;
1806         r->size = d->size;
1807         r->value = state->value;
1808         r->arch_info = state;
1809         r->type = &dwt_reg_type;
1810 }
1811
1812 static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1813 {
1814         uint32_t dwtcr;
1815         struct reg_cache *cache;
1816         struct cortex_m_dwt_comparator *comparator;
1817         int reg, i;
1818
1819         target_read_u32(target, DWT_CTRL, &dwtcr);
1820         LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1821         if (!dwtcr) {
1822                 LOG_DEBUG("no DWT");
1823                 return;
1824         }
1825
1826         target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
1827         LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
1828
1829         cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1830         cm->dwt_comp_available = cm->dwt_num_comp;
1831         cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1832                         sizeof(struct cortex_m_dwt_comparator));
1833         if (!cm->dwt_comparator_list) {
1834 fail0:
1835                 cm->dwt_num_comp = 0;
1836                 LOG_ERROR("out of mem");
1837                 return;
1838         }
1839
1840         cache = calloc(1, sizeof(*cache));
1841         if (!cache) {
1842 fail1:
1843                 free(cm->dwt_comparator_list);
1844                 goto fail0;
1845         }
1846         cache->name = "Cortex-M DWT registers";
1847         cache->num_regs = 2 + cm->dwt_num_comp * 3;
1848         cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
1849         if (!cache->reg_list) {
1850                 free(cache);
1851                 goto fail1;
1852         }
1853
1854         for (reg = 0; reg < 2; reg++)
1855                 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1856                         dwt_base_regs + reg);
1857
1858         comparator = cm->dwt_comparator_list;
1859         for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1860                 int j;
1861
1862                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1863                 for (j = 0; j < 3; j++, reg++)
1864                         cortex_m_dwt_addreg(target, cache->reg_list + reg,
1865                                 dwt_comp + 3 * i + j);
1866
1867                 /* make sure we clear any watchpoints enabled on the target */
1868                 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1869         }
1870
1871         *register_get_last_cache_p(&target->reg_cache) = cache;
1872         cm->dwt_cache = cache;
1873
1874         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1875                 dwtcr, cm->dwt_num_comp,
1876                 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1877
1878         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1879          * implement single-address data value watchpoints ... so we
1880          * won't need to check it later, when asked to set one up.
1881          */
1882 }
1883
1884 static void cortex_m_dwt_free(struct target *target)
1885 {
1886         struct cortex_m_common *cm = target_to_cm(target);
1887         struct reg_cache *cache = cm->dwt_cache;
1888
1889         free(cm->dwt_comparator_list);
1890         cm->dwt_comparator_list = NULL;
1891         cm->dwt_num_comp = 0;
1892
1893         if (cache) {
1894                 register_unlink_cache(&target->reg_cache, cache);
1895
1896                 if (cache->reg_list) {
1897                         for (size_t i = 0; i < cache->num_regs; i++)
1898                                 free(cache->reg_list[i].arch_info);
1899                         free(cache->reg_list);
1900                 }
1901                 free(cache);
1902         }
1903         cm->dwt_cache = NULL;
1904 }
1905
1906 #define MVFR0 0xe000ef40
1907 #define MVFR1 0xe000ef44
1908
1909 #define MVFR0_DEFAULT_M4 0x10110021
1910 #define MVFR1_DEFAULT_M4 0x11000011
1911
1912 #define MVFR0_DEFAULT_M7_SP 0x10110021
1913 #define MVFR0_DEFAULT_M7_DP 0x10110221
1914 #define MVFR1_DEFAULT_M7_SP 0x11000011
1915 #define MVFR1_DEFAULT_M7_DP 0x12000011
1916
1917 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
1918                 struct adiv5_ap **debug_ap)
1919 {
1920         if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
1921                 return ERROR_OK;
1922
1923         return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
1924 }
1925
1926 int cortex_m_examine(struct target *target)
1927 {
1928         int retval;
1929         uint32_t cpuid, fpcr, mvfr0, mvfr1;
1930         int i;
1931         struct cortex_m_common *cortex_m = target_to_cm(target);
1932         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1933         struct armv7m_common *armv7m = target_to_armv7m(target);
1934
1935         /* stlink shares the examine handler but does not support
1936          * all its calls */
1937         if (!armv7m->stlink) {
1938                 if (cortex_m->apsel == DP_APSEL_INVALID) {
1939                         /* Search for the MEM-AP */
1940                         retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
1941                         if (retval != ERROR_OK) {
1942                                 LOG_ERROR("Could not find MEM-AP to control the core");
1943                                 return retval;
1944                         }
1945                 } else {
1946                         armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
1947                 }
1948
1949                 /* Leave (only) generic DAP stuff for debugport_init(); */
1950                 armv7m->debug_ap->memaccess_tck = 8;
1951
1952                 retval = mem_ap_init(armv7m->debug_ap);
1953                 if (retval != ERROR_OK)
1954                         return retval;
1955         }
1956
1957         if (!target_was_examined(target)) {
1958                 target_set_examined(target);
1959
1960                 /* Read from Device Identification Registers */
1961                 retval = target_read_u32(target, CPUID, &cpuid);
1962                 if (retval != ERROR_OK)
1963                         return retval;
1964
1965                 /* Get CPU Type */
1966                 i = (cpuid >> 4) & 0xf;
1967
1968                 /* Check if it is an ARMv8-M core */
1969                 armv7m->arm.is_armv8m = true;
1970
1971                 switch (cpuid & ARM_CPUID_PARTNO_MASK) {
1972                         case CORTEX_M23_PARTNO:
1973                                 i = 23;
1974                                 break;
1975                         case CORTEX_M33_PARTNO:
1976                                 i = 33;
1977                                 break;
1978                         case CORTEX_M35P_PARTNO:
1979                                 i = 35;
1980                                 break;
1981                         case CORTEX_M55_PARTNO:
1982                                 i = 55;
1983                                 break;
1984                         default:
1985                                 armv7m->arm.is_armv8m = false;
1986                                 break;
1987                 }
1988
1989
1990                 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
1991                                 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1992                 cortex_m->maskints_erratum = false;
1993                 if (i == 7) {
1994                         uint8_t rev, patch;
1995                         rev = (cpuid >> 20) & 0xf;
1996                         patch = (cpuid >> 0) & 0xf;
1997                         if ((rev == 0) && (patch < 2)) {
1998                                 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
1999                                 cortex_m->maskints_erratum = true;
2000                         }
2001                 }
2002                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2003
2004                 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2005                 cortex_m->vectreset_supported = i > 1;
2006
2007                 if (i == 4) {
2008                         target_read_u32(target, MVFR0, &mvfr0);
2009                         target_read_u32(target, MVFR1, &mvfr1);
2010
2011                         /* test for floating point feature on Cortex-M4 */
2012                         if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2013                                 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2014                                 armv7m->fp_feature = FPv4_SP;
2015                         }
2016                 } else if (i == 7 || i == 33 || i == 35 || i == 55) {
2017                         target_read_u32(target, MVFR0, &mvfr0);
2018                         target_read_u32(target, MVFR1, &mvfr1);
2019
2020                         /* test for floating point features on Cortex-M7 */
2021                         if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2022                                 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2023                                 armv7m->fp_feature = FPv5_SP;
2024                         } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2025                                 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2026                                 armv7m->fp_feature = FPv5_DP;
2027                         }
2028                 } else if (i == 0) {
2029                         /* Cortex-M0 does not support unaligned memory access */
2030                         armv7m->arm.is_armv6m = true;
2031                 }
2032
2033                 if (armv7m->fp_feature == FP_NONE &&
2034                     armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2035                         /* free unavailable FPU registers */
2036                         size_t idx;
2037
2038                         for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2039                              idx < armv7m->arm.core_cache->num_regs;
2040                              idx++) {
2041                                 free(armv7m->arm.core_cache->reg_list[idx].feature);
2042                                 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2043                         }
2044                         armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2045                 }
2046
2047                 if (!armv7m->stlink) {
2048                         if (i == 3 || i == 4)
2049                                 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2050                                  * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2051                                 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2052                         else if (i == 7)
2053                                 /* Cortex-M7 has only 1024 bytes autoincrement range */
2054                                 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2055                 }
2056
2057                 /* Enable debug requests */
2058                 retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
2059                 if (retval != ERROR_OK)
2060                         return retval;
2061                 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
2062                         uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
2063
2064                         retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
2065                         if (retval != ERROR_OK)
2066                                 return retval;
2067                         cortex_m->dcb_dhcsr = dhcsr;
2068                 }
2069
2070                 /* Configure trace modules */
2071                 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2072                 if (retval != ERROR_OK)
2073                         return retval;
2074
2075                 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2076                         armv7m_trace_tpiu_config(target);
2077                         armv7m_trace_itm_config(target);
2078                 }
2079
2080                 /* NOTE: FPB and DWT are both optional. */
2081
2082                 /* Setup FPB */
2083                 target_read_u32(target, FP_CTRL, &fpcr);
2084                 /* bits [14:12] and [7:4] */
2085                 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2086                 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2087                 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2088                    Revision is zero base, fp_rev == 1 means Rev.2 ! */
2089                 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2090                 free(cortex_m->fp_comparator_list);
2091                 cortex_m->fp_comparator_list = calloc(
2092                                 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2093                                 sizeof(struct cortex_m_fp_comparator));
2094                 cortex_m->fpb_enabled = fpcr & 1;
2095                 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2096                         cortex_m->fp_comparator_list[i].type =
2097                                 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2098                         cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2099
2100                         /* make sure we clear any breakpoints enabled on the target */
2101                         target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2102                 }
2103                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2104                         fpcr,
2105                         cortex_m->fp_num_code,
2106                         cortex_m->fp_num_lit);
2107
2108                 /* Setup DWT */
2109                 cortex_m_dwt_free(target);
2110                 cortex_m_dwt_setup(cortex_m, target);
2111
2112                 /* These hardware breakpoints only work for code in flash! */
2113                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2114                         target_name(target),
2115                         cortex_m->fp_num_code,
2116                         cortex_m->dwt_num_comp);
2117         }
2118
2119         return ERROR_OK;
2120 }
2121
2122 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2123 {
2124         struct armv7m_common *armv7m = target_to_armv7m(target);
2125         uint16_t dcrdr;
2126         uint8_t buf[2];
2127         int retval;
2128
2129         retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2130         if (retval != ERROR_OK)
2131                 return retval;
2132
2133         dcrdr = target_buffer_get_u16(target, buf);
2134         *ctrl = (uint8_t)dcrdr;
2135         *value = (uint8_t)(dcrdr >> 8);
2136
2137         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2138
2139         /* write ack back to software dcc register
2140          * signify we have read data */
2141         if (dcrdr & (1 << 0)) {
2142                 target_buffer_set_u16(target, buf, 0);
2143                 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2144                 if (retval != ERROR_OK)
2145                         return retval;
2146         }
2147
2148         return ERROR_OK;
2149 }
2150
2151 static int cortex_m_target_request_data(struct target *target,
2152         uint32_t size, uint8_t *buffer)
2153 {
2154         uint8_t data;
2155         uint8_t ctrl;
2156         uint32_t i;
2157
2158         for (i = 0; i < (size * 4); i++) {
2159                 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2160                 if (retval != ERROR_OK)
2161                         return retval;
2162                 buffer[i] = data;
2163         }
2164
2165         return ERROR_OK;
2166 }
2167
2168 static int cortex_m_handle_target_request(void *priv)
2169 {
2170         struct target *target = priv;
2171         if (!target_was_examined(target))
2172                 return ERROR_OK;
2173
2174         if (!target->dbg_msg_enabled)
2175                 return ERROR_OK;
2176
2177         if (target->state == TARGET_RUNNING) {
2178                 uint8_t data;
2179                 uint8_t ctrl;
2180                 int retval;
2181
2182                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2183                 if (retval != ERROR_OK)
2184                         return retval;
2185
2186                 /* check if we have data */
2187                 if (ctrl & (1 << 0)) {
2188                         uint32_t request;
2189
2190                         /* we assume target is quick enough */
2191                         request = data;
2192                         for (int i = 1; i <= 3; i++) {
2193                                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2194                                 if (retval != ERROR_OK)
2195                                         return retval;
2196                                 request |= ((uint32_t)data << (i * 8));
2197                         }
2198                         target_request(target, request);
2199                 }
2200         }
2201
2202         return ERROR_OK;
2203 }
2204
2205 static int cortex_m_init_arch_info(struct target *target,
2206         struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2207 {
2208         struct armv7m_common *armv7m = &cortex_m->armv7m;
2209
2210         armv7m_init_arch_info(target, armv7m);
2211
2212         /* default reset mode is to use srst if fitted
2213          * if not it will use CORTEX_M3_RESET_VECTRESET */
2214         cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2215
2216         armv7m->arm.dap = dap;
2217
2218         /* register arch-specific functions */
2219         armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2220
2221         armv7m->post_debug_entry = NULL;
2222
2223         armv7m->pre_restore_context = NULL;
2224
2225         armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2226         armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2227
2228         target_register_timer_callback(cortex_m_handle_target_request, 1,
2229                 TARGET_TIMER_TYPE_PERIODIC, target);
2230
2231         return ERROR_OK;
2232 }
2233
2234 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2235 {
2236         struct adiv5_private_config *pc;
2237
2238         pc = (struct adiv5_private_config *)target->private_config;
2239         if (adiv5_verify_config(pc) != ERROR_OK)
2240                 return ERROR_FAIL;
2241
2242         struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2243         if (cortex_m == NULL) {
2244                 LOG_ERROR("No memory creating target");
2245                 return ERROR_FAIL;
2246         }
2247
2248         cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2249         cortex_m->apsel = pc->ap_num;
2250
2251         cortex_m_init_arch_info(target, cortex_m, pc->dap);
2252
2253         return ERROR_OK;
2254 }
2255
2256 /*--------------------------------------------------------------------------*/
2257
2258 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2259         struct cortex_m_common *cm)
2260 {
2261         if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2262                 command_print(cmd, "target is not a Cortex-M");
2263                 return ERROR_TARGET_INVALID;
2264         }
2265         return ERROR_OK;
2266 }
2267
2268 /*
2269  * Only stuff below this line should need to verify that its target
2270  * is a Cortex-M3.  Everything else should have indirected through the
2271  * cortexm3_target structure, which is only used with CM3 targets.
2272  */
2273
2274 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2275 {
2276         struct target *target = get_current_target(CMD_CTX);
2277         struct cortex_m_common *cortex_m = target_to_cm(target);
2278         struct armv7m_common *armv7m = &cortex_m->armv7m;
2279         uint32_t demcr = 0;
2280         int retval;
2281
2282         static const struct {
2283                 char name[10];
2284                 unsigned mask;
2285         } vec_ids[] = {
2286                 { "hard_err",   VC_HARDERR, },
2287                 { "int_err",    VC_INTERR, },
2288                 { "bus_err",    VC_BUSERR, },
2289                 { "state_err",  VC_STATERR, },
2290                 { "chk_err",    VC_CHKERR, },
2291                 { "nocp_err",   VC_NOCPERR, },
2292                 { "mm_err",     VC_MMERR, },
2293                 { "reset",      VC_CORERESET, },
2294         };
2295
2296         retval = cortex_m_verify_pointer(CMD, cortex_m);
2297         if (retval != ERROR_OK)
2298                 return retval;
2299
2300         if (!target_was_examined(target)) {
2301                 LOG_ERROR("Target not examined yet");
2302                 return ERROR_FAIL;
2303         }
2304
2305         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2306         if (retval != ERROR_OK)
2307                 return retval;
2308
2309         if (CMD_ARGC > 0) {
2310                 unsigned catch = 0;
2311
2312                 if (CMD_ARGC == 1) {
2313                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2314                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2315                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2316                                         | VC_MMERR | VC_CORERESET;
2317                                 goto write;
2318                         } else if (strcmp(CMD_ARGV[0], "none") == 0)
2319                                 goto write;
2320                 }
2321                 while (CMD_ARGC-- > 0) {
2322                         unsigned i;
2323                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2324                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2325                                         continue;
2326                                 catch |= vec_ids[i].mask;
2327                                 break;
2328                         }
2329                         if (i == ARRAY_SIZE(vec_ids)) {
2330                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2331                                 return ERROR_COMMAND_SYNTAX_ERROR;
2332                         }
2333                 }
2334 write:
2335                 /* For now, armv7m->demcr only stores vector catch flags. */
2336                 armv7m->demcr = catch;
2337
2338                 demcr &= ~0xffff;
2339                 demcr |= catch;
2340
2341                 /* write, but don't assume it stuck (why not??) */
2342                 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2343                 if (retval != ERROR_OK)
2344                         return retval;
2345                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2346                 if (retval != ERROR_OK)
2347                         return retval;
2348
2349                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2350                  * Otherwise the vector catch hardware could fire when there's
2351                  * no debugger hooked up, causing much confusion...
2352                  */
2353         }
2354
2355         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2356                 command_print(CMD, "%9s: %s", vec_ids[i].name,
2357                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2358         }
2359
2360         return ERROR_OK;
2361 }
2362
2363 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2364 {
2365         struct target *target = get_current_target(CMD_CTX);
2366         struct cortex_m_common *cortex_m = target_to_cm(target);
2367         int retval;
2368
2369         static const Jim_Nvp nvp_maskisr_modes[] = {
2370                 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2371                 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2372                 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2373                 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2374                 { .name = NULL, .value = -1 },
2375         };
2376         const Jim_Nvp *n;
2377
2378
2379         retval = cortex_m_verify_pointer(CMD, cortex_m);
2380         if (retval != ERROR_OK)
2381                 return retval;
2382
2383         if (target->state != TARGET_HALTED) {
2384                 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2385                 return ERROR_OK;
2386         }
2387
2388         if (CMD_ARGC > 0) {
2389                 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2390                 if (n->name == NULL)
2391                         return ERROR_COMMAND_SYNTAX_ERROR;
2392                 cortex_m->isrmasking_mode = n->value;
2393                 cortex_m_set_maskints_for_halt(target);
2394         }
2395
2396         n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2397         command_print(CMD, "cortex_m interrupt mask %s", n->name);
2398
2399         return ERROR_OK;
2400 }
2401
2402 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2403 {
2404         struct target *target = get_current_target(CMD_CTX);
2405         struct cortex_m_common *cortex_m = target_to_cm(target);
2406         int retval;
2407         char *reset_config;
2408
2409         retval = cortex_m_verify_pointer(CMD, cortex_m);
2410         if (retval != ERROR_OK)
2411                 return retval;
2412
2413         if (CMD_ARGC > 0) {
2414                 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2415                         cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2416
2417                 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2418                         if (target_was_examined(target)
2419                                         && !cortex_m->vectreset_supported)
2420                                 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2421                         else
2422                                 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2423
2424                 } else
2425                         return ERROR_COMMAND_SYNTAX_ERROR;
2426         }
2427
2428         switch (cortex_m->soft_reset_config) {
2429                 case CORTEX_M_RESET_SYSRESETREQ:
2430                         reset_config = "sysresetreq";
2431                         break;
2432
2433                 case CORTEX_M_RESET_VECTRESET:
2434                         reset_config = "vectreset";
2435                         break;
2436
2437                 default:
2438                         reset_config = "unknown";
2439                         break;
2440         }
2441
2442         command_print(CMD, "cortex_m reset_config %s", reset_config);
2443
2444         return ERROR_OK;
2445 }
2446
2447 static const struct command_registration cortex_m_exec_command_handlers[] = {
2448         {
2449                 .name = "maskisr",
2450                 .handler = handle_cortex_m_mask_interrupts_command,
2451                 .mode = COMMAND_EXEC,
2452                 .help = "mask cortex_m interrupts",
2453                 .usage = "['auto'|'on'|'off'|'steponly']",
2454         },
2455         {
2456                 .name = "vector_catch",
2457                 .handler = handle_cortex_m_vector_catch_command,
2458                 .mode = COMMAND_EXEC,
2459                 .help = "configure hardware vectors to trigger debug entry",
2460                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2461         },
2462         {
2463                 .name = "reset_config",
2464                 .handler = handle_cortex_m_reset_config_command,
2465                 .mode = COMMAND_ANY,
2466                 .help = "configure software reset handling",
2467                 .usage = "['sysresetreq'|'vectreset']",
2468         },
2469         COMMAND_REGISTRATION_DONE
2470 };
2471 static const struct command_registration cortex_m_command_handlers[] = {
2472         {
2473                 .chain = armv7m_command_handlers,
2474         },
2475         {
2476                 .chain = armv7m_trace_command_handlers,
2477         },
2478         {
2479                 .name = "cortex_m",
2480                 .mode = COMMAND_EXEC,
2481                 .help = "Cortex-M command group",
2482                 .usage = "",
2483                 .chain = cortex_m_exec_command_handlers,
2484         },
2485         COMMAND_REGISTRATION_DONE
2486 };
2487
2488 struct target_type cortexm_target = {
2489         .name = "cortex_m",
2490         .deprecated_name = "cortex_m3",
2491
2492         .poll = cortex_m_poll,
2493         .arch_state = armv7m_arch_state,
2494
2495         .target_request_data = cortex_m_target_request_data,
2496
2497         .halt = cortex_m_halt,
2498         .resume = cortex_m_resume,
2499         .step = cortex_m_step,
2500
2501         .assert_reset = cortex_m_assert_reset,
2502         .deassert_reset = cortex_m_deassert_reset,
2503         .soft_reset_halt = cortex_m_soft_reset_halt,
2504
2505         .get_gdb_arch = arm_get_gdb_arch,
2506         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2507
2508         .read_memory = cortex_m_read_memory,
2509         .write_memory = cortex_m_write_memory,
2510         .checksum_memory = armv7m_checksum_memory,
2511         .blank_check_memory = armv7m_blank_check_memory,
2512
2513         .run_algorithm = armv7m_run_algorithm,
2514         .start_algorithm = armv7m_start_algorithm,
2515         .wait_algorithm = armv7m_wait_algorithm,
2516
2517         .add_breakpoint = cortex_m_add_breakpoint,
2518         .remove_breakpoint = cortex_m_remove_breakpoint,
2519         .add_watchpoint = cortex_m_add_watchpoint,
2520         .remove_watchpoint = cortex_m_remove_watchpoint,
2521
2522         .commands = cortex_m_command_handlers,
2523         .target_create = cortex_m_target_create,
2524         .target_jim_configure = adiv5_jim_configure,
2525         .init_target = cortex_m_init_target,
2526         .examine = cortex_m_examine,
2527         .deinit_target = cortex_m_deinit_target,
2528
2529         .profiling = cortex_m_profiling,
2530 };