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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  *                                                                         *
  24  *                                                                         *
  25  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  26  *                                                                         *
  27  ***************************************************************************/
  28 #ifdef HAVE_CONFIG_H
  29 #include "config.h"
  30 #endif
  31
  32 #include "jtag/interface.h"
  33 #include "breakpoints.h"
  34 #include "cortex_m.h"
  35 #include "target_request.h"
  36 #include "target_type.h"
  37 #include "arm_disassembler.h"
  38 #include "register.h"
  39 #include "arm_opcodes.h"
  40 #include "arm_semihosting.h"
  41 #include <helper/time_support.h>
  42
  43 /* NOTE:  most of this should work fine for the Cortex-M1 and
  44  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  45  * Some differences:  M0/M1 doesn't have FPB remapping or the
  46  * DWT tracing/profiling support.  (So the cycle counter will
  47  * not be usable; the other stuff isn't currently used here.)
  48  *
  49  * Although there are some workarounds for errata seen only in r0p0
  50  * silicon, such old parts are hard to find and thus not much tested
  51  * any longer.
  52  */
  53
  54 /* forward declarations */
  55 static int cortex_m_store_core_reg_u32(struct target *target,
  56                 uint32_t num, uint32_t value);
  57 static void cortex_m_dwt_free(struct target *target);
  58
  59 static int cortexm_dap_read_coreregister_u32(struct target *target,
  60         uint32_t *value, int regnum)
  61 {
  62         struct armv7m_common *armv7m = target_to_armv7m(target);
  63         int retval;
  64         uint32_t dcrdr;
  65
  66         /* because the DCB_DCRDR is used for the emulated dcc channel
  67          * we have to save/restore the DCB_DCRDR when used */
  68         if (target->dbg_msg_enabled) {
  69                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
  70                 if (retval != ERROR_OK)
  71                         return retval;
  72         }
  73
  74         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
  75         if (retval != ERROR_OK)
  76                 return retval;
  77
  78         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
  79         if (retval != ERROR_OK)
  80                 return retval;
  81
  82         if (target->dbg_msg_enabled) {
  83                 /* restore DCB_DCRDR - this needs to be in a separate
  84                  * transaction otherwise the emulated DCC channel breaks */
  85                 if (retval == ERROR_OK)
  86                         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
  87         }
  88
  89         return retval;
  90 }
  91
  92 static int cortexm_dap_write_coreregister_u32(struct target *target,
  93         uint32_t value, int regnum)
  94 {
  95         struct armv7m_common *armv7m = target_to_armv7m(target);
  96         int retval;
  97         uint32_t dcrdr;
  98
  99         /* because the DCB_DCRDR is used for the emulated dcc channel
 100          * we have to save/restore the DCB_DCRDR when used */
 101         if (target->dbg_msg_enabled) {
 102                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
 103                 if (retval != ERROR_OK)
 104                         return retval;
 105         }
 106
 107         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
 108         if (retval != ERROR_OK)
 109                 return retval;
 110
 111         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
 112         if (retval != ERROR_OK)
 113                 return retval;
 114
 115         if (target->dbg_msg_enabled) {
 116                 /* restore DCB_DCRDR - this needs to be in a seperate
 117                  * transaction otherwise the emulated DCC channel breaks */
 118                 if (retval == ERROR_OK)
 119                         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
 120         }
 121
 122         return retval;
 123 }
 124
 125 static int cortex_m_write_debug_halt_mask(struct target *target,
 126         uint32_t mask_on, uint32_t mask_off)
 127 {
 128         struct cortex_m_common *cortex_m = target_to_cm(target);
 129         struct armv7m_common *armv7m = &cortex_m->armv7m;
 130
 131         /* mask off status bits */
 132         cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
 133         /* create new register mask */
 134         cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 135
 136         return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
 137 }
 138
 139 static int cortex_m_set_maskints(struct target *target, bool mask)
 140 {
 141         struct cortex_m_common *cortex_m = target_to_cm(target);
 142         if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
 143                 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
 144         else
 145                 return ERROR_OK;
 146 }
 147
 148 static int cortex_m_set_maskints_for_halt(struct target *target)
 149 {
 150         struct cortex_m_common *cortex_m = target_to_cm(target);
 151         switch (cortex_m->isrmasking_mode) {
 152                 case CORTEX_M_ISRMASK_AUTO:
 153                         /* interrupts taken at resume, whether for step or run -> no mask */
 154                         return cortex_m_set_maskints(target, false);
 155
 156                 case CORTEX_M_ISRMASK_OFF:
 157                         /* interrupts never masked */
 158                         return cortex_m_set_maskints(target, false);
 159
 160                 case CORTEX_M_ISRMASK_ON:
 161                         /* interrupts always masked */
 162                         return cortex_m_set_maskints(target, true);
 163
 164                 case CORTEX_M_ISRMASK_STEPONLY:
 165                         /* interrupts masked for single step only -> mask now if MASKINTS
 166                          * erratum, otherwise only mask before stepping */
 167                         return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
 168         }
 169         return ERROR_OK;
 170 }
 171
 172 static int cortex_m_set_maskints_for_run(struct target *target)
 173 {
 174         switch (target_to_cm(target)->isrmasking_mode) {
 175                 case CORTEX_M_ISRMASK_AUTO:
 176                         /* interrupts taken at resume, whether for step or run -> no mask */
 177                         return cortex_m_set_maskints(target, false);
 178
 179                 case CORTEX_M_ISRMASK_OFF:
 180                         /* interrupts never masked */
 181                         return cortex_m_set_maskints(target, false);
 182
 183                 case CORTEX_M_ISRMASK_ON:
 184                         /* interrupts always masked */
 185                         return cortex_m_set_maskints(target, true);
 186
 187                 case CORTEX_M_ISRMASK_STEPONLY:
 188                         /* interrupts masked for single step only -> no mask */
 189                         return cortex_m_set_maskints(target, false);
 190         }
 191         return ERROR_OK;
 192 }
 193
 194 static int cortex_m_set_maskints_for_step(struct target *target)
 195 {
 196         switch (target_to_cm(target)->isrmasking_mode) {
 197                 case CORTEX_M_ISRMASK_AUTO:
 198                         /* the auto-interrupt should already be done -> mask */
 199                         return cortex_m_set_maskints(target, true);
 200
 201                 case CORTEX_M_ISRMASK_OFF:
 202                         /* interrupts never masked */
 203                         return cortex_m_set_maskints(target, false);
 204
 205                 case CORTEX_M_ISRMASK_ON:
 206                         /* interrupts always masked */
 207                         return cortex_m_set_maskints(target, true);
 208
 209                 case CORTEX_M_ISRMASK_STEPONLY:
 210                         /* interrupts masked for single step only -> mask */
 211                         return cortex_m_set_maskints(target, true);
 212         }
 213         return ERROR_OK;
 214 }
 215
 216 static int cortex_m_clear_halt(struct target *target)
 217 {
 218         struct cortex_m_common *cortex_m = target_to_cm(target);
 219         struct armv7m_common *armv7m = &cortex_m->armv7m;
 220         int retval;
 221
 222         /* clear step if any */
 223         cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
 224
 225         /* Read Debug Fault Status Register */
 226         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
 227         if (retval != ERROR_OK)
 228                 return retval;
 229
 230         /* Clear Debug Fault Status */
 231         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
 232         if (retval != ERROR_OK)
 233                 return retval;
 234         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
 235
 236         return ERROR_OK;
 237 }
 238
 239 static int cortex_m_single_step_core(struct target *target)
 240 {
 241         struct cortex_m_common *cortex_m = target_to_cm(target);
 242         struct armv7m_common *armv7m = &cortex_m->armv7m;
 243         int retval;
 244
 245         /* Mask interrupts before clearing halt, if not done already.  This avoids
 246          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 247          * HALT can put the core into an unknown state.
 248          */
 249         if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
 250                 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
 251                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 252                 if (retval != ERROR_OK)
 253                         return retval;
 254         }
 255         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
 256                         DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 257         if (retval != ERROR_OK)
 258                 return retval;
 259         LOG_DEBUG(" ");
 260
 261         /* restore dhcsr reg */
 262         cortex_m_clear_halt(target);
 263
 264         return ERROR_OK;
 265 }
 266
 267 static int cortex_m_enable_fpb(struct target *target)
 268 {
 269         int retval = target_write_u32(target, FP_CTRL, 3);
 270         if (retval != ERROR_OK)
 271                 return retval;
 272
 273         /* check the fpb is actually enabled */
 274         uint32_t fpctrl;
 275         retval = target_read_u32(target, FP_CTRL, &fpctrl);
 276         if (retval != ERROR_OK)
 277                 return retval;
 278
 279         if (fpctrl & 1)
 280                 return ERROR_OK;
 281
 282         return ERROR_FAIL;
 283 }
 284
 285 static int cortex_m_endreset_event(struct target *target)
 286 {
 287         int i;
 288         int retval;
 289         uint32_t dcb_demcr;
 290         struct cortex_m_common *cortex_m = target_to_cm(target);
 291         struct armv7m_common *armv7m = &cortex_m->armv7m;
 292         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 293         struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
 294         struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
 295
 296         /* REVISIT The four debug monitor bits are currently ignored... */
 297         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
 298         if (retval != ERROR_OK)
 299                 return retval;
 300         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
 301
 302         /* this register is used for emulated dcc channel */
 303         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
 304         if (retval != ERROR_OK)
 305                 return retval;
 306
 307         /* Enable debug requests */
 308         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 309         if (retval != ERROR_OK)
 310                 return retval;
 311         if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
 312                 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
 313                 if (retval != ERROR_OK)
 314                         return retval;
 315         }
 316
 317         /* Restore proper interrupt masking setting for running CPU. */
 318         cortex_m_set_maskints_for_run(target);
 319
 320         /* Enable features controlled by ITM and DWT blocks, and catch only
 321          * the vectors we were told to pay attention to.
 322          *
 323          * Target firmware is responsible for all fault handling policy
 324          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 325          * or manual updates to the NVIC SHCSR and CCR registers.
 326          */
 327         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
 328         if (retval != ERROR_OK)
 329                 return retval;
 330
 331         /* Paranoia: evidently some (early?) chips don't preserve all the
 332          * debug state (including FPB, DWT, etc) across reset...
 333          */
 334
 335         /* Enable FPB */
 336         retval = cortex_m_enable_fpb(target);
 337         if (retval != ERROR_OK) {
 338                 LOG_ERROR("Failed to enable the FPB");
 339                 return retval;
 340         }
 341
 342         cortex_m->fpb_enabled = true;
 343
 344         /* Restore FPB registers */
 345         for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
 346                 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 347                 if (retval != ERROR_OK)
 348                         return retval;
 349         }
 350
 351         /* Restore DWT registers */
 352         for (i = 0; i < cortex_m->dwt_num_comp; i++) {
 353                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 354                                 dwt_list[i].comp);
 355                 if (retval != ERROR_OK)
 356                         return retval;
 357                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 358                                 dwt_list[i].mask);
 359                 if (retval != ERROR_OK)
 360                         return retval;
 361                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 362                                 dwt_list[i].function);
 363                 if (retval != ERROR_OK)
 364                         return retval;
 365         }
 366         retval = dap_run(swjdp);
 367         if (retval != ERROR_OK)
 368                 return retval;
 369
 370         register_cache_invalidate(armv7m->arm.core_cache);
 371
 372         /* make sure we have latest dhcsr flags */
 373         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 374
 375         return retval;
 376 }
 377
 378 static int cortex_m_examine_debug_reason(struct target *target)
 379 {
 380         struct cortex_m_common *cortex_m = target_to_cm(target);
 381
 382         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
 383          * only check the debug reason if we don't know it already */
 384
 385         if ((target->debug_reason != DBG_REASON_DBGRQ)
 386                 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
 387                 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
 388                         target->debug_reason = DBG_REASON_BREAKPOINT;
 389                         if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 390                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 391                 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 392                         target->debug_reason = DBG_REASON_WATCHPOINT;
 393                 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
 394                         target->debug_reason = DBG_REASON_BREAKPOINT;
 395                 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
 396                         target->debug_reason = DBG_REASON_DBGRQ;
 397                 else    /* HALTED */
 398                         target->debug_reason = DBG_REASON_UNDEFINED;
 399         }
 400
 401         return ERROR_OK;
 402 }
 403
 404 static int cortex_m_examine_exception_reason(struct target *target)
 405 {
 406         uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
 407         struct armv7m_common *armv7m = target_to_armv7m(target);
 408         struct adiv5_dap *swjdp = armv7m->arm.dap;
 409         int retval;
 410
 411         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
 412         if (retval != ERROR_OK)
 413                 return retval;
 414         switch (armv7m->exception_number) {
 415                 case 2: /* NMI */
 416                         break;
 417                 case 3: /* Hard Fault */
 418                         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
 419                         if (retval != ERROR_OK)
 420                                 return retval;
 421                         if (except_sr & 0x40000000) {
 422                                 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
 423                                 if (retval != ERROR_OK)
 424                                         return retval;
 425                         }
 426                         break;
 427                 case 4: /* Memory Management */
 428                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 429                         if (retval != ERROR_OK)
 430                                 return retval;
 431                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
 432                         if (retval != ERROR_OK)
 433                                 return retval;
 434                         break;
 435                 case 5: /* Bus Fault */
 436                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 437                         if (retval != ERROR_OK)
 438                                 return retval;
 439                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
 440                         if (retval != ERROR_OK)
 441                                 return retval;
 442                         break;
 443                 case 6: /* Usage Fault */
 444                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 445                         if (retval != ERROR_OK)
 446                                 return retval;
 447                         break;
 448                 case 11:        /* SVCall */
 449                         break;
 450                 case 12:        /* Debug Monitor */
 451                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
 452                         if (retval != ERROR_OK)
 453                                 return retval;
 454                         break;
 455                 case 14:        /* PendSV */
 456                         break;
 457                 case 15:        /* SysTick */
 458                         break;
 459                 default:
 460                         except_sr = 0;
 461                         break;
 462         }
 463         retval = dap_run(swjdp);
 464         if (retval == ERROR_OK)
 465                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 466                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 467                         armv7m_exception_string(armv7m->exception_number),
 468                         shcsr, except_sr, cfsr, except_ar);
 469         return retval;
 470 }
 471
 472 static int cortex_m_debug_entry(struct target *target)
 473 {
 474         int i;
 475         uint32_t xPSR;
 476         int retval;
 477         struct cortex_m_common *cortex_m = target_to_cm(target);
 478         struct armv7m_common *armv7m = &cortex_m->armv7m;
 479         struct arm *arm = &armv7m->arm;
 480         struct reg *r;
 481
 482         LOG_DEBUG(" ");
 483
 484         /* Do this really early to minimize the window where the MASKINTS erratum
 485          * can pile up pending interrupts. */
 486         cortex_m_set_maskints_for_halt(target);
 487
 488         cortex_m_clear_halt(target);
 489         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 490         if (retval != ERROR_OK)
 491                 return retval;
 492
 493         retval = armv7m->examine_debug_reason(target);
 494         if (retval != ERROR_OK)
 495                 return retval;
 496
 497         /* Examine target state and mode
 498          * First load register accessible through core debug port */
 499         int num_regs = arm->core_cache->num_regs;
 500
 501         for (i = 0; i < num_regs; i++) {
 502                 r = &armv7m->arm.core_cache->reg_list[i];
 503                 if (!r->valid)
 504                         arm->read_core_reg(target, r, i, ARM_MODE_ANY);
 505         }
 506
 507         r = arm->cpsr;
 508         xPSR = buf_get_u32(r->value, 0, 32);
 509
 510         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 511         if (xPSR & 0xf00) {
 512                 r->dirty = r->valid;
 513                 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
 514         }
 515
 516         /* Are we in an exception handler */
 517         if (xPSR & 0x1FF) {
 518                 armv7m->exception_number = (xPSR & 0x1FF);
 519
 520                 arm->core_mode = ARM_MODE_HANDLER;
 521                 arm->map = armv7m_msp_reg_map;
 522         } else {
 523                 unsigned control = buf_get_u32(arm->core_cache
 524                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 525
 526                 /* is this thread privileged? */
 527                 arm->core_mode = control & 1
 528                         ? ARM_MODE_USER_THREAD
 529                         : ARM_MODE_THREAD;
 530
 531                 /* which stack is it using? */
 532                 if (control & 2)
 533                         arm->map = armv7m_psp_reg_map;
 534                 else
 535                         arm->map = armv7m_msp_reg_map;
 536
 537                 armv7m->exception_number = 0;
 538         }
 539
 540         if (armv7m->exception_number)
 541                 cortex_m_examine_exception_reason(target);
 542
 543         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 544                 arm_mode_name(arm->core_mode),
 545                 buf_get_u32(arm->pc->value, 0, 32),
 546                 target_state_name(target));
 547
 548         if (armv7m->post_debug_entry) {
 549                 retval = armv7m->post_debug_entry(target);
 550                 if (retval != ERROR_OK)
 551                         return retval;
 552         }
 553
 554         return ERROR_OK;
 555 }
 556
 557 static int cortex_m_poll(struct target *target)
 558 {
 559         int detected_failure = ERROR_OK;
 560         int retval = ERROR_OK;
 561         enum target_state prev_target_state = target->state;
 562         struct cortex_m_common *cortex_m = target_to_cm(target);
 563         struct armv7m_common *armv7m = &cortex_m->armv7m;
 564
 565         /* Read from Debug Halting Control and Status Register */
 566         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 567         if (retval != ERROR_OK) {
 568                 target->state = TARGET_UNKNOWN;
 569                 return retval;
 570         }
 571
 572         /* Recover from lockup.  See ARMv7-M architecture spec,
 573          * section B1.5.15 "Unrecoverable exception cases".
 574          */
 575         if (cortex_m->dcb_dhcsr & S_LOCKUP) {
 576                 LOG_ERROR("%s -- clearing lockup after double fault",
 577                         target_name(target));
 578                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 579                 target->debug_reason = DBG_REASON_DBGRQ;
 580
 581                 /* We have to execute the rest (the "finally" equivalent, but
 582                  * still throw this exception again).
 583                  */
 584                 detected_failure = ERROR_FAIL;
 585
 586                 /* refresh status bits */
 587                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 588                 if (retval != ERROR_OK)
 589                         return retval;
 590         }
 591
 592         if (cortex_m->dcb_dhcsr & S_RESET_ST) {
 593                 if (target->state != TARGET_RESET) {
 594                         target->state = TARGET_RESET;
 595                         LOG_INFO("%s: external reset detected", target_name(target));
 596                 }
 597                 return ERROR_OK;
 598         }
 599
 600         if (target->state == TARGET_RESET) {
 601                 /* Cannot switch context while running so endreset is
 602                  * called with target->state == TARGET_RESET
 603                  */
 604                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 605                         cortex_m->dcb_dhcsr);
 606                 retval = cortex_m_endreset_event(target);
 607                 if (retval != ERROR_OK) {
 608                         target->state = TARGET_UNKNOWN;
 609                         return retval;
 610                 }
 611                 target->state = TARGET_RUNNING;
 612                 prev_target_state = TARGET_RUNNING;
 613         }
 614
 615         if (cortex_m->dcb_dhcsr & S_HALT) {
 616                 target->state = TARGET_HALTED;
 617
 618                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
 619                         retval = cortex_m_debug_entry(target);
 620                         if (retval != ERROR_OK)
 621                                 return retval;
 622
 623                         if (arm_semihosting(target, &retval) != 0)
 624                                 return retval;
 625
 626                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 627                 }
 628                 if (prev_target_state == TARGET_DEBUG_RUNNING) {
 629                         LOG_DEBUG(" ");
 630                         retval = cortex_m_debug_entry(target);
 631                         if (retval != ERROR_OK)
 632                                 return retval;
 633
 634                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 635                 }
 636         }
 637
 638         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 639          * How best to model low power modes?
 640          */
 641
 642         if (target->state == TARGET_UNKNOWN) {
 643                 /* check if processor is retiring instructions */
 644                 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
 645                         target->state = TARGET_RUNNING;
 646                         retval = ERROR_OK;
 647                 }
 648         }
 649
 650         /* Check that target is truly halted, since the target could be resumed externally */
 651         if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
 652                 /* registers are now invalid */
 653                 register_cache_invalidate(armv7m->arm.core_cache);
 654
 655                 target->state = TARGET_RUNNING;
 656                 LOG_WARNING("%s: external resume detected", target_name(target));
 657                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 658                 retval = ERROR_OK;
 659         }
 660
 661         /* Did we detect a failure condition that we cleared? */
 662         if (detected_failure != ERROR_OK)
 663                 retval = detected_failure;
 664         return retval;
 665 }
 666
 667 static int cortex_m_halt(struct target *target)
 668 {
 669         LOG_DEBUG("target->state: %s",
 670                 target_state_name(target));
 671
 672         if (target->state == TARGET_HALTED) {
 673                 LOG_DEBUG("target was already halted");
 674                 return ERROR_OK;
 675         }
 676
 677         if (target->state == TARGET_UNKNOWN)
 678                 LOG_WARNING("target was in unknown state when halt was requested");
 679
 680         if (target->state == TARGET_RESET) {
 681                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 682                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 683                         return ERROR_TARGET_FAILURE;
 684                 } else {
 685                         /* we came here in a reset_halt or reset_init sequence
 686                          * debug entry was already prepared in cortex_m3_assert_reset()
 687                          */
 688                         target->debug_reason = DBG_REASON_DBGRQ;
 689
 690                         return ERROR_OK;
 691                 }
 692         }
 693
 694         /* Write to Debug Halting Control and Status Register */
 695         cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 696
 697         /* Do this really early to minimize the window where the MASKINTS erratum
 698          * can pile up pending interrupts. */
 699         cortex_m_set_maskints_for_halt(target);
 700
 701         target->debug_reason = DBG_REASON_DBGRQ;
 702
 703         return ERROR_OK;
 704 }
 705
 706 static int cortex_m_soft_reset_halt(struct target *target)
 707 {
 708         struct cortex_m_common *cortex_m = target_to_cm(target);
 709         struct armv7m_common *armv7m = &cortex_m->armv7m;
 710         uint32_t dcb_dhcsr = 0;
 711         int retval, timeout = 0;
 712
 713         /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
 714          * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
 715          * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
 716          * core, not the peripherals */
 717         LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
 718
 719         /* Set C_DEBUGEN */
 720         retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
 721         if (retval != ERROR_OK)
 722                 return retval;
 723
 724         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 725         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
 726                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 727         if (retval != ERROR_OK)
 728                 return retval;
 729
 730         /* Request a core-only reset */
 731         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
 732                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 733         if (retval != ERROR_OK)
 734                 return retval;
 735         target->state = TARGET_RESET;
 736
 737         /* registers are now invalid */
 738         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 739
 740         while (timeout < 100) {
 741                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
 742                 if (retval == ERROR_OK) {
 743                         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
 744                                         &cortex_m->nvic_dfsr);
 745                         if (retval != ERROR_OK)
 746                                 return retval;
 747                         if ((dcb_dhcsr & S_HALT)
 748                                 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
 749                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 750                                         "DFSR 0x%08x",
 751                                         (unsigned) dcb_dhcsr,
 752                                         (unsigned) cortex_m->nvic_dfsr);
 753                                 cortex_m_poll(target);
 754                                 /* FIXME restore user's vector catch config */
 755                                 return ERROR_OK;
 756                         } else
 757                                 LOG_DEBUG("waiting for system reset-halt, "
 758                                         "DHCSR 0x%08x, %d ms",
 759                                         (unsigned) dcb_dhcsr, timeout);
 760                 }
 761                 timeout++;
 762                 alive_sleep(1);
 763         }
 764
 765         return ERROR_OK;
 766 }
 767
 768 void cortex_m_enable_breakpoints(struct target *target)
 769 {
 770         struct breakpoint *breakpoint = target->breakpoints;
 771
 772         /* set any pending breakpoints */
 773         while (breakpoint) {
 774                 if (!breakpoint->set)
 775                         cortex_m_set_breakpoint(target, breakpoint);
 776                 breakpoint = breakpoint->next;
 777         }
 778 }
 779
 780 static int cortex_m_resume(struct target *target, int current,
 781         target_addr_t address, int handle_breakpoints, int debug_execution)
 782 {
 783         struct armv7m_common *armv7m = target_to_armv7m(target);
 784         struct breakpoint *breakpoint = NULL;
 785         uint32_t resume_pc;
 786         struct reg *r;
 787
 788         if (target->state != TARGET_HALTED) {
 789                 LOG_WARNING("target not halted");
 790                 return ERROR_TARGET_NOT_HALTED;
 791         }
 792
 793         if (!debug_execution) {
 794                 target_free_all_working_areas(target);
 795                 cortex_m_enable_breakpoints(target);
 796                 cortex_m_enable_watchpoints(target);
 797         }
 798
 799         if (debug_execution) {
 800                 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
 801
 802                 /* Disable interrupts */
 803                 /* We disable interrupts in the PRIMASK register instead of
 804                  * masking with C_MASKINTS.  This is probably the same issue
 805                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 806                  * in parallel with disabled interrupts can cause local faults
 807                  * to not be taken.
 808                  *
 809                  * REVISIT this clearly breaks non-debug execution, since the
 810                  * PRIMASK register state isn't saved/restored...  workaround
 811                  * by never resuming app code after debug execution.
 812                  */
 813                 buf_set_u32(r->value, 0, 1, 1);
 814                 r->dirty = true;
 815                 r->valid = true;
 816
 817                 /* Make sure we are in Thumb mode */
 818                 r = armv7m->arm.cpsr;
 819                 buf_set_u32(r->value, 24, 1, 1);
 820                 r->dirty = true;
 821                 r->valid = true;
 822         }
 823
 824         /* current = 1: continue on current pc, otherwise continue at <address> */
 825         r = armv7m->arm.pc;
 826         if (!current) {
 827                 buf_set_u32(r->value, 0, 32, address);
 828                 r->dirty = true;
 829                 r->valid = true;
 830         }
 831
 832         /* if we halted last time due to a bkpt instruction
 833          * then we have to manually step over it, otherwise
 834          * the core will break again */
 835
 836         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 837                 && !debug_execution)
 838                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 839
 840         resume_pc = buf_get_u32(r->value, 0, 32);
 841
 842         armv7m_restore_context(target);
 843
 844         /* the front-end may request us not to handle breakpoints */
 845         if (handle_breakpoints) {
 846                 /* Single step past breakpoint at current address */
 847                 breakpoint = breakpoint_find(target, resume_pc);
 848                 if (breakpoint) {
 849                         LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
 850                                 breakpoint->address,
 851                                 breakpoint->unique_id);
 852                         cortex_m_unset_breakpoint(target, breakpoint);
 853                         cortex_m_single_step_core(target);
 854                         cortex_m_set_breakpoint(target, breakpoint);
 855                 }
 856         }
 857
 858         /* Restart core */
 859         cortex_m_set_maskints_for_run(target);
 860         cortex_m_write_debug_halt_mask(target, 0, C_HALT);
 861
 862         target->debug_reason = DBG_REASON_NOTHALTED;
 863
 864         /* registers are now invalid */
 865         register_cache_invalidate(armv7m->arm.core_cache);
 866
 867         if (!debug_execution) {
 868                 target->state = TARGET_RUNNING;
 869                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 870                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 871         } else {
 872                 target->state = TARGET_DEBUG_RUNNING;
 873                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 874                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 875         }
 876
 877         return ERROR_OK;
 878 }
 879
 880 /* int irqstepcount = 0; */
 881 static int cortex_m_step(struct target *target, int current,
 882         target_addr_t address, int handle_breakpoints)
 883 {
 884         struct cortex_m_common *cortex_m = target_to_cm(target);
 885         struct armv7m_common *armv7m = &cortex_m->armv7m;
 886         struct breakpoint *breakpoint = NULL;
 887         struct reg *pc = armv7m->arm.pc;
 888         bool bkpt_inst_found = false;
 889         int retval;
 890         bool isr_timed_out = false;
 891
 892         if (target->state != TARGET_HALTED) {
 893                 LOG_WARNING("target not halted");
 894                 return ERROR_TARGET_NOT_HALTED;
 895         }
 896
 897         /* current = 1: continue on current pc, otherwise continue at <address> */
 898         if (!current)
 899                 buf_set_u32(pc->value, 0, 32, address);
 900
 901         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
 902
 903         /* the front-end may request us not to handle breakpoints */
 904         if (handle_breakpoints) {
 905                 breakpoint = breakpoint_find(target, pc_value);
 906                 if (breakpoint)
 907                         cortex_m_unset_breakpoint(target, breakpoint);
 908         }
 909
 910         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 911
 912         target->debug_reason = DBG_REASON_SINGLESTEP;
 913
 914         armv7m_restore_context(target);
 915
 916         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 917
 918         /* if no bkpt instruction is found at pc then we can perform
 919          * a normal step, otherwise we have to manually step over the bkpt
 920          * instruction - as such simulate a step */
 921         if (bkpt_inst_found == false) {
 922                 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
 923                         /* Automatic ISR masking mode off: Just step over the next
 924                          * instruction, with interrupts on or off as appropriate. */
 925                         cortex_m_set_maskints_for_step(target);
 926                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 927                 } else {
 928                         /* Process interrupts during stepping in a way they don't interfere
 929                          * debugging.
 930                          *
 931                          * Principle:
 932                          *
 933                          * Set a temporary break point at the current pc and let the core run
 934                          * with interrupts enabled. Pending interrupts get served and we run
 935                          * into the breakpoint again afterwards. Then we step over the next
 936                          * instruction with interrupts disabled.
 937                          *
 938                          * If the pending interrupts don't complete within time, we leave the
 939                          * core running. This may happen if the interrupts trigger faster
 940                          * than the core can process them or the handler doesn't return.
 941                          *
 942                          * If no more breakpoints are available we simply do a step with
 943                          * interrupts enabled.
 944                          *
 945                          */
 946
 947                         /* 2012-09-29 ph
 948                          *
 949                          * If a break point is already set on the lower half word then a break point on
 950                          * the upper half word will not break again when the core is restarted. So we
 951                          * just step over the instruction with interrupts disabled.
 952                          *
 953                          * The documentation has no information about this, it was found by observation
 954                          * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
 955                          * suffer from this problem.
 956                          *
 957                          * To add some confusion: pc_value has bit 0 always set, while the breakpoint
 958                          * address has it always cleared. The former is done to indicate thumb mode
 959                          * to gdb.
 960                          *
 961                          */
 962                         if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
 963                                 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
 964                                 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
 965                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 966                                 /* Re-enable interrupts if appropriate */
 967                                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 968                                 cortex_m_set_maskints_for_halt(target);
 969                         } else {
 970
 971                                 /* Set a temporary break point */
 972                                 if (breakpoint) {
 973                                         retval = cortex_m_set_breakpoint(target, breakpoint);
 974                                 } else {
 975                                         enum breakpoint_type type = BKPT_HARD;
 976                                         if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
 977                                                 /* FPB rev.1 cannot handle such addr, try BKPT instr */
 978                                                 type = BKPT_SOFT;
 979                                         }
 980                                         retval = breakpoint_add(target, pc_value, 2, type);
 981                                 }
 982
 983                                 bool tmp_bp_set = (retval == ERROR_OK);
 984
 985                                 /* No more breakpoints left, just do a step */
 986                                 if (!tmp_bp_set) {
 987                                         cortex_m_set_maskints_for_step(target);
 988                                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 989                                         /* Re-enable interrupts if appropriate */
 990                                         cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 991                                         cortex_m_set_maskints_for_halt(target);
 992                                 } else {
 993                                         /* Start the core */
 994                                         LOG_DEBUG("Starting core to serve pending interrupts");
 995                                         int64_t t_start = timeval_ms();
 996                                         cortex_m_set_maskints_for_run(target);
 997                                         cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
 998
 999                                         /* Wait for pending handlers to complete or timeout */
1000                                         do {
1001                                                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
1002                                                                 DCB_DHCSR,
1003                                                                 &cortex_m->dcb_dhcsr);
1004                                                 if (retval != ERROR_OK) {
1005                                                         target->state = TARGET_UNKNOWN;
1006                                                         return retval;
1007                                                 }
1008                                                 isr_timed_out = ((timeval_ms() - t_start) > 500);
1009                                         } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1010
1011                                         /* only remove breakpoint if we created it */
1012                                         if (breakpoint)
1013                                                 cortex_m_unset_breakpoint(target, breakpoint);
1014                                         else {
1015                                                 /* Remove the temporary breakpoint */
1016                                                 breakpoint_remove(target, pc_value);
1017                                         }
1018
1019                                         if (isr_timed_out) {
1020                                                 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1021                                                         "leaving target running");
1022                                         } else {
1023                                                 /* Step over next instruction with interrupts disabled */
1024                                                 cortex_m_set_maskints_for_step(target);
1025                                                 cortex_m_write_debug_halt_mask(target,
1026                                                         C_HALT | C_MASKINTS,
1027                                                         0);
1028                                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1029                                                 /* Re-enable interrupts if appropriate */
1030                                                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1031                                                 cortex_m_set_maskints_for_halt(target);
1032                                         }
1033                                 }
1034                         }
1035                 }
1036         }
1037
1038         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1039         if (retval != ERROR_OK)
1040                 return retval;
1041
1042         /* registers are now invalid */
1043         register_cache_invalidate(armv7m->arm.core_cache);
1044
1045         if (breakpoint)
1046                 cortex_m_set_breakpoint(target, breakpoint);
1047
1048         if (isr_timed_out) {
1049                 /* Leave the core running. The user has to stop execution manually. */
1050                 target->debug_reason = DBG_REASON_NOTHALTED;
1051                 target->state = TARGET_RUNNING;
1052                 return ERROR_OK;
1053         }
1054
1055         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1056                 " nvic_icsr = 0x%" PRIx32,
1057                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1058
1059         retval = cortex_m_debug_entry(target);
1060         if (retval != ERROR_OK)
1061                 return retval;
1062         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1063
1064         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1065                 " nvic_icsr = 0x%" PRIx32,
1066                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1067
1068         return ERROR_OK;
1069 }
1070
1071 static int cortex_m_assert_reset(struct target *target)
1072 {
1073         struct cortex_m_common *cortex_m = target_to_cm(target);
1074         struct armv7m_common *armv7m = &cortex_m->armv7m;
1075         enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1076
1077         LOG_DEBUG("target->state: %s",
1078                 target_state_name(target));
1079
1080         enum reset_types jtag_reset_config = jtag_get_reset_config();
1081
1082         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1083                 /* allow scripts to override the reset event */
1084
1085                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1086                 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1087                 target->state = TARGET_RESET;
1088
1089                 return ERROR_OK;
1090         }
1091
1092         /* some cores support connecting while srst is asserted
1093          * use that mode is it has been configured */
1094
1095         bool srst_asserted = false;
1096
1097         if (!target_was_examined(target)) {
1098                 if (jtag_reset_config & RESET_HAS_SRST) {
1099                         adapter_assert_reset();
1100                         if (target->reset_halt)
1101                                 LOG_ERROR("Target not examined, will not halt after reset!");
1102                         return ERROR_OK;
1103                 } else {
1104                         LOG_ERROR("Target not examined, reset NOT asserted!");
1105                         return ERROR_FAIL;
1106                 }
1107         }
1108
1109         if ((jtag_reset_config & RESET_HAS_SRST) &&
1110             (jtag_reset_config & RESET_SRST_NO_GATING)) {
1111                 adapter_assert_reset();
1112                 srst_asserted = true;
1113         }
1114
1115         /* Enable debug requests */
1116         int retval;
1117         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1118         /* Store important errors instead of failing and proceed to reset assert */
1119
1120         if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1121                 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1122
1123         /* If the processor is sleeping in a WFI or WFE instruction, the
1124          * C_HALT bit must be asserted to regain control */
1125         if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1126                 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1127
1128         mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1129         /* Ignore less important errors */
1130
1131         if (!target->reset_halt) {
1132                 /* Set/Clear C_MASKINTS in a separate operation */
1133                 cortex_m_set_maskints_for_run(target);
1134
1135                 /* clear any debug flags before resuming */
1136                 cortex_m_clear_halt(target);
1137
1138                 /* clear C_HALT in dhcsr reg */
1139                 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1140         } else {
1141                 /* Halt in debug on reset; endreset_event() restores DEMCR.
1142                  *
1143                  * REVISIT catching BUSERR presumably helps to defend against
1144                  * bad vector table entries.  Should this include MMERR or
1145                  * other flags too?
1146                  */
1147                 int retval2;
1148                 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1149                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1150                 if (retval != ERROR_OK || retval2 != ERROR_OK)
1151                         LOG_INFO("AP write error, reset will not halt");
1152         }
1153
1154         if (jtag_reset_config & RESET_HAS_SRST) {
1155                 /* default to asserting srst */
1156                 if (!srst_asserted)
1157                         adapter_assert_reset();
1158
1159                 /* srst is asserted, ignore AP access errors */
1160                 retval = ERROR_OK;
1161         } else {
1162                 /* Use a standard Cortex-M3 software reset mechanism.
1163                  * We default to using VECRESET as it is supported on all current cores
1164                  * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1165                  * This has the disadvantage of not resetting the peripherals, so a
1166                  * reset-init event handler is needed to perform any peripheral resets.
1167                  */
1168                 if (!cortex_m->vectreset_supported
1169                                 && reset_config == CORTEX_M_RESET_VECTRESET) {
1170                         reset_config = CORTEX_M_RESET_SYSRESETREQ;
1171                         LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1172                         LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1173                 }
1174
1175                 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1176                         ? "SYSRESETREQ" : "VECTRESET");
1177
1178                 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1179                         LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1180                                 "handler to reset any peripherals or configure hardware srst support.");
1181                 }
1182
1183                 int retval3;
1184                 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1185                                 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1186                                 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1187                 if (retval3 != ERROR_OK)
1188                         LOG_DEBUG("Ignoring AP write error right after reset");
1189
1190                 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1191                 if (retval3 != ERROR_OK)
1192                         LOG_ERROR("DP initialisation failed");
1193
1194                 else {
1195                         /* I do not know why this is necessary, but it
1196                          * fixes strange effects (step/resume cause NMI
1197                          * after reset) on LM3S6918 -- Michael Schwingen
1198                          */
1199                         uint32_t tmp;
1200                         mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1201                 }
1202         }
1203
1204         target->state = TARGET_RESET;
1205         jtag_sleep(50000);
1206
1207         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1208
1209         /* now return stored error code if any */
1210         if (retval != ERROR_OK)
1211                 return retval;
1212
1213         if (target->reset_halt) {
1214                 retval = target_halt(target);
1215                 if (retval != ERROR_OK)
1216                         return retval;
1217         }
1218
1219         return ERROR_OK;
1220 }
1221
1222 static int cortex_m_deassert_reset(struct target *target)
1223 {
1224         struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1225
1226         LOG_DEBUG("target->state: %s",
1227                 target_state_name(target));
1228
1229         /* deassert reset lines */
1230         adapter_deassert_reset();
1231
1232         enum reset_types jtag_reset_config = jtag_get_reset_config();
1233
1234         if ((jtag_reset_config & RESET_HAS_SRST) &&
1235             !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1236                 target_was_examined(target)) {
1237                 int retval = dap_dp_init(armv7m->debug_ap->dap);
1238                 if (retval != ERROR_OK) {
1239                         LOG_ERROR("DP initialisation failed");
1240                         return retval;
1241                 }
1242         }
1243
1244         return ERROR_OK;
1245 }
1246
1247 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1248 {
1249         int retval;
1250         int fp_num = 0;
1251         struct cortex_m_common *cortex_m = target_to_cm(target);
1252         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1253
1254         if (breakpoint->set) {
1255                 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1256                 return ERROR_OK;
1257         }
1258
1259         if (breakpoint->type == BKPT_HARD) {
1260                 uint32_t fpcr_value;
1261                 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1262                         fp_num++;
1263                 if (fp_num >= cortex_m->fp_num_code) {
1264                         LOG_ERROR("Can not find free FPB Comparator!");
1265                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1266                 }
1267                 breakpoint->set = fp_num + 1;
1268                 fpcr_value = breakpoint->address | 1;
1269                 if (cortex_m->fp_rev == 0) {
1270                         if (breakpoint->address > 0x1FFFFFFF) {
1271                                 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1272                                 return ERROR_FAIL;
1273                         }
1274                         uint32_t hilo;
1275                         hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1276                         fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1277                 } else if (cortex_m->fp_rev > 1) {
1278                         LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1279                         return ERROR_FAIL;
1280                 }
1281                 comparator_list[fp_num].used = true;
1282                 comparator_list[fp_num].fpcr_value = fpcr_value;
1283                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1284                         comparator_list[fp_num].fpcr_value);
1285                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1286                         fp_num,
1287                         comparator_list[fp_num].fpcr_value);
1288                 if (!cortex_m->fpb_enabled) {
1289                         LOG_DEBUG("FPB wasn't enabled, do it now");
1290                         retval = cortex_m_enable_fpb(target);
1291                         if (retval != ERROR_OK) {
1292                                 LOG_ERROR("Failed to enable the FPB");
1293                                 return retval;
1294                         }
1295
1296                         cortex_m->fpb_enabled = true;
1297                 }
1298         } else if (breakpoint->type == BKPT_SOFT) {
1299                 uint8_t code[4];
1300
1301                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1302                  * semihosting; don't use that.  Otherwise the BKPT
1303                  * parameter is arbitrary.
1304                  */
1305                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1306                 retval = target_read_memory(target,
1307                                 breakpoint->address & 0xFFFFFFFE,
1308                                 breakpoint->length, 1,
1309                                 breakpoint->orig_instr);
1310                 if (retval != ERROR_OK)
1311                         return retval;
1312                 retval = target_write_memory(target,
1313                                 breakpoint->address & 0xFFFFFFFE,
1314                                 breakpoint->length, 1,
1315                                 code);
1316                 if (retval != ERROR_OK)
1317                         return retval;
1318                 breakpoint->set = true;
1319         }
1320
1321         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1322                 breakpoint->unique_id,
1323                 (int)(breakpoint->type),
1324                 breakpoint->address,
1325                 breakpoint->length,
1326                 breakpoint->set);
1327
1328         return ERROR_OK;
1329 }
1330
1331 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1332 {
1333         int retval;
1334         struct cortex_m_common *cortex_m = target_to_cm(target);
1335         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1336
1337         if (!breakpoint->set) {
1338                 LOG_WARNING("breakpoint not set");
1339                 return ERROR_OK;
1340         }
1341
1342         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1343                 breakpoint->unique_id,
1344                 (int)(breakpoint->type),
1345                 breakpoint->address,
1346                 breakpoint->length,
1347                 breakpoint->set);
1348
1349         if (breakpoint->type == BKPT_HARD) {
1350                 int fp_num = breakpoint->set - 1;
1351                 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1352                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1353                         return ERROR_OK;
1354                 }
1355                 comparator_list[fp_num].used = false;
1356                 comparator_list[fp_num].fpcr_value = 0;
1357                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1358                         comparator_list[fp_num].fpcr_value);
1359         } else {
1360                 /* restore original instruction (kept in target endianness) */
1361                 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1362                                         breakpoint->length, 1,
1363                                         breakpoint->orig_instr);
1364                 if (retval != ERROR_OK)
1365                         return retval;
1366         }
1367         breakpoint->set = false;
1368
1369         return ERROR_OK;
1370 }
1371
1372 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1373 {
1374         if (breakpoint->length == 3) {
1375                 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1376                 breakpoint->length = 2;
1377         }
1378
1379         if ((breakpoint->length != 2)) {
1380                 LOG_INFO("only breakpoints of two bytes length supported");
1381                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1382         }
1383
1384         return cortex_m_set_breakpoint(target, breakpoint);
1385 }
1386
1387 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1388 {
1389         if (!breakpoint->set)
1390                 return ERROR_OK;
1391
1392         return cortex_m_unset_breakpoint(target, breakpoint);
1393 }
1394
1395 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1396 {
1397         int dwt_num = 0;
1398         struct cortex_m_common *cortex_m = target_to_cm(target);
1399
1400         /* REVISIT Don't fully trust these "not used" records ... users
1401          * may set up breakpoints by hand, e.g. dual-address data value
1402          * watchpoint using comparator #1; comparator #0 matching cycle
1403          * count; send data trace info through ITM and TPIU; etc
1404          */
1405         struct cortex_m_dwt_comparator *comparator;
1406
1407         for (comparator = cortex_m->dwt_comparator_list;
1408                 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1409                 comparator++, dwt_num++)
1410                 continue;
1411         if (dwt_num >= cortex_m->dwt_num_comp) {
1412                 LOG_ERROR("Can not find free DWT Comparator");
1413                 return ERROR_FAIL;
1414         }
1415         comparator->used = true;
1416         watchpoint->set = dwt_num + 1;
1417
1418         comparator->comp = watchpoint->address;
1419         target_write_u32(target, comparator->dwt_comparator_address + 0,
1420                 comparator->comp);
1421
1422         if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1423                 uint32_t mask = 0, temp;
1424
1425                 /* watchpoint params were validated earlier */
1426                 temp = watchpoint->length;
1427                 while (temp) {
1428                         temp >>= 1;
1429                         mask++;
1430                 }
1431                 mask--;
1432
1433                 comparator->mask = mask;
1434                 target_write_u32(target, comparator->dwt_comparator_address + 4,
1435                         comparator->mask);
1436
1437                 switch (watchpoint->rw) {
1438                 case WPT_READ:
1439                         comparator->function = 5;
1440                         break;
1441                 case WPT_WRITE:
1442                         comparator->function = 6;
1443                         break;
1444                 case WPT_ACCESS:
1445                         comparator->function = 7;
1446                         break;
1447                 }
1448         } else {
1449                 uint32_t data_size = watchpoint->length >> 1;
1450                 comparator->mask = (watchpoint->length >> 1) | 1;
1451
1452                 switch (watchpoint->rw) {
1453                 case WPT_ACCESS:
1454                         comparator->function = 4;
1455                         break;
1456                 case WPT_WRITE:
1457                         comparator->function = 5;
1458                         break;
1459                 case WPT_READ:
1460                         comparator->function = 6;
1461                         break;
1462                 }
1463                 comparator->function = comparator->function | (1 << 4) |
1464                                 (data_size << 10);
1465         }
1466
1467         target_write_u32(target, comparator->dwt_comparator_address + 8,
1468                 comparator->function);
1469
1470         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1471                 watchpoint->unique_id, dwt_num,
1472                 (unsigned) comparator->comp,
1473                 (unsigned) comparator->mask,
1474                 (unsigned) comparator->function);
1475         return ERROR_OK;
1476 }
1477
1478 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1479 {
1480         struct cortex_m_common *cortex_m = target_to_cm(target);
1481         struct cortex_m_dwt_comparator *comparator;
1482         int dwt_num;
1483
1484         if (!watchpoint->set) {
1485                 LOG_WARNING("watchpoint (wpid: %d) not set",
1486                         watchpoint->unique_id);
1487                 return ERROR_OK;
1488         }
1489
1490         dwt_num = watchpoint->set - 1;
1491
1492         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1493                 watchpoint->unique_id, dwt_num,
1494                 (unsigned) watchpoint->address);
1495
1496         if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1497                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1498                 return ERROR_OK;
1499         }
1500
1501         comparator = cortex_m->dwt_comparator_list + dwt_num;
1502         comparator->used = false;
1503         comparator->function = 0;
1504         target_write_u32(target, comparator->dwt_comparator_address + 8,
1505                 comparator->function);
1506
1507         watchpoint->set = false;
1508
1509         return ERROR_OK;
1510 }
1511
1512 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1513 {
1514         struct cortex_m_common *cortex_m = target_to_cm(target);
1515
1516         if (cortex_m->dwt_comp_available < 1) {
1517                 LOG_DEBUG("no comparators?");
1518                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1519         }
1520
1521         /* hardware doesn't support data value masking */
1522         if (watchpoint->mask != ~(uint32_t)0) {
1523                 LOG_DEBUG("watchpoint value masks not supported");
1524                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1525         }
1526
1527         /* hardware allows address masks of up to 32K */
1528         unsigned mask;
1529
1530         for (mask = 0; mask < 16; mask++) {
1531                 if ((1u << mask) == watchpoint->length)
1532                         break;
1533         }
1534         if (mask == 16) {
1535                 LOG_DEBUG("unsupported watchpoint length");
1536                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1537         }
1538         if (watchpoint->address & ((1 << mask) - 1)) {
1539                 LOG_DEBUG("watchpoint address is unaligned");
1540                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1541         }
1542
1543         /* Caller doesn't seem to be able to describe watching for data
1544          * values of zero; that flags "no value".
1545          *
1546          * REVISIT This DWT may well be able to watch for specific data
1547          * values.  Requires comparator #1 to set DATAVMATCH and match
1548          * the data, and another comparator (DATAVADDR0) matching addr.
1549          */
1550         if (watchpoint->value) {
1551                 LOG_DEBUG("data value watchpoint not YET supported");
1552                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1553         }
1554
1555         cortex_m->dwt_comp_available--;
1556         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1557
1558         return ERROR_OK;
1559 }
1560
1561 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1562 {
1563         struct cortex_m_common *cortex_m = target_to_cm(target);
1564
1565         /* REVISIT why check? DWT can be updated with core running ... */
1566         if (target->state != TARGET_HALTED) {
1567                 LOG_WARNING("target not halted");
1568                 return ERROR_TARGET_NOT_HALTED;
1569         }
1570
1571         if (watchpoint->set)
1572                 cortex_m_unset_watchpoint(target, watchpoint);
1573
1574         cortex_m->dwt_comp_available++;
1575         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1576
1577         return ERROR_OK;
1578 }
1579
1580 void cortex_m_enable_watchpoints(struct target *target)
1581 {
1582         struct watchpoint *watchpoint = target->watchpoints;
1583
1584         /* set any pending watchpoints */
1585         while (watchpoint) {
1586                 if (!watchpoint->set)
1587                         cortex_m_set_watchpoint(target, watchpoint);
1588                 watchpoint = watchpoint->next;
1589         }
1590 }
1591
1592 static int cortex_m_load_core_reg_u32(struct target *target,
1593                 uint32_t num, uint32_t *value)
1594 {
1595         int retval;
1596
1597         /* NOTE:  we "know" here that the register identifiers used
1598          * in the v7m header match the Cortex-M3 Debug Core Register
1599          * Selector values for R0..R15, xPSR, MSP, and PSP.
1600          */
1601         switch (num) {
1602                 case 0 ... 18:
1603                         /* read a normal core register */
1604                         retval = cortexm_dap_read_coreregister_u32(target, value, num);
1605
1606                         if (retval != ERROR_OK) {
1607                                 LOG_ERROR("JTAG failure %i", retval);
1608                                 return ERROR_JTAG_DEVICE_ERROR;
1609                         }
1610                         LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
1611                         break;
1612
1613                 case ARMV7M_FPSCR:
1614                         /* Floating-point Status and Registers */
1615                         retval = target_write_u32(target, DCB_DCRSR, 0x21);
1616                         if (retval != ERROR_OK)
1617                                 return retval;
1618                         retval = target_read_u32(target, DCB_DCRDR, value);
1619                         if (retval != ERROR_OK)
1620                                 return retval;
1621                         LOG_DEBUG("load from FPSCR  value 0x%" PRIx32, *value);
1622                         break;
1623
1624                 case ARMV7M_S0 ... ARMV7M_S31:
1625                         /* Floating-point Status and Registers */
1626                         retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1627                         if (retval != ERROR_OK)
1628                                 return retval;
1629                         retval = target_read_u32(target, DCB_DCRDR, value);
1630                         if (retval != ERROR_OK)
1631                                 return retval;
1632                         LOG_DEBUG("load from FPU reg S%d  value 0x%" PRIx32,
1633                                   (int)(num - ARMV7M_S0), *value);
1634                         break;
1635
1636                 case ARMV7M_PRIMASK:
1637                 case ARMV7M_BASEPRI:
1638                 case ARMV7M_FAULTMASK:
1639                 case ARMV7M_CONTROL:
1640                         /* Cortex-M3 packages these four registers as bitfields
1641                          * in one Debug Core register.  So say r0 and r2 docs;
1642                          * it was removed from r1 docs, but still works.
1643                          */
1644                         cortexm_dap_read_coreregister_u32(target, value, 20);
1645
1646                         switch (num) {
1647                                 case ARMV7M_PRIMASK:
1648                                         *value = buf_get_u32((uint8_t *)value, 0, 1);
1649                                         break;
1650
1651                                 case ARMV7M_BASEPRI:
1652                                         *value = buf_get_u32((uint8_t *)value, 8, 8);
1653                                         break;
1654
1655                                 case ARMV7M_FAULTMASK:
1656                                         *value = buf_get_u32((uint8_t *)value, 16, 1);
1657                                         break;
1658
1659                                 case ARMV7M_CONTROL:
1660                                         *value = buf_get_u32((uint8_t *)value, 24, 2);
1661                                         break;
1662                         }
1663
1664                         LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1665                         break;
1666
1667                 default:
1668                         return ERROR_COMMAND_SYNTAX_ERROR;
1669         }
1670
1671         return ERROR_OK;
1672 }
1673
1674 static int cortex_m_store_core_reg_u32(struct target *target,
1675                 uint32_t num, uint32_t value)
1676 {
1677         int retval;
1678         uint32_t reg;
1679         struct armv7m_common *armv7m = target_to_armv7m(target);
1680
1681         /* NOTE:  we "know" here that the register identifiers used
1682          * in the v7m header match the Cortex-M3 Debug Core Register
1683          * Selector values for R0..R15, xPSR, MSP, and PSP.
1684          */
1685         switch (num) {
1686                 case 0 ... 18:
1687                         retval = cortexm_dap_write_coreregister_u32(target, value, num);
1688                         if (retval != ERROR_OK) {
1689                                 struct reg *r;
1690
1691                                 LOG_ERROR("JTAG failure");
1692                                 r = armv7m->arm.core_cache->reg_list + num;
1693                                 r->dirty = r->valid;
1694                                 return ERROR_JTAG_DEVICE_ERROR;
1695                         }
1696                         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1697                         break;
1698
1699                 case ARMV7M_FPSCR:
1700                         /* Floating-point Status and Registers */
1701                         retval = target_write_u32(target, DCB_DCRDR, value);
1702                         if (retval != ERROR_OK)
1703                                 return retval;
1704                         retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1705                         if (retval != ERROR_OK)
1706                                 return retval;
1707                         LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1708                         break;
1709
1710                 case ARMV7M_S0 ... ARMV7M_S31:
1711                         /* Floating-point Status and Registers */
1712                         retval = target_write_u32(target, DCB_DCRDR, value);
1713                         if (retval != ERROR_OK)
1714                                 return retval;
1715                         retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1716                         if (retval != ERROR_OK)
1717                                 return retval;
1718                         LOG_DEBUG("write FPU reg S%d  value 0x%" PRIx32,
1719                                   (int)(num - ARMV7M_S0), value);
1720                         break;
1721
1722                 case ARMV7M_PRIMASK:
1723                 case ARMV7M_BASEPRI:
1724                 case ARMV7M_FAULTMASK:
1725                 case ARMV7M_CONTROL:
1726                         /* Cortex-M3 packages these four registers as bitfields
1727                          * in one Debug Core register.  So say r0 and r2 docs;
1728                          * it was removed from r1 docs, but still works.
1729                          */
1730                         cortexm_dap_read_coreregister_u32(target, &reg, 20);
1731
1732                         switch (num) {
1733                                 case ARMV7M_PRIMASK:
1734                                         buf_set_u32((uint8_t *)&reg, 0, 1, value);
1735                                         break;
1736
1737                                 case ARMV7M_BASEPRI:
1738                                         buf_set_u32((uint8_t *)&reg, 8, 8, value);
1739                                         break;
1740
1741                                 case ARMV7M_FAULTMASK:
1742                                         buf_set_u32((uint8_t *)&reg, 16, 1, value);
1743                                         break;
1744
1745                                 case ARMV7M_CONTROL:
1746                                         buf_set_u32((uint8_t *)&reg, 24, 2, value);
1747                                         break;
1748                         }
1749
1750                         cortexm_dap_write_coreregister_u32(target, reg, 20);
1751
1752                         LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1753                         break;
1754
1755                 default:
1756                         return ERROR_COMMAND_SYNTAX_ERROR;
1757         }
1758
1759         return ERROR_OK;
1760 }
1761
1762 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1763         uint32_t size, uint32_t count, uint8_t *buffer)
1764 {
1765         struct armv7m_common *armv7m = target_to_armv7m(target);
1766
1767         if (armv7m->arm.is_armv6m) {
1768                 /* armv6m does not handle unaligned memory access */
1769                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1770                         return ERROR_TARGET_UNALIGNED_ACCESS;
1771         }
1772
1773         return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1774 }
1775
1776 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1777         uint32_t size, uint32_t count, const uint8_t *buffer)
1778 {
1779         struct armv7m_common *armv7m = target_to_armv7m(target);
1780
1781         if (armv7m->arm.is_armv6m) {
1782                 /* armv6m does not handle unaligned memory access */
1783                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1784                         return ERROR_TARGET_UNALIGNED_ACCESS;
1785         }
1786
1787         return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1788 }
1789
1790 static int cortex_m_init_target(struct command_context *cmd_ctx,
1791         struct target *target)
1792 {
1793         armv7m_build_reg_cache(target);
1794         arm_semihosting_init(target);
1795         return ERROR_OK;
1796 }
1797
1798 void cortex_m_deinit_target(struct target *target)
1799 {
1800         struct cortex_m_common *cortex_m = target_to_cm(target);
1801
1802         free(cortex_m->fp_comparator_list);
1803
1804         cortex_m_dwt_free(target);
1805         armv7m_free_reg_cache(target);
1806
1807         free(target->private_config);
1808         free(cortex_m);
1809 }
1810
1811 int cortex_m_profiling(struct target *target, uint32_t *samples,
1812                               uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1813 {
1814         struct timeval timeout, now;
1815         struct armv7m_common *armv7m = target_to_armv7m(target);
1816         uint32_t reg_value;
1817         bool use_pcsr = false;
1818         int retval = ERROR_OK;
1819         struct reg *reg;
1820
1821         gettimeofday(&timeout, NULL);
1822         timeval_add_time(&timeout, seconds, 0);
1823
1824         retval = target_read_u32(target, DWT_PCSR, &reg_value);
1825         if (retval != ERROR_OK) {
1826                 LOG_ERROR("Error while reading PCSR");
1827                 return retval;
1828         }
1829
1830         if (reg_value != 0) {
1831                 use_pcsr = true;
1832                 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1833         } else {
1834                 LOG_INFO("Starting profiling. Halting and resuming the"
1835                          " target as often as we can...");
1836                 reg = register_get_by_name(target->reg_cache, "pc", 1);
1837         }
1838
1839         /* Make sure the target is running */
1840         target_poll(target);
1841         if (target->state == TARGET_HALTED)
1842                 retval = target_resume(target, 1, 0, 0, 0);
1843
1844         if (retval != ERROR_OK) {
1845                 LOG_ERROR("Error while resuming target");
1846                 return retval;
1847         }
1848
1849         uint32_t sample_count = 0;
1850
1851         for (;;) {
1852                 if (use_pcsr) {
1853                         if (armv7m && armv7m->debug_ap) {
1854                                 uint32_t read_count = max_num_samples - sample_count;
1855                                 if (read_count > 1024)
1856                                         read_count = 1024;
1857
1858                                 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1859                                                         (void *)&samples[sample_count],
1860                                                         4, read_count, DWT_PCSR);
1861                                 sample_count += read_count;
1862                         } else {
1863                                 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1864                         }
1865                 } else {
1866                         target_poll(target);
1867                         if (target->state == TARGET_HALTED) {
1868                                 reg_value = buf_get_u32(reg->value, 0, 32);
1869                                 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1870                                 retval = target_resume(target, 1, 0, 0, 0);
1871                                 samples[sample_count++] = reg_value;
1872                                 target_poll(target);
1873                                 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1874                         } else if (target->state == TARGET_RUNNING) {
1875                                 /* We want to quickly sample the PC. */
1876                                 retval = target_halt(target);
1877                         } else {
1878                                 LOG_INFO("Target not halted or running");
1879                                 retval = ERROR_OK;
1880                                 break;
1881                         }
1882                 }
1883
1884                 if (retval != ERROR_OK) {
1885                         LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1886                         return retval;
1887                 }
1888
1889
1890                 gettimeofday(&now, NULL);
1891                 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1892                         LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1893                         break;
1894                 }
1895         }
1896
1897         *num_samples = sample_count;
1898         return retval;
1899 }
1900
1901
1902 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1903  * on r/w if the core is not running, and clear on resume or reset ... or
1904  * at least, in a post_restore_context() method.
1905  */
1906
1907 struct dwt_reg_state {
1908         struct target *target;
1909         uint32_t addr;
1910         uint8_t value[4];               /* scratch/cache */
1911 };
1912
1913 static int cortex_m_dwt_get_reg(struct reg *reg)
1914 {
1915         struct dwt_reg_state *state = reg->arch_info;
1916
1917         uint32_t tmp;
1918         int retval = target_read_u32(state->target, state->addr, &tmp);
1919         if (retval != ERROR_OK)
1920                 return retval;
1921
1922         buf_set_u32(state->value, 0, 32, tmp);
1923         return ERROR_OK;
1924 }
1925
1926 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1927 {
1928         struct dwt_reg_state *state = reg->arch_info;
1929
1930         return target_write_u32(state->target, state->addr,
1931                         buf_get_u32(buf, 0, reg->size));
1932 }
1933
1934 struct dwt_reg {
1935         uint32_t addr;
1936         const char *name;
1937         unsigned size;
1938 };
1939
1940 static const struct dwt_reg dwt_base_regs[] = {
1941         { DWT_CTRL, "dwt_ctrl", 32, },
1942         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1943          * increments while the core is asleep.
1944          */
1945         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1946         /* plus some 8 bit counters, useful for profiling with TPIU */
1947 };
1948
1949 static const struct dwt_reg dwt_comp[] = {
1950 #define DWT_COMPARATOR(i) \
1951                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1952                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1953                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1954         DWT_COMPARATOR(0),
1955         DWT_COMPARATOR(1),
1956         DWT_COMPARATOR(2),
1957         DWT_COMPARATOR(3),
1958         DWT_COMPARATOR(4),
1959         DWT_COMPARATOR(5),
1960         DWT_COMPARATOR(6),
1961         DWT_COMPARATOR(7),
1962         DWT_COMPARATOR(8),
1963         DWT_COMPARATOR(9),
1964         DWT_COMPARATOR(10),
1965         DWT_COMPARATOR(11),
1966         DWT_COMPARATOR(12),
1967         DWT_COMPARATOR(13),
1968         DWT_COMPARATOR(14),
1969         DWT_COMPARATOR(15),
1970 #undef DWT_COMPARATOR
1971 };
1972
1973 static const struct reg_arch_type dwt_reg_type = {
1974         .get = cortex_m_dwt_get_reg,
1975         .set = cortex_m_dwt_set_reg,
1976 };
1977
1978 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1979 {
1980         struct dwt_reg_state *state;
1981
1982         state = calloc(1, sizeof(*state));
1983         if (!state)
1984                 return;
1985         state->addr = d->addr;
1986         state->target = t;
1987
1988         r->name = d->name;
1989         r->size = d->size;
1990         r->value = state->value;
1991         r->arch_info = state;
1992         r->type = &dwt_reg_type;
1993 }
1994
1995 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1996 {
1997         uint32_t dwtcr;
1998         struct reg_cache *cache;
1999         struct cortex_m_dwt_comparator *comparator;
2000         int reg, i;
2001
2002         target_read_u32(target, DWT_CTRL, &dwtcr);
2003         LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
2004         if (!dwtcr) {
2005                 LOG_DEBUG("no DWT");
2006                 return;
2007         }
2008
2009         target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
2010         LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
2011
2012         cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
2013         cm->dwt_comp_available = cm->dwt_num_comp;
2014         cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
2015                         sizeof(struct cortex_m_dwt_comparator));
2016         if (!cm->dwt_comparator_list) {
2017 fail0:
2018                 cm->dwt_num_comp = 0;
2019                 LOG_ERROR("out of mem");
2020                 return;
2021         }
2022
2023         cache = calloc(1, sizeof(*cache));
2024         if (!cache) {
2025 fail1:
2026                 free(cm->dwt_comparator_list);
2027                 goto fail0;
2028         }
2029         cache->name = "Cortex-M DWT registers";
2030         cache->num_regs = 2 + cm->dwt_num_comp * 3;
2031         cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
2032         if (!cache->reg_list) {
2033                 free(cache);
2034                 goto fail1;
2035         }
2036
2037         for (reg = 0; reg < 2; reg++)
2038                 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2039                         dwt_base_regs + reg);
2040
2041         comparator = cm->dwt_comparator_list;
2042         for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
2043                 int j;
2044
2045                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
2046                 for (j = 0; j < 3; j++, reg++)
2047                         cortex_m_dwt_addreg(target, cache->reg_list + reg,
2048                                 dwt_comp + 3 * i + j);
2049
2050                 /* make sure we clear any watchpoints enabled on the target */
2051                 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
2052         }
2053
2054         *register_get_last_cache_p(&target->reg_cache) = cache;
2055         cm->dwt_cache = cache;
2056
2057         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
2058                 dwtcr, cm->dwt_num_comp,
2059                 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
2060
2061         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
2062          * implement single-address data value watchpoints ... so we
2063          * won't need to check it later, when asked to set one up.
2064          */
2065 }
2066
2067 static void cortex_m_dwt_free(struct target *target)
2068 {
2069         struct cortex_m_common *cm = target_to_cm(target);
2070         struct reg_cache *cache = cm->dwt_cache;
2071
2072         free(cm->dwt_comparator_list);
2073         cm->dwt_comparator_list = NULL;
2074         cm->dwt_num_comp = 0;
2075
2076         if (cache) {
2077                 register_unlink_cache(&target->reg_cache, cache);
2078
2079                 if (cache->reg_list) {
2080                         for (size_t i = 0; i < cache->num_regs; i++)
2081                                 free(cache->reg_list[i].arch_info);
2082                         free(cache->reg_list);
2083                 }
2084                 free(cache);
2085         }
2086         cm->dwt_cache = NULL;
2087 }
2088
2089 #define MVFR0 0xe000ef40
2090 #define MVFR1 0xe000ef44
2091
2092 #define MVFR0_DEFAULT_M4 0x10110021
2093 #define MVFR1_DEFAULT_M4 0x11000011
2094
2095 #define MVFR0_DEFAULT_M7_SP 0x10110021
2096 #define MVFR0_DEFAULT_M7_DP 0x10110221
2097 #define MVFR1_DEFAULT_M7_SP 0x11000011
2098 #define MVFR1_DEFAULT_M7_DP 0x12000011
2099
2100 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
2101                 struct adiv5_ap **debug_ap)
2102 {
2103         if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
2104                 return ERROR_OK;
2105
2106         return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
2107 }
2108
2109 int cortex_m_examine(struct target *target)
2110 {
2111         int retval;
2112         uint32_t cpuid, fpcr, mvfr0, mvfr1;
2113         int i;
2114         struct cortex_m_common *cortex_m = target_to_cm(target);
2115         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2116         struct armv7m_common *armv7m = target_to_armv7m(target);
2117
2118         /* stlink shares the examine handler but does not support
2119          * all its calls */
2120         if (!armv7m->stlink) {
2121                 if (cortex_m->apsel == DP_APSEL_INVALID) {
2122                         /* Search for the MEM-AP */
2123                         retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
2124                         if (retval != ERROR_OK) {
2125                                 LOG_ERROR("Could not find MEM-AP to control the core");
2126                                 return retval;
2127                         }
2128                 } else {
2129                         armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2130                 }
2131
2132                 /* Leave (only) generic DAP stuff for debugport_init(); */
2133                 armv7m->debug_ap->memaccess_tck = 8;
2134
2135                 retval = mem_ap_init(armv7m->debug_ap);
2136                 if (retval != ERROR_OK)
2137                         return retval;
2138         }
2139
2140         if (!target_was_examined(target)) {
2141                 target_set_examined(target);
2142
2143                 /* Read from Device Identification Registers */
2144                 retval = target_read_u32(target, CPUID, &cpuid);
2145                 if (retval != ERROR_OK)
2146                         return retval;
2147
2148                 /* Get CPU Type */
2149                 i = (cpuid >> 4) & 0xf;
2150
2151                 switch (cpuid & ARM_CPUID_PARTNO_MASK) {
2152                         case CORTEX_M23_PARTNO:
2153                                 i = 23;
2154                                 break;
2155
2156                         case CORTEX_M33_PARTNO:
2157                                 i = 33;
2158                                 break;
2159
2160                         default:
2161                                 break;
2162                 }
2163
2164
2165                 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2166                                 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2167                 cortex_m->maskints_erratum = false;
2168                 if (i == 7) {
2169                         uint8_t rev, patch;
2170                         rev = (cpuid >> 20) & 0xf;
2171                         patch = (cpuid >> 0) & 0xf;
2172                         if ((rev == 0) && (patch < 2)) {
2173                                 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2174                                 cortex_m->maskints_erratum = true;
2175                         }
2176                 }
2177                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2178
2179                 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2180                 cortex_m->vectreset_supported = i > 1;
2181
2182                 if (i == 4) {
2183                         target_read_u32(target, MVFR0, &mvfr0);
2184                         target_read_u32(target, MVFR1, &mvfr1);
2185
2186                         /* test for floating point feature on Cortex-M4 */
2187                         if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2188                                 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2189                                 armv7m->fp_feature = FPv4_SP;
2190                         }
2191                 } else if (i == 7 || i == 33) {
2192                         target_read_u32(target, MVFR0, &mvfr0);
2193                         target_read_u32(target, MVFR1, &mvfr1);
2194
2195                         /* test for floating point features on Cortex-M7 */
2196                         if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2197                                 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2198                                 armv7m->fp_feature = FPv5_SP;
2199                         } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2200                                 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2201                                 armv7m->fp_feature = FPv5_DP;
2202                         }
2203                 } else if (i == 0) {
2204                         /* Cortex-M0 does not support unaligned memory access */
2205                         armv7m->arm.is_armv6m = true;
2206                 }
2207
2208                 if (armv7m->fp_feature == FP_NONE &&
2209                     armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2210                         /* free unavailable FPU registers */
2211                         size_t idx;
2212
2213                         for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2214                              idx < armv7m->arm.core_cache->num_regs;
2215                              idx++) {
2216                                 free(armv7m->arm.core_cache->reg_list[idx].value);
2217                                 free(armv7m->arm.core_cache->reg_list[idx].feature);
2218                                 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2219                         }
2220                         armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2221                 }
2222
2223                 if (!armv7m->stlink) {
2224                         if (i == 3 || i == 4)
2225                                 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2226                                  * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2227                                 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2228                         else if (i == 7)
2229                                 /* Cortex-M7 has only 1024 bytes autoincrement range */
2230                                 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2231                 }
2232
2233                 /* Configure trace modules */
2234                 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2235                 if (retval != ERROR_OK)
2236                         return retval;
2237
2238                 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2239                         armv7m_trace_tpiu_config(target);
2240                         armv7m_trace_itm_config(target);
2241                 }
2242
2243                 /* NOTE: FPB and DWT are both optional. */
2244
2245                 /* Setup FPB */
2246                 target_read_u32(target, FP_CTRL, &fpcr);
2247                 /* bits [14:12] and [7:4] */
2248                 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2249                 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2250                 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2251                    Revision is zero base, fp_rev == 1 means Rev.2 ! */
2252                 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2253                 free(cortex_m->fp_comparator_list);
2254                 cortex_m->fp_comparator_list = calloc(
2255                                 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2256                                 sizeof(struct cortex_m_fp_comparator));
2257                 cortex_m->fpb_enabled = fpcr & 1;
2258                 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2259                         cortex_m->fp_comparator_list[i].type =
2260                                 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2261                         cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2262
2263                         /* make sure we clear any breakpoints enabled on the target */
2264                         target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2265                 }
2266                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2267                         fpcr,
2268                         cortex_m->fp_num_code,
2269                         cortex_m->fp_num_lit);
2270
2271                 /* Setup DWT */
2272                 cortex_m_dwt_free(target);
2273                 cortex_m_dwt_setup(cortex_m, target);
2274
2275                 /* These hardware breakpoints only work for code in flash! */
2276                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2277                         target_name(target),
2278                         cortex_m->fp_num_code,
2279                         cortex_m->dwt_num_comp);
2280         }
2281
2282         return ERROR_OK;
2283 }
2284
2285 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2286 {
2287         struct armv7m_common *armv7m = target_to_armv7m(target);
2288         uint16_t dcrdr;
2289         uint8_t buf[2];
2290         int retval;
2291
2292         retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2293         if (retval != ERROR_OK)
2294                 return retval;
2295
2296         dcrdr = target_buffer_get_u16(target, buf);
2297         *ctrl = (uint8_t)dcrdr;
2298         *value = (uint8_t)(dcrdr >> 8);
2299
2300         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2301
2302         /* write ack back to software dcc register
2303          * signify we have read data */
2304         if (dcrdr & (1 << 0)) {
2305                 target_buffer_set_u16(target, buf, 0);
2306                 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2307                 if (retval != ERROR_OK)
2308                         return retval;
2309         }
2310
2311         return ERROR_OK;
2312 }
2313
2314 static int cortex_m_target_request_data(struct target *target,
2315         uint32_t size, uint8_t *buffer)
2316 {
2317         uint8_t data;
2318         uint8_t ctrl;
2319         uint32_t i;
2320
2321         for (i = 0; i < (size * 4); i++) {
2322                 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2323                 if (retval != ERROR_OK)
2324                         return retval;
2325                 buffer[i] = data;
2326         }
2327
2328         return ERROR_OK;
2329 }
2330
2331 static int cortex_m_handle_target_request(void *priv)
2332 {
2333         struct target *target = priv;
2334         if (!target_was_examined(target))
2335                 return ERROR_OK;
2336
2337         if (!target->dbg_msg_enabled)
2338                 return ERROR_OK;
2339
2340         if (target->state == TARGET_RUNNING) {
2341                 uint8_t data;
2342                 uint8_t ctrl;
2343                 int retval;
2344
2345                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2346                 if (retval != ERROR_OK)
2347                         return retval;
2348
2349                 /* check if we have data */
2350                 if (ctrl & (1 << 0)) {
2351                         uint32_t request;
2352
2353                         /* we assume target is quick enough */
2354                         request = data;
2355                         for (int i = 1; i <= 3; i++) {
2356                                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2357                                 if (retval != ERROR_OK)
2358                                         return retval;
2359                                 request |= ((uint32_t)data << (i * 8));
2360                         }
2361                         target_request(target, request);
2362                 }
2363         }
2364
2365         return ERROR_OK;
2366 }
2367
2368 static int cortex_m_init_arch_info(struct target *target,
2369         struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2370 {
2371         struct armv7m_common *armv7m = &cortex_m->armv7m;
2372
2373         armv7m_init_arch_info(target, armv7m);
2374
2375         /* default reset mode is to use srst if fitted
2376          * if not it will use CORTEX_M3_RESET_VECTRESET */
2377         cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2378
2379         armv7m->arm.dap = dap;
2380
2381         /* register arch-specific functions */
2382         armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2383
2384         armv7m->post_debug_entry = NULL;
2385
2386         armv7m->pre_restore_context = NULL;
2387
2388         armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2389         armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2390
2391         target_register_timer_callback(cortex_m_handle_target_request, 1,
2392                 TARGET_TIMER_TYPE_PERIODIC, target);
2393
2394         return ERROR_OK;
2395 }
2396
2397 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2398 {
2399         struct adiv5_private_config *pc;
2400
2401         pc = (struct adiv5_private_config *)target->private_config;
2402         if (adiv5_verify_config(pc) != ERROR_OK)
2403                 return ERROR_FAIL;
2404
2405         struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2406         if (cortex_m == NULL) {
2407                 LOG_ERROR("No memory creating target");
2408                 return ERROR_FAIL;
2409         }
2410
2411         cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2412         cortex_m->apsel = pc->ap_num;
2413
2414         cortex_m_init_arch_info(target, cortex_m, pc->dap);
2415
2416         return ERROR_OK;
2417 }
2418
2419 /*--------------------------------------------------------------------------*/
2420
2421 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2422         struct cortex_m_common *cm)
2423 {
2424         if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2425                 command_print(cmd, "target is not a Cortex-M");
2426                 return ERROR_TARGET_INVALID;
2427         }
2428         return ERROR_OK;
2429 }
2430
2431 /*
2432  * Only stuff below this line should need to verify that its target
2433  * is a Cortex-M3.  Everything else should have indirected through the
2434  * cortexm3_target structure, which is only used with CM3 targets.
2435  */
2436
2437 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2438 {
2439         struct target *target = get_current_target(CMD_CTX);
2440         struct cortex_m_common *cortex_m = target_to_cm(target);
2441         struct armv7m_common *armv7m = &cortex_m->armv7m;
2442         uint32_t demcr = 0;
2443         int retval;
2444
2445         static const struct {
2446                 char name[10];
2447                 unsigned mask;
2448         } vec_ids[] = {
2449                 { "hard_err",   VC_HARDERR, },
2450                 { "int_err",    VC_INTERR, },
2451                 { "bus_err",    VC_BUSERR, },
2452                 { "state_err",  VC_STATERR, },
2453                 { "chk_err",    VC_CHKERR, },
2454                 { "nocp_err",   VC_NOCPERR, },
2455                 { "mm_err",     VC_MMERR, },
2456                 { "reset",      VC_CORERESET, },
2457         };
2458
2459         retval = cortex_m_verify_pointer(CMD, cortex_m);
2460         if (retval != ERROR_OK)
2461                 return retval;
2462
2463         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2464         if (retval != ERROR_OK)
2465                 return retval;
2466
2467         if (CMD_ARGC > 0) {
2468                 unsigned catch = 0;
2469
2470                 if (CMD_ARGC == 1) {
2471                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2472                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2473                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2474                                         | VC_MMERR | VC_CORERESET;
2475                                 goto write;
2476                         } else if (strcmp(CMD_ARGV[0], "none") == 0)
2477                                 goto write;
2478                 }
2479                 while (CMD_ARGC-- > 0) {
2480                         unsigned i;
2481                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2482                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2483                                         continue;
2484                                 catch |= vec_ids[i].mask;
2485                                 break;
2486                         }
2487                         if (i == ARRAY_SIZE(vec_ids)) {
2488                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2489                                 return ERROR_COMMAND_SYNTAX_ERROR;
2490                         }
2491                 }
2492 write:
2493                 /* For now, armv7m->demcr only stores vector catch flags. */
2494                 armv7m->demcr = catch;
2495
2496                 demcr &= ~0xffff;
2497                 demcr |= catch;
2498
2499                 /* write, but don't assume it stuck (why not??) */
2500                 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2501                 if (retval != ERROR_OK)
2502                         return retval;
2503                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2504                 if (retval != ERROR_OK)
2505                         return retval;
2506
2507                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2508                  * Otherwise the vector catch hardware could fire when there's
2509                  * no debugger hooked up, causing much confusion...
2510                  */
2511         }
2512
2513         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2514                 command_print(CMD, "%9s: %s", vec_ids[i].name,
2515                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2516         }
2517
2518         return ERROR_OK;
2519 }
2520
2521 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2522 {
2523         struct target *target = get_current_target(CMD_CTX);
2524         struct cortex_m_common *cortex_m = target_to_cm(target);
2525         int retval;
2526
2527         static const Jim_Nvp nvp_maskisr_modes[] = {
2528                 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2529                 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2530                 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2531                 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2532                 { .name = NULL, .value = -1 },
2533         };
2534         const Jim_Nvp *n;
2535
2536
2537         retval = cortex_m_verify_pointer(CMD, cortex_m);
2538         if (retval != ERROR_OK)
2539                 return retval;
2540
2541         if (target->state != TARGET_HALTED) {
2542                 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2543                 return ERROR_OK;
2544         }
2545
2546         if (CMD_ARGC > 0) {
2547                 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2548                 if (n->name == NULL)
2549                         return ERROR_COMMAND_SYNTAX_ERROR;
2550                 cortex_m->isrmasking_mode = n->value;
2551                 cortex_m_set_maskints_for_halt(target);
2552         }
2553
2554         n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2555         command_print(CMD, "cortex_m interrupt mask %s", n->name);
2556
2557         return ERROR_OK;
2558 }
2559
2560 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2561 {
2562         struct target *target = get_current_target(CMD_CTX);
2563         struct cortex_m_common *cortex_m = target_to_cm(target);
2564         int retval;
2565         char *reset_config;
2566
2567         retval = cortex_m_verify_pointer(CMD, cortex_m);
2568         if (retval != ERROR_OK)
2569                 return retval;
2570
2571         if (CMD_ARGC > 0) {
2572                 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2573                         cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2574
2575                 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2576                         if (target_was_examined(target)
2577                                         && !cortex_m->vectreset_supported)
2578                                 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2579                         else
2580                                 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2581
2582                 } else
2583                         return ERROR_COMMAND_SYNTAX_ERROR;
2584         }
2585
2586         switch (cortex_m->soft_reset_config) {
2587                 case CORTEX_M_RESET_SYSRESETREQ:
2588                         reset_config = "sysresetreq";
2589                         break;
2590
2591                 case CORTEX_M_RESET_VECTRESET:
2592                         reset_config = "vectreset";
2593                         break;
2594
2595                 default:
2596                         reset_config = "unknown";
2597                         break;
2598         }
2599
2600         command_print(CMD, "cortex_m reset_config %s", reset_config);
2601
2602         return ERROR_OK;
2603 }
2604
2605 static const struct command_registration cortex_m_exec_command_handlers[] = {
2606         {
2607                 .name = "maskisr",
2608                 .handler = handle_cortex_m_mask_interrupts_command,
2609                 .mode = COMMAND_EXEC,
2610                 .help = "mask cortex_m interrupts",
2611                 .usage = "['auto'|'on'|'off'|'steponly']",
2612         },
2613         {
2614                 .name = "vector_catch",
2615                 .handler = handle_cortex_m_vector_catch_command,
2616                 .mode = COMMAND_EXEC,
2617                 .help = "configure hardware vectors to trigger debug entry",
2618                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2619         },
2620         {
2621                 .name = "reset_config",
2622                 .handler = handle_cortex_m_reset_config_command,
2623                 .mode = COMMAND_ANY,
2624                 .help = "configure software reset handling",
2625                 .usage = "['sysresetreq'|'vectreset']",
2626         },
2627         COMMAND_REGISTRATION_DONE
2628 };
2629 static const struct command_registration cortex_m_command_handlers[] = {
2630         {
2631                 .chain = armv7m_command_handlers,
2632         },
2633         {
2634                 .chain = armv7m_trace_command_handlers,
2635         },
2636         {
2637                 .name = "cortex_m",
2638                 .mode = COMMAND_EXEC,
2639                 .help = "Cortex-M command group",
2640                 .usage = "",
2641                 .chain = cortex_m_exec_command_handlers,
2642         },
2643         COMMAND_REGISTRATION_DONE
2644 };
2645
2646 struct target_type cortexm_target = {
2647         .name = "cortex_m",
2648         .deprecated_name = "cortex_m3",
2649
2650         .poll = cortex_m_poll,
2651         .arch_state = armv7m_arch_state,
2652
2653         .target_request_data = cortex_m_target_request_data,
2654
2655         .halt = cortex_m_halt,
2656         .resume = cortex_m_resume,
2657         .step = cortex_m_step,
2658
2659         .assert_reset = cortex_m_assert_reset,
2660         .deassert_reset = cortex_m_deassert_reset,
2661         .soft_reset_halt = cortex_m_soft_reset_halt,
2662
2663         .get_gdb_arch = arm_get_gdb_arch,
2664         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2665
2666         .read_memory = cortex_m_read_memory,
2667         .write_memory = cortex_m_write_memory,
2668         .checksum_memory = armv7m_checksum_memory,
2669         .blank_check_memory = armv7m_blank_check_memory,
2670
2671         .run_algorithm = armv7m_run_algorithm,
2672         .start_algorithm = armv7m_start_algorithm,
2673         .wait_algorithm = armv7m_wait_algorithm,
2674
2675         .add_breakpoint = cortex_m_add_breakpoint,
2676         .remove_breakpoint = cortex_m_remove_breakpoint,
2677         .add_watchpoint = cortex_m_add_watchpoint,
2678         .remove_watchpoint = cortex_m_remove_watchpoint,
2679
2680         .commands = cortex_m_command_handlers,
2681         .target_create = cortex_m_target_create,
2682         .target_jim_configure = adiv5_jim_configure,
2683         .init_target = cortex_m_init_target,
2684         .examine = cortex_m_examine,
2685         .deinit_target = cortex_m_deinit_target,
2686
2687         .profiling = cortex_m_profiling,
2688 };