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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  *                                                                         *
  24  *                                                                         *
  25  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  26  *                                                                         *
  27  ***************************************************************************/
  28 #ifdef HAVE_CONFIG_H
  29 #include "config.h"
  30 #endif
  31
  32 #include "jtag/interface.h"
  33 #include "breakpoints.h"
  34 #include "cortex_m.h"
  35 #include "target_request.h"
  36 #include "target_type.h"
  37 #include "arm_disassembler.h"
  38 #include "register.h"
  39 #include "arm_opcodes.h"
  40 #include "arm_semihosting.h"
  41 #include <helper/time_support.h>
  42
  43 /* NOTE:  most of this should work fine for the Cortex-M1 and
  44  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  45  * Some differences:  M0/M1 doesn't have FPB remapping or the
  46  * DWT tracing/profiling support.  (So the cycle counter will
  47  * not be usable; the other stuff isn't currently used here.)
  48  *
  49  * Although there are some workarounds for errata seen only in r0p0
  50  * silicon, such old parts are hard to find and thus not much tested
  51  * any longer.
  52  */
  53
  54 /* forward declarations */
  55 static int cortex_m_store_core_reg_u32(struct target *target,
  56                 uint32_t num, uint32_t value);
  57 static void cortex_m_dwt_free(struct target *target);
  58
  59 static int cortexm_dap_read_coreregister_u32(struct target *target,
  60         uint32_t *value, int regnum)
  61 {
  62         struct armv7m_common *armv7m = target_to_armv7m(target);
  63         int retval;
  64         uint32_t dcrdr;
  65
  66         /* because the DCB_DCRDR is used for the emulated dcc channel
  67          * we have to save/restore the DCB_DCRDR when used */
  68         if (target->dbg_msg_enabled) {
  69                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
  70                 if (retval != ERROR_OK)
  71                         return retval;
  72         }
  73
  74         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
  75         if (retval != ERROR_OK)
  76                 return retval;
  77
  78         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
  79         if (retval != ERROR_OK)
  80                 return retval;
  81
  82         if (target->dbg_msg_enabled) {
  83                 /* restore DCB_DCRDR - this needs to be in a separate
  84                  * transaction otherwise the emulated DCC channel breaks */
  85                 if (retval == ERROR_OK)
  86                         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
  87         }
  88
  89         return retval;
  90 }
  91
  92 static int cortexm_dap_write_coreregister_u32(struct target *target,
  93         uint32_t value, int regnum)
  94 {
  95         struct armv7m_common *armv7m = target_to_armv7m(target);
  96         int retval;
  97         uint32_t dcrdr;
  98
  99         /* because the DCB_DCRDR is used for the emulated dcc channel
 100          * we have to save/restore the DCB_DCRDR when used */
 101         if (target->dbg_msg_enabled) {
 102                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
 103                 if (retval != ERROR_OK)
 104                         return retval;
 105         }
 106
 107         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
 108         if (retval != ERROR_OK)
 109                 return retval;
 110
 111         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
 112         if (retval != ERROR_OK)
 113                 return retval;
 114
 115         if (target->dbg_msg_enabled) {
 116                 /* restore DCB_DCRDR - this needs to be in a seperate
 117                  * transaction otherwise the emulated DCC channel breaks */
 118                 if (retval == ERROR_OK)
 119                         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
 120         }
 121
 122         return retval;
 123 }
 124
 125 static int cortex_m_write_debug_halt_mask(struct target *target,
 126         uint32_t mask_on, uint32_t mask_off)
 127 {
 128         struct cortex_m_common *cortex_m = target_to_cm(target);
 129         struct armv7m_common *armv7m = &cortex_m->armv7m;
 130
 131         /* mask off status bits */
 132         cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 133         /* create new register mask */
 134         cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 135
 136         return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
 137 }
 138
 139 static int cortex_m_clear_halt(struct target *target)
 140 {
 141         struct cortex_m_common *cortex_m = target_to_cm(target);
 142         struct armv7m_common *armv7m = &cortex_m->armv7m;
 143         int retval;
 144
 145         /* clear step if any */
 146         cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
 147
 148         /* Read Debug Fault Status Register */
 149         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
 150         if (retval != ERROR_OK)
 151                 return retval;
 152
 153         /* Clear Debug Fault Status */
 154         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
 155         if (retval != ERROR_OK)
 156                 return retval;
 157         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
 158
 159         return ERROR_OK;
 160 }
 161
 162 static int cortex_m_single_step_core(struct target *target)
 163 {
 164         struct cortex_m_common *cortex_m = target_to_cm(target);
 165         struct armv7m_common *armv7m = &cortex_m->armv7m;
 166         int retval;
 167
 168         /* Mask interrupts before clearing halt, if not done already.  This avoids
 169          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 170          * HALT can put the core into an unknown state.
 171          */
 172         if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
 173                 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
 174                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 175                 if (retval != ERROR_OK)
 176                         return retval;
 177         }
 178         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
 179                         DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 180         if (retval != ERROR_OK)
 181                 return retval;
 182         LOG_DEBUG(" ");
 183
 184         /* restore dhcsr reg */
 185         cortex_m_clear_halt(target);
 186
 187         return ERROR_OK;
 188 }
 189
 190 static int cortex_m_enable_fpb(struct target *target)
 191 {
 192         int retval = target_write_u32(target, FP_CTRL, 3);
 193         if (retval != ERROR_OK)
 194                 return retval;
 195
 196         /* check the fpb is actually enabled */
 197         uint32_t fpctrl;
 198         retval = target_read_u32(target, FP_CTRL, &fpctrl);
 199         if (retval != ERROR_OK)
 200                 return retval;
 201
 202         if (fpctrl & 1)
 203                 return ERROR_OK;
 204
 205         return ERROR_FAIL;
 206 }
 207
 208 static int cortex_m_endreset_event(struct target *target)
 209 {
 210         int i;
 211         int retval;
 212         uint32_t dcb_demcr;
 213         struct cortex_m_common *cortex_m = target_to_cm(target);
 214         struct armv7m_common *armv7m = &cortex_m->armv7m;
 215         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 216         struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
 217         struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
 218
 219         /* REVISIT The four debug monitor bits are currently ignored... */
 220         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
 221         if (retval != ERROR_OK)
 222                 return retval;
 223         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
 224
 225         /* this register is used for emulated dcc channel */
 226         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
 227         if (retval != ERROR_OK)
 228                 return retval;
 229
 230         /* Enable debug requests */
 231         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 232         if (retval != ERROR_OK)
 233                 return retval;
 234         if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
 235                 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
 236                 if (retval != ERROR_OK)
 237                         return retval;
 238         }
 239
 240         /* Restore proper interrupt masking setting. */
 241         if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
 242                 cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
 243         else
 244                 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
 245
 246         /* Enable features controlled by ITM and DWT blocks, and catch only
 247          * the vectors we were told to pay attention to.
 248          *
 249          * Target firmware is responsible for all fault handling policy
 250          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 251          * or manual updates to the NVIC SHCSR and CCR registers.
 252          */
 253         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
 254         if (retval != ERROR_OK)
 255                 return retval;
 256
 257         /* Paranoia: evidently some (early?) chips don't preserve all the
 258          * debug state (including FPB, DWT, etc) across reset...
 259          */
 260
 261         /* Enable FPB */
 262         retval = cortex_m_enable_fpb(target);
 263         if (retval != ERROR_OK) {
 264                 LOG_ERROR("Failed to enable the FPB");
 265                 return retval;
 266         }
 267
 268         cortex_m->fpb_enabled = true;
 269
 270         /* Restore FPB registers */
 271         for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
 272                 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 273                 if (retval != ERROR_OK)
 274                         return retval;
 275         }
 276
 277         /* Restore DWT registers */
 278         for (i = 0; i < cortex_m->dwt_num_comp; i++) {
 279                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 280                                 dwt_list[i].comp);
 281                 if (retval != ERROR_OK)
 282                         return retval;
 283                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 284                                 dwt_list[i].mask);
 285                 if (retval != ERROR_OK)
 286                         return retval;
 287                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 288                                 dwt_list[i].function);
 289                 if (retval != ERROR_OK)
 290                         return retval;
 291         }
 292         retval = dap_run(swjdp);
 293         if (retval != ERROR_OK)
 294                 return retval;
 295
 296         register_cache_invalidate(armv7m->arm.core_cache);
 297
 298         /* make sure we have latest dhcsr flags */
 299         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 300
 301         return retval;
 302 }
 303
 304 static int cortex_m_examine_debug_reason(struct target *target)
 305 {
 306         struct cortex_m_common *cortex_m = target_to_cm(target);
 307
 308         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
 309          * only check the debug reason if we don't know it already */
 310
 311         if ((target->debug_reason != DBG_REASON_DBGRQ)
 312                 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
 313                 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
 314                         target->debug_reason = DBG_REASON_BREAKPOINT;
 315                         if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 316                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 317                 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 318                         target->debug_reason = DBG_REASON_WATCHPOINT;
 319                 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
 320                         target->debug_reason = DBG_REASON_BREAKPOINT;
 321                 else    /* EXTERNAL, HALTED */
 322                         target->debug_reason = DBG_REASON_UNDEFINED;
 323         }
 324
 325         return ERROR_OK;
 326 }
 327
 328 static int cortex_m_examine_exception_reason(struct target *target)
 329 {
 330         uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
 331         struct armv7m_common *armv7m = target_to_armv7m(target);
 332         struct adiv5_dap *swjdp = armv7m->arm.dap;
 333         int retval;
 334
 335         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
 336         if (retval != ERROR_OK)
 337                 return retval;
 338         switch (armv7m->exception_number) {
 339                 case 2: /* NMI */
 340                         break;
 341                 case 3: /* Hard Fault */
 342                         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
 343                         if (retval != ERROR_OK)
 344                                 return retval;
 345                         if (except_sr & 0x40000000) {
 346                                 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
 347                                 if (retval != ERROR_OK)
 348                                         return retval;
 349                         }
 350                         break;
 351                 case 4: /* Memory Management */
 352                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 353                         if (retval != ERROR_OK)
 354                                 return retval;
 355                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
 356                         if (retval != ERROR_OK)
 357                                 return retval;
 358                         break;
 359                 case 5: /* Bus Fault */
 360                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 361                         if (retval != ERROR_OK)
 362                                 return retval;
 363                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
 364                         if (retval != ERROR_OK)
 365                                 return retval;
 366                         break;
 367                 case 6: /* Usage Fault */
 368                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 369                         if (retval != ERROR_OK)
 370                                 return retval;
 371                         break;
 372                 case 11:        /* SVCall */
 373                         break;
 374                 case 12:        /* Debug Monitor */
 375                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
 376                         if (retval != ERROR_OK)
 377                                 return retval;
 378                         break;
 379                 case 14:        /* PendSV */
 380                         break;
 381                 case 15:        /* SysTick */
 382                         break;
 383                 default:
 384                         except_sr = 0;
 385                         break;
 386         }
 387         retval = dap_run(swjdp);
 388         if (retval == ERROR_OK)
 389                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 390                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 391                         armv7m_exception_string(armv7m->exception_number),
 392                         shcsr, except_sr, cfsr, except_ar);
 393         return retval;
 394 }
 395
 396 static int cortex_m_debug_entry(struct target *target)
 397 {
 398         int i;
 399         uint32_t xPSR;
 400         int retval;
 401         struct cortex_m_common *cortex_m = target_to_cm(target);
 402         struct armv7m_common *armv7m = &cortex_m->armv7m;
 403         struct arm *arm = &armv7m->arm;
 404         struct reg *r;
 405
 406         LOG_DEBUG(" ");
 407
 408         cortex_m_clear_halt(target);
 409         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 410         if (retval != ERROR_OK)
 411                 return retval;
 412
 413         retval = armv7m->examine_debug_reason(target);
 414         if (retval != ERROR_OK)
 415                 return retval;
 416
 417         /* Examine target state and mode
 418          * First load register accessible through core debug port */
 419         int num_regs = arm->core_cache->num_regs;
 420
 421         for (i = 0; i < num_regs; i++) {
 422                 r = &armv7m->arm.core_cache->reg_list[i];
 423                 if (!r->valid)
 424                         arm->read_core_reg(target, r, i, ARM_MODE_ANY);
 425         }
 426
 427         r = arm->cpsr;
 428         xPSR = buf_get_u32(r->value, 0, 32);
 429
 430         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 431         if (xPSR & 0xf00) {
 432                 r->dirty = r->valid;
 433                 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
 434         }
 435
 436         /* Are we in an exception handler */
 437         if (xPSR & 0x1FF) {
 438                 armv7m->exception_number = (xPSR & 0x1FF);
 439
 440                 arm->core_mode = ARM_MODE_HANDLER;
 441                 arm->map = armv7m_msp_reg_map;
 442         } else {
 443                 unsigned control = buf_get_u32(arm->core_cache
 444                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 445
 446                 /* is this thread privileged? */
 447                 arm->core_mode = control & 1
 448                         ? ARM_MODE_USER_THREAD
 449                         : ARM_MODE_THREAD;
 450
 451                 /* which stack is it using? */
 452                 if (control & 2)
 453                         arm->map = armv7m_psp_reg_map;
 454                 else
 455                         arm->map = armv7m_msp_reg_map;
 456
 457                 armv7m->exception_number = 0;
 458         }
 459
 460         if (armv7m->exception_number)
 461                 cortex_m_examine_exception_reason(target);
 462
 463         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 464                 arm_mode_name(arm->core_mode),
 465                 buf_get_u32(arm->pc->value, 0, 32),
 466                 target_state_name(target));
 467
 468         if (armv7m->post_debug_entry) {
 469                 retval = armv7m->post_debug_entry(target);
 470                 if (retval != ERROR_OK)
 471                         return retval;
 472         }
 473
 474         return ERROR_OK;
 475 }
 476
 477 static int cortex_m_poll(struct target *target)
 478 {
 479         int detected_failure = ERROR_OK;
 480         int retval = ERROR_OK;
 481         enum target_state prev_target_state = target->state;
 482         struct cortex_m_common *cortex_m = target_to_cm(target);
 483         struct armv7m_common *armv7m = &cortex_m->armv7m;
 484
 485         /* Read from Debug Halting Control and Status Register */
 486         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 487         if (retval != ERROR_OK) {
 488                 target->state = TARGET_UNKNOWN;
 489                 return retval;
 490         }
 491
 492         /* Recover from lockup.  See ARMv7-M architecture spec,
 493          * section B1.5.15 "Unrecoverable exception cases".
 494          */
 495         if (cortex_m->dcb_dhcsr & S_LOCKUP) {
 496                 LOG_ERROR("%s -- clearing lockup after double fault",
 497                         target_name(target));
 498                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 499                 target->debug_reason = DBG_REASON_DBGRQ;
 500
 501                 /* We have to execute the rest (the "finally" equivalent, but
 502                  * still throw this exception again).
 503                  */
 504                 detected_failure = ERROR_FAIL;
 505
 506                 /* refresh status bits */
 507                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 508                 if (retval != ERROR_OK)
 509                         return retval;
 510         }
 511
 512         if (cortex_m->dcb_dhcsr & S_RESET_ST) {
 513                 if (target->state != TARGET_RESET) {
 514                         target->state = TARGET_RESET;
 515                         LOG_INFO("%s: external reset detected", target_name(target));
 516                 }
 517                 return ERROR_OK;
 518         }
 519
 520         if (target->state == TARGET_RESET) {
 521                 /* Cannot switch context while running so endreset is
 522                  * called with target->state == TARGET_RESET
 523                  */
 524                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 525                         cortex_m->dcb_dhcsr);
 526                 retval = cortex_m_endreset_event(target);
 527                 if (retval != ERROR_OK) {
 528                         target->state = TARGET_UNKNOWN;
 529                         return retval;
 530                 }
 531                 target->state = TARGET_RUNNING;
 532                 prev_target_state = TARGET_RUNNING;
 533         }
 534
 535         if (cortex_m->dcb_dhcsr & S_HALT) {
 536                 target->state = TARGET_HALTED;
 537
 538                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
 539                         retval = cortex_m_debug_entry(target);
 540                         if (retval != ERROR_OK)
 541                                 return retval;
 542
 543                         if (arm_semihosting(target, &retval) != 0)
 544                                 return retval;
 545
 546                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 547                 }
 548                 if (prev_target_state == TARGET_DEBUG_RUNNING) {
 549                         LOG_DEBUG(" ");
 550                         retval = cortex_m_debug_entry(target);
 551                         if (retval != ERROR_OK)
 552                                 return retval;
 553
 554                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 555                 }
 556         }
 557
 558         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 559          * How best to model low power modes?
 560          */
 561
 562         if (target->state == TARGET_UNKNOWN) {
 563                 /* check if processor is retiring instructions */
 564                 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
 565                         target->state = TARGET_RUNNING;
 566                         retval = ERROR_OK;
 567                 }
 568         }
 569
 570         /* Check that target is truly halted, since the target could be resumed externally */
 571         if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
 572                 /* registers are now invalid */
 573                 register_cache_invalidate(armv7m->arm.core_cache);
 574
 575                 target->state = TARGET_RUNNING;
 576                 LOG_WARNING("%s: external resume detected", target_name(target));
 577                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 578                 retval = ERROR_OK;
 579         }
 580
 581         /* Did we detect a failure condition that we cleared? */
 582         if (detected_failure != ERROR_OK)
 583                 retval = detected_failure;
 584         return retval;
 585 }
 586
 587 static int cortex_m_halt(struct target *target)
 588 {
 589         LOG_DEBUG("target->state: %s",
 590                 target_state_name(target));
 591
 592         if (target->state == TARGET_HALTED) {
 593                 LOG_DEBUG("target was already halted");
 594                 return ERROR_OK;
 595         }
 596
 597         if (target->state == TARGET_UNKNOWN)
 598                 LOG_WARNING("target was in unknown state when halt was requested");
 599
 600         if (target->state == TARGET_RESET) {
 601                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 602                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 603                         return ERROR_TARGET_FAILURE;
 604                 } else {
 605                         /* we came here in a reset_halt or reset_init sequence
 606                          * debug entry was already prepared in cortex_m3_assert_reset()
 607                          */
 608                         target->debug_reason = DBG_REASON_DBGRQ;
 609
 610                         return ERROR_OK;
 611                 }
 612         }
 613
 614         /* Write to Debug Halting Control and Status Register */
 615         cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 616
 617         target->debug_reason = DBG_REASON_DBGRQ;
 618
 619         return ERROR_OK;
 620 }
 621
 622 static int cortex_m_soft_reset_halt(struct target *target)
 623 {
 624         struct cortex_m_common *cortex_m = target_to_cm(target);
 625         struct armv7m_common *armv7m = &cortex_m->armv7m;
 626         uint32_t dcb_dhcsr = 0;
 627         int retval, timeout = 0;
 628
 629         /* soft_reset_halt is deprecated on cortex_m as the same functionality
 630          * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
 631          * As this reset only used VC_CORERESET it would only ever reset the cortex_m
 632          * core, not the peripherals */
 633         LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
 634
 635         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 636         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
 637                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 638         if (retval != ERROR_OK)
 639                 return retval;
 640
 641         /* Request a core-only reset */
 642         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
 643                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 644         if (retval != ERROR_OK)
 645                 return retval;
 646         target->state = TARGET_RESET;
 647
 648         /* registers are now invalid */
 649         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 650
 651         while (timeout < 100) {
 652                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
 653                 if (retval == ERROR_OK) {
 654                         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
 655                                         &cortex_m->nvic_dfsr);
 656                         if (retval != ERROR_OK)
 657                                 return retval;
 658                         if ((dcb_dhcsr & S_HALT)
 659                                 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
 660                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 661                                         "DFSR 0x%08x",
 662                                         (unsigned) dcb_dhcsr,
 663                                         (unsigned) cortex_m->nvic_dfsr);
 664                                 cortex_m_poll(target);
 665                                 /* FIXME restore user's vector catch config */
 666                                 return ERROR_OK;
 667                         } else
 668                                 LOG_DEBUG("waiting for system reset-halt, "
 669                                         "DHCSR 0x%08x, %d ms",
 670                                         (unsigned) dcb_dhcsr, timeout);
 671                 }
 672                 timeout++;
 673                 alive_sleep(1);
 674         }
 675
 676         return ERROR_OK;
 677 }
 678
 679 void cortex_m_enable_breakpoints(struct target *target)
 680 {
 681         struct breakpoint *breakpoint = target->breakpoints;
 682
 683         /* set any pending breakpoints */
 684         while (breakpoint) {
 685                 if (!breakpoint->set)
 686                         cortex_m_set_breakpoint(target, breakpoint);
 687                 breakpoint = breakpoint->next;
 688         }
 689 }
 690
 691 static int cortex_m_resume(struct target *target, int current,
 692         target_addr_t address, int handle_breakpoints, int debug_execution)
 693 {
 694         struct armv7m_common *armv7m = target_to_armv7m(target);
 695         struct breakpoint *breakpoint = NULL;
 696         uint32_t resume_pc;
 697         struct reg *r;
 698
 699         if (target->state != TARGET_HALTED) {
 700                 LOG_WARNING("target not halted");
 701                 return ERROR_TARGET_NOT_HALTED;
 702         }
 703
 704         if (!debug_execution) {
 705                 target_free_all_working_areas(target);
 706                 cortex_m_enable_breakpoints(target);
 707                 cortex_m_enable_watchpoints(target);
 708         }
 709
 710         if (debug_execution) {
 711                 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
 712
 713                 /* Disable interrupts */
 714                 /* We disable interrupts in the PRIMASK register instead of
 715                  * masking with C_MASKINTS.  This is probably the same issue
 716                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 717                  * in parallel with disabled interrupts can cause local faults
 718                  * to not be taken.
 719                  *
 720                  * REVISIT this clearly breaks non-debug execution, since the
 721                  * PRIMASK register state isn't saved/restored...  workaround
 722                  * by never resuming app code after debug execution.
 723                  */
 724                 buf_set_u32(r->value, 0, 1, 1);
 725                 r->dirty = true;
 726                 r->valid = true;
 727
 728                 /* Make sure we are in Thumb mode */
 729                 r = armv7m->arm.cpsr;
 730                 buf_set_u32(r->value, 24, 1, 1);
 731                 r->dirty = true;
 732                 r->valid = true;
 733         }
 734
 735         /* current = 1: continue on current pc, otherwise continue at <address> */
 736         r = armv7m->arm.pc;
 737         if (!current) {
 738                 buf_set_u32(r->value, 0, 32, address);
 739                 r->dirty = true;
 740                 r->valid = true;
 741         }
 742
 743         /* if we halted last time due to a bkpt instruction
 744          * then we have to manually step over it, otherwise
 745          * the core will break again */
 746
 747         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 748                 && !debug_execution)
 749                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 750
 751         resume_pc = buf_get_u32(r->value, 0, 32);
 752
 753         armv7m_restore_context(target);
 754
 755         /* the front-end may request us not to handle breakpoints */
 756         if (handle_breakpoints) {
 757                 /* Single step past breakpoint at current address */
 758                 breakpoint = breakpoint_find(target, resume_pc);
 759                 if (breakpoint) {
 760                         LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
 761                                 breakpoint->address,
 762                                 breakpoint->unique_id);
 763                         cortex_m_unset_breakpoint(target, breakpoint);
 764                         cortex_m_single_step_core(target);
 765                         cortex_m_set_breakpoint(target, breakpoint);
 766                 }
 767         }
 768
 769         /* Restart core */
 770         cortex_m_write_debug_halt_mask(target, 0, C_HALT);
 771
 772         target->debug_reason = DBG_REASON_NOTHALTED;
 773
 774         /* registers are now invalid */
 775         register_cache_invalidate(armv7m->arm.core_cache);
 776
 777         if (!debug_execution) {
 778                 target->state = TARGET_RUNNING;
 779                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 780                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 781         } else {
 782                 target->state = TARGET_DEBUG_RUNNING;
 783                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 784                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 785         }
 786
 787         return ERROR_OK;
 788 }
 789
 790 /* int irqstepcount = 0; */
 791 static int cortex_m_step(struct target *target, int current,
 792         target_addr_t address, int handle_breakpoints)
 793 {
 794         struct cortex_m_common *cortex_m = target_to_cm(target);
 795         struct armv7m_common *armv7m = &cortex_m->armv7m;
 796         struct breakpoint *breakpoint = NULL;
 797         struct reg *pc = armv7m->arm.pc;
 798         bool bkpt_inst_found = false;
 799         int retval;
 800         bool isr_timed_out = false;
 801
 802         if (target->state != TARGET_HALTED) {
 803                 LOG_WARNING("target not halted");
 804                 return ERROR_TARGET_NOT_HALTED;
 805         }
 806
 807         /* current = 1: continue on current pc, otherwise continue at <address> */
 808         if (!current)
 809                 buf_set_u32(pc->value, 0, 32, address);
 810
 811         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
 812
 813         /* the front-end may request us not to handle breakpoints */
 814         if (handle_breakpoints) {
 815                 breakpoint = breakpoint_find(target, pc_value);
 816                 if (breakpoint)
 817                         cortex_m_unset_breakpoint(target, breakpoint);
 818         }
 819
 820         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 821
 822         target->debug_reason = DBG_REASON_SINGLESTEP;
 823
 824         armv7m_restore_context(target);
 825
 826         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 827
 828         /* if no bkpt instruction is found at pc then we can perform
 829          * a normal step, otherwise we have to manually step over the bkpt
 830          * instruction - as such simulate a step */
 831         if (bkpt_inst_found == false) {
 832                 /* Automatic ISR masking mode off: Just step over the next instruction */
 833                 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
 834                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 835                 else {
 836                         /* Process interrupts during stepping in a way they don't interfere
 837                          * debugging.
 838                          *
 839                          * Principle:
 840                          *
 841                          * Set a temporary break point at the current pc and let the core run
 842                          * with interrupts enabled. Pending interrupts get served and we run
 843                          * into the breakpoint again afterwards. Then we step over the next
 844                          * instruction with interrupts disabled.
 845                          *
 846                          * If the pending interrupts don't complete within time, we leave the
 847                          * core running. This may happen if the interrupts trigger faster
 848                          * than the core can process them or the handler doesn't return.
 849                          *
 850                          * If no more breakpoints are available we simply do a step with
 851                          * interrupts enabled.
 852                          *
 853                          */
 854
 855                         /* 2012-09-29 ph
 856                          *
 857                          * If a break point is already set on the lower half word then a break point on
 858                          * the upper half word will not break again when the core is restarted. So we
 859                          * just step over the instruction with interrupts disabled.
 860                          *
 861                          * The documentation has no information about this, it was found by observation
 862                          * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
 863                          * suffer from this problem.
 864                          *
 865                          * To add some confusion: pc_value has bit 0 always set, while the breakpoint
 866                          * address has it always cleared. The former is done to indicate thumb mode
 867                          * to gdb.
 868                          *
 869                          */
 870                         if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
 871                                 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
 872                                 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
 873                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 874                                 /* Re-enable interrupts */
 875                                 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
 876                         }
 877                         else {
 878
 879                                 /* Set a temporary break point */
 880                                 if (breakpoint) {
 881                                         retval = cortex_m_set_breakpoint(target, breakpoint);
 882                                 } else {
 883                                         enum breakpoint_type type = BKPT_HARD;
 884                                         if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
 885                                                 /* FPB rev.1 cannot handle such addr, try BKPT instr */
 886                                                 type = BKPT_SOFT;
 887                                         }
 888                                         retval = breakpoint_add(target, pc_value, 2, type);
 889                                 }
 890
 891                                 bool tmp_bp_set = (retval == ERROR_OK);
 892
 893                                 /* No more breakpoints left, just do a step */
 894                                 if (!tmp_bp_set)
 895                                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 896                                 else {
 897                                         /* Start the core */
 898                                         LOG_DEBUG("Starting core to serve pending interrupts");
 899                                         int64_t t_start = timeval_ms();
 900                                         cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
 901
 902                                         /* Wait for pending handlers to complete or timeout */
 903                                         do {
 904                                                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
 905                                                                 DCB_DHCSR,
 906                                                                 &cortex_m->dcb_dhcsr);
 907                                                 if (retval != ERROR_OK) {
 908                                                         target->state = TARGET_UNKNOWN;
 909                                                         return retval;
 910                                                 }
 911                                                 isr_timed_out = ((timeval_ms() - t_start) > 500);
 912                                         } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
 913
 914                                         /* only remove breakpoint if we created it */
 915                                         if (breakpoint)
 916                                                 cortex_m_unset_breakpoint(target, breakpoint);
 917                                         else {
 918                                                 /* Remove the temporary breakpoint */
 919                                                 breakpoint_remove(target, pc_value);
 920                                         }
 921
 922                                         if (isr_timed_out) {
 923                                                 LOG_DEBUG("Interrupt handlers didn't complete within time, "
 924                                                         "leaving target running");
 925                                         } else {
 926                                                 /* Step over next instruction with interrupts disabled */
 927                                                 cortex_m_write_debug_halt_mask(target,
 928                                                         C_HALT | C_MASKINTS,
 929                                                         0);
 930                                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 931                                                 /* Re-enable interrupts */
 932                                                 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
 933                                         }
 934                                 }
 935                         }
 936                 }
 937         }
 938
 939         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 940         if (retval != ERROR_OK)
 941                 return retval;
 942
 943         /* registers are now invalid */
 944         register_cache_invalidate(armv7m->arm.core_cache);
 945
 946         if (breakpoint)
 947                 cortex_m_set_breakpoint(target, breakpoint);
 948
 949         if (isr_timed_out) {
 950                 /* Leave the core running. The user has to stop execution manually. */
 951                 target->debug_reason = DBG_REASON_NOTHALTED;
 952                 target->state = TARGET_RUNNING;
 953                 return ERROR_OK;
 954         }
 955
 956         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 957                 " nvic_icsr = 0x%" PRIx32,
 958                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
 959
 960         retval = cortex_m_debug_entry(target);
 961         if (retval != ERROR_OK)
 962                 return retval;
 963         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 964
 965         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 966                 " nvic_icsr = 0x%" PRIx32,
 967                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
 968
 969         return ERROR_OK;
 970 }
 971
 972 static int cortex_m_assert_reset(struct target *target)
 973 {
 974         struct cortex_m_common *cortex_m = target_to_cm(target);
 975         struct armv7m_common *armv7m = &cortex_m->armv7m;
 976         enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
 977
 978         LOG_DEBUG("target->state: %s",
 979                 target_state_name(target));
 980
 981         enum reset_types jtag_reset_config = jtag_get_reset_config();
 982
 983         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
 984                 /* allow scripts to override the reset event */
 985
 986                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
 987                 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 988                 target->state = TARGET_RESET;
 989
 990                 return ERROR_OK;
 991         }
 992
 993         /* some cores support connecting while srst is asserted
 994          * use that mode is it has been configured */
 995
 996         bool srst_asserted = false;
 997
 998         if (!target_was_examined(target)) {
 999                 if (jtag_reset_config & RESET_HAS_SRST) {
1000                         adapter_assert_reset();
1001                         if (target->reset_halt)
1002                                 LOG_ERROR("Target not examined, will not halt after reset!");
1003                         return ERROR_OK;
1004                 } else {
1005                         LOG_ERROR("Target not examined, reset NOT asserted!");
1006                         return ERROR_FAIL;
1007                 }
1008         }
1009
1010         if ((jtag_reset_config & RESET_HAS_SRST) &&
1011             (jtag_reset_config & RESET_SRST_NO_GATING)) {
1012                 adapter_assert_reset();
1013                 srst_asserted = true;
1014         }
1015
1016         /* Enable debug requests */
1017         int retval;
1018         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1019         /* Store important errors instead of failing and proceed to reset assert */
1020
1021         if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1022                 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1023
1024         /* If the processor is sleeping in a WFI or WFE instruction, the
1025          * C_HALT bit must be asserted to regain control */
1026         if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1027                 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1028
1029         mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1030         /* Ignore less important errors */
1031
1032         if (!target->reset_halt) {
1033                 /* Set/Clear C_MASKINTS in a separate operation */
1034                 if (cortex_m->dcb_dhcsr & C_MASKINTS)
1035                         cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
1036
1037                 /* clear any debug flags before resuming */
1038                 cortex_m_clear_halt(target);
1039
1040                 /* clear C_HALT in dhcsr reg */
1041                 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1042         } else {
1043                 /* Halt in debug on reset; endreset_event() restores DEMCR.
1044                  *
1045                  * REVISIT catching BUSERR presumably helps to defend against
1046                  * bad vector table entries.  Should this include MMERR or
1047                  * other flags too?
1048                  */
1049                 int retval2;
1050                 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1051                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1052                 if (retval != ERROR_OK || retval2 != ERROR_OK)
1053                         LOG_INFO("AP write error, reset will not halt");
1054         }
1055
1056         if (jtag_reset_config & RESET_HAS_SRST) {
1057                 /* default to asserting srst */
1058                 if (!srst_asserted)
1059                         adapter_assert_reset();
1060
1061                 /* srst is asserted, ignore AP access errors */
1062                 retval = ERROR_OK;
1063         } else {
1064                 /* Use a standard Cortex-M3 software reset mechanism.
1065                  * We default to using VECRESET as it is supported on all current cores
1066                  * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1067                  * This has the disadvantage of not resetting the peripherals, so a
1068                  * reset-init event handler is needed to perform any peripheral resets.
1069                  */
1070                 if (!cortex_m->vectreset_supported
1071                                 && reset_config == CORTEX_M_RESET_VECTRESET) {
1072                         reset_config = CORTEX_M_RESET_SYSRESETREQ;
1073                         LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1074                         LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1075                 }
1076
1077                 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1078                         ? "SYSRESETREQ" : "VECTRESET");
1079
1080                 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1081                         LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1082                                 "handler to reset any peripherals or configure hardware srst support.");
1083                 }
1084
1085                 int retval3;
1086                 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1087                                 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1088                                 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1089                 if (retval3 != ERROR_OK)
1090                         LOG_DEBUG("Ignoring AP write error right after reset");
1091
1092                 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1093                 if (retval3 != ERROR_OK)
1094                         LOG_ERROR("DP initialisation failed");
1095
1096                 else {
1097                         /* I do not know why this is necessary, but it
1098                          * fixes strange effects (step/resume cause NMI
1099                          * after reset) on LM3S6918 -- Michael Schwingen
1100                          */
1101                         uint32_t tmp;
1102                         mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1103                 }
1104         }
1105
1106         target->state = TARGET_RESET;
1107         jtag_add_sleep(50000);
1108
1109         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1110
1111         /* now return stored error code if any */
1112         if (retval != ERROR_OK)
1113                 return retval;
1114
1115         if (target->reset_halt) {
1116                 retval = target_halt(target);
1117                 if (retval != ERROR_OK)
1118                         return retval;
1119         }
1120
1121         return ERROR_OK;
1122 }
1123
1124 static int cortex_m_deassert_reset(struct target *target)
1125 {
1126         struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1127
1128         LOG_DEBUG("target->state: %s",
1129                 target_state_name(target));
1130
1131         /* deassert reset lines */
1132         adapter_deassert_reset();
1133
1134         enum reset_types jtag_reset_config = jtag_get_reset_config();
1135
1136         if ((jtag_reset_config & RESET_HAS_SRST) &&
1137             !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1138                 target_was_examined(target)) {
1139                 int retval = dap_dp_init(armv7m->debug_ap->dap);
1140                 if (retval != ERROR_OK) {
1141                         LOG_ERROR("DP initialisation failed");
1142                         return retval;
1143                 }
1144         }
1145
1146         return ERROR_OK;
1147 }
1148
1149 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1150 {
1151         int retval;
1152         int fp_num = 0;
1153         struct cortex_m_common *cortex_m = target_to_cm(target);
1154         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1155
1156         if (breakpoint->set) {
1157                 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1158                 return ERROR_OK;
1159         }
1160
1161         if (breakpoint->type == BKPT_HARD) {
1162                 uint32_t fpcr_value;
1163                 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1164                         fp_num++;
1165                 if (fp_num >= cortex_m->fp_num_code) {
1166                         LOG_ERROR("Can not find free FPB Comparator!");
1167                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1168                 }
1169                 breakpoint->set = fp_num + 1;
1170                 fpcr_value = breakpoint->address | 1;
1171                 if (cortex_m->fp_rev == 0) {
1172                         if (breakpoint->address > 0x1FFFFFFF) {
1173                                 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1174                                 return ERROR_FAIL;
1175                         }
1176                         uint32_t hilo;
1177                         hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1178                         fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1179                 } else if (cortex_m->fp_rev > 1) {
1180                         LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1181                         return ERROR_FAIL;
1182                 }
1183                 comparator_list[fp_num].used = true;
1184                 comparator_list[fp_num].fpcr_value = fpcr_value;
1185                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1186                         comparator_list[fp_num].fpcr_value);
1187                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1188                         fp_num,
1189                         comparator_list[fp_num].fpcr_value);
1190                 if (!cortex_m->fpb_enabled) {
1191                         LOG_DEBUG("FPB wasn't enabled, do it now");
1192                         retval = cortex_m_enable_fpb(target);
1193                         if (retval != ERROR_OK) {
1194                                 LOG_ERROR("Failed to enable the FPB");
1195                                 return retval;
1196                         }
1197
1198                         cortex_m->fpb_enabled = true;
1199                 }
1200         } else if (breakpoint->type == BKPT_SOFT) {
1201                 uint8_t code[4];
1202
1203                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1204                  * semihosting; don't use that.  Otherwise the BKPT
1205                  * parameter is arbitrary.
1206                  */
1207                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1208                 retval = target_read_memory(target,
1209                                 breakpoint->address & 0xFFFFFFFE,
1210                                 breakpoint->length, 1,
1211                                 breakpoint->orig_instr);
1212                 if (retval != ERROR_OK)
1213                         return retval;
1214                 retval = target_write_memory(target,
1215                                 breakpoint->address & 0xFFFFFFFE,
1216                                 breakpoint->length, 1,
1217                                 code);
1218                 if (retval != ERROR_OK)
1219                         return retval;
1220                 breakpoint->set = true;
1221         }
1222
1223         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1224                 breakpoint->unique_id,
1225                 (int)(breakpoint->type),
1226                 breakpoint->address,
1227                 breakpoint->length,
1228                 breakpoint->set);
1229
1230         return ERROR_OK;
1231 }
1232
1233 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1234 {
1235         int retval;
1236         struct cortex_m_common *cortex_m = target_to_cm(target);
1237         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1238
1239         if (!breakpoint->set) {
1240                 LOG_WARNING("breakpoint not set");
1241                 return ERROR_OK;
1242         }
1243
1244         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1245                 breakpoint->unique_id,
1246                 (int)(breakpoint->type),
1247                 breakpoint->address,
1248                 breakpoint->length,
1249                 breakpoint->set);
1250
1251         if (breakpoint->type == BKPT_HARD) {
1252                 int fp_num = breakpoint->set - 1;
1253                 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1254                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1255                         return ERROR_OK;
1256                 }
1257                 comparator_list[fp_num].used = false;
1258                 comparator_list[fp_num].fpcr_value = 0;
1259                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1260                         comparator_list[fp_num].fpcr_value);
1261         } else {
1262                 /* restore original instruction (kept in target endianness) */
1263                 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1264                                         breakpoint->length, 1,
1265                                         breakpoint->orig_instr);
1266                 if (retval != ERROR_OK)
1267                         return retval;
1268         }
1269         breakpoint->set = false;
1270
1271         return ERROR_OK;
1272 }
1273
1274 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1275 {
1276         if (breakpoint->length == 3) {
1277                 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1278                 breakpoint->length = 2;
1279         }
1280
1281         if ((breakpoint->length != 2)) {
1282                 LOG_INFO("only breakpoints of two bytes length supported");
1283                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1284         }
1285
1286         return cortex_m_set_breakpoint(target, breakpoint);
1287 }
1288
1289 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1290 {
1291         if (!breakpoint->set)
1292                 return ERROR_OK;
1293
1294         return cortex_m_unset_breakpoint(target, breakpoint);
1295 }
1296
1297 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1298 {
1299         int dwt_num = 0;
1300         uint32_t mask, temp;
1301         struct cortex_m_common *cortex_m = target_to_cm(target);
1302
1303         /* watchpoint params were validated earlier */
1304         mask = 0;
1305         temp = watchpoint->length;
1306         while (temp) {
1307                 temp >>= 1;
1308                 mask++;
1309         }
1310         mask--;
1311
1312         /* REVISIT Don't fully trust these "not used" records ... users
1313          * may set up breakpoints by hand, e.g. dual-address data value
1314          * watchpoint using comparator #1; comparator #0 matching cycle
1315          * count; send data trace info through ITM and TPIU; etc
1316          */
1317         struct cortex_m_dwt_comparator *comparator;
1318
1319         for (comparator = cortex_m->dwt_comparator_list;
1320                 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1321                 comparator++, dwt_num++)
1322                 continue;
1323         if (dwt_num >= cortex_m->dwt_num_comp) {
1324                 LOG_ERROR("Can not find free DWT Comparator");
1325                 return ERROR_FAIL;
1326         }
1327         comparator->used = true;
1328         watchpoint->set = dwt_num + 1;
1329
1330         comparator->comp = watchpoint->address;
1331         target_write_u32(target, comparator->dwt_comparator_address + 0,
1332                 comparator->comp);
1333
1334         comparator->mask = mask;
1335         target_write_u32(target, comparator->dwt_comparator_address + 4,
1336                 comparator->mask);
1337
1338         switch (watchpoint->rw) {
1339                 case WPT_READ:
1340                         comparator->function = 5;
1341                         break;
1342                 case WPT_WRITE:
1343                         comparator->function = 6;
1344                         break;
1345                 case WPT_ACCESS:
1346                         comparator->function = 7;
1347                         break;
1348         }
1349         target_write_u32(target, comparator->dwt_comparator_address + 8,
1350                 comparator->function);
1351
1352         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1353                 watchpoint->unique_id, dwt_num,
1354                 (unsigned) comparator->comp,
1355                 (unsigned) comparator->mask,
1356                 (unsigned) comparator->function);
1357         return ERROR_OK;
1358 }
1359
1360 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1361 {
1362         struct cortex_m_common *cortex_m = target_to_cm(target);
1363         struct cortex_m_dwt_comparator *comparator;
1364         int dwt_num;
1365
1366         if (!watchpoint->set) {
1367                 LOG_WARNING("watchpoint (wpid: %d) not set",
1368                         watchpoint->unique_id);
1369                 return ERROR_OK;
1370         }
1371
1372         dwt_num = watchpoint->set - 1;
1373
1374         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1375                 watchpoint->unique_id, dwt_num,
1376                 (unsigned) watchpoint->address);
1377
1378         if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1379                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1380                 return ERROR_OK;
1381         }
1382
1383         comparator = cortex_m->dwt_comparator_list + dwt_num;
1384         comparator->used = false;
1385         comparator->function = 0;
1386         target_write_u32(target, comparator->dwt_comparator_address + 8,
1387                 comparator->function);
1388
1389         watchpoint->set = false;
1390
1391         return ERROR_OK;
1392 }
1393
1394 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1395 {
1396         struct cortex_m_common *cortex_m = target_to_cm(target);
1397
1398         if (cortex_m->dwt_comp_available < 1) {
1399                 LOG_DEBUG("no comparators?");
1400                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1401         }
1402
1403         /* hardware doesn't support data value masking */
1404         if (watchpoint->mask != ~(uint32_t)0) {
1405                 LOG_DEBUG("watchpoint value masks not supported");
1406                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1407         }
1408
1409         /* hardware allows address masks of up to 32K */
1410         unsigned mask;
1411
1412         for (mask = 0; mask < 16; mask++) {
1413                 if ((1u << mask) == watchpoint->length)
1414                         break;
1415         }
1416         if (mask == 16) {
1417                 LOG_DEBUG("unsupported watchpoint length");
1418                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1419         }
1420         if (watchpoint->address & ((1 << mask) - 1)) {
1421                 LOG_DEBUG("watchpoint address is unaligned");
1422                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1423         }
1424
1425         /* Caller doesn't seem to be able to describe watching for data
1426          * values of zero; that flags "no value".
1427          *
1428          * REVISIT This DWT may well be able to watch for specific data
1429          * values.  Requires comparator #1 to set DATAVMATCH and match
1430          * the data, and another comparator (DATAVADDR0) matching addr.
1431          */
1432         if (watchpoint->value) {
1433                 LOG_DEBUG("data value watchpoint not YET supported");
1434                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1435         }
1436
1437         cortex_m->dwt_comp_available--;
1438         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1439
1440         return ERROR_OK;
1441 }
1442
1443 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1444 {
1445         struct cortex_m_common *cortex_m = target_to_cm(target);
1446
1447         /* REVISIT why check? DWT can be updated with core running ... */
1448         if (target->state != TARGET_HALTED) {
1449                 LOG_WARNING("target not halted");
1450                 return ERROR_TARGET_NOT_HALTED;
1451         }
1452
1453         if (watchpoint->set)
1454                 cortex_m_unset_watchpoint(target, watchpoint);
1455
1456         cortex_m->dwt_comp_available++;
1457         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1458
1459         return ERROR_OK;
1460 }
1461
1462 void cortex_m_enable_watchpoints(struct target *target)
1463 {
1464         struct watchpoint *watchpoint = target->watchpoints;
1465
1466         /* set any pending watchpoints */
1467         while (watchpoint) {
1468                 if (!watchpoint->set)
1469                         cortex_m_set_watchpoint(target, watchpoint);
1470                 watchpoint = watchpoint->next;
1471         }
1472 }
1473
1474 static int cortex_m_load_core_reg_u32(struct target *target,
1475                 uint32_t num, uint32_t *value)
1476 {
1477         int retval;
1478
1479         /* NOTE:  we "know" here that the register identifiers used
1480          * in the v7m header match the Cortex-M3 Debug Core Register
1481          * Selector values for R0..R15, xPSR, MSP, and PSP.
1482          */
1483         switch (num) {
1484                 case 0 ... 18:
1485                         /* read a normal core register */
1486                         retval = cortexm_dap_read_coreregister_u32(target, value, num);
1487
1488                         if (retval != ERROR_OK) {
1489                                 LOG_ERROR("JTAG failure %i", retval);
1490                                 return ERROR_JTAG_DEVICE_ERROR;
1491                         }
1492                         LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
1493                         break;
1494
1495                 case ARMV7M_FPSCR:
1496                         /* Floating-point Status and Registers */
1497                         retval = target_write_u32(target, DCB_DCRSR, 0x21);
1498                         if (retval != ERROR_OK)
1499                                 return retval;
1500                         retval = target_read_u32(target, DCB_DCRDR, value);
1501                         if (retval != ERROR_OK)
1502                                 return retval;
1503                         LOG_DEBUG("load from FPSCR  value 0x%" PRIx32, *value);
1504                         break;
1505
1506                 case ARMV7M_S0 ... ARMV7M_S31:
1507                         /* Floating-point Status and Registers */
1508                         retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1509                         if (retval != ERROR_OK)
1510                                 return retval;
1511                         retval = target_read_u32(target, DCB_DCRDR, value);
1512                         if (retval != ERROR_OK)
1513                                 return retval;
1514                         LOG_DEBUG("load from FPU reg S%d  value 0x%" PRIx32,
1515                                   (int)(num - ARMV7M_S0), *value);
1516                         break;
1517
1518                 case ARMV7M_PRIMASK:
1519                 case ARMV7M_BASEPRI:
1520                 case ARMV7M_FAULTMASK:
1521                 case ARMV7M_CONTROL:
1522                         /* Cortex-M3 packages these four registers as bitfields
1523                          * in one Debug Core register.  So say r0 and r2 docs;
1524                          * it was removed from r1 docs, but still works.
1525                          */
1526                         cortexm_dap_read_coreregister_u32(target, value, 20);
1527
1528                         switch (num) {
1529                                 case ARMV7M_PRIMASK:
1530                                         *value = buf_get_u32((uint8_t *)value, 0, 1);
1531                                         break;
1532
1533                                 case ARMV7M_BASEPRI:
1534                                         *value = buf_get_u32((uint8_t *)value, 8, 8);
1535                                         break;
1536
1537                                 case ARMV7M_FAULTMASK:
1538                                         *value = buf_get_u32((uint8_t *)value, 16, 1);
1539                                         break;
1540
1541                                 case ARMV7M_CONTROL:
1542                                         *value = buf_get_u32((uint8_t *)value, 24, 2);
1543                                         break;
1544                         }
1545
1546                         LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1547                         break;
1548
1549                 default:
1550                         return ERROR_COMMAND_SYNTAX_ERROR;
1551         }
1552
1553         return ERROR_OK;
1554 }
1555
1556 static int cortex_m_store_core_reg_u32(struct target *target,
1557                 uint32_t num, uint32_t value)
1558 {
1559         int retval;
1560         uint32_t reg;
1561         struct armv7m_common *armv7m = target_to_armv7m(target);
1562
1563         /* NOTE:  we "know" here that the register identifiers used
1564          * in the v7m header match the Cortex-M3 Debug Core Register
1565          * Selector values for R0..R15, xPSR, MSP, and PSP.
1566          */
1567         switch (num) {
1568                 case 0 ... 18:
1569                         retval = cortexm_dap_write_coreregister_u32(target, value, num);
1570                         if (retval != ERROR_OK) {
1571                                 struct reg *r;
1572
1573                                 LOG_ERROR("JTAG failure");
1574                                 r = armv7m->arm.core_cache->reg_list + num;
1575                                 r->dirty = r->valid;
1576                                 return ERROR_JTAG_DEVICE_ERROR;
1577                         }
1578                         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1579                         break;
1580
1581                 case ARMV7M_FPSCR:
1582                         /* Floating-point Status and Registers */
1583                         retval = target_write_u32(target, DCB_DCRDR, value);
1584                         if (retval != ERROR_OK)
1585                                 return retval;
1586                         retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1587                         if (retval != ERROR_OK)
1588                                 return retval;
1589                         LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1590                         break;
1591
1592                 case ARMV7M_S0 ... ARMV7M_S31:
1593                         /* Floating-point Status and Registers */
1594                         retval = target_write_u32(target, DCB_DCRDR, value);
1595                         if (retval != ERROR_OK)
1596                                 return retval;
1597                         retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1598                         if (retval != ERROR_OK)
1599                                 return retval;
1600                         LOG_DEBUG("write FPU reg S%d  value 0x%" PRIx32,
1601                                   (int)(num - ARMV7M_S0), value);
1602                         break;
1603
1604                 case ARMV7M_PRIMASK:
1605                 case ARMV7M_BASEPRI:
1606                 case ARMV7M_FAULTMASK:
1607                 case ARMV7M_CONTROL:
1608                         /* Cortex-M3 packages these four registers as bitfields
1609                          * in one Debug Core register.  So say r0 and r2 docs;
1610                          * it was removed from r1 docs, but still works.
1611                          */
1612                         cortexm_dap_read_coreregister_u32(target, &reg, 20);
1613
1614                         switch (num) {
1615                                 case ARMV7M_PRIMASK:
1616                                         buf_set_u32((uint8_t *)&reg, 0, 1, value);
1617                                         break;
1618
1619                                 case ARMV7M_BASEPRI:
1620                                         buf_set_u32((uint8_t *)&reg, 8, 8, value);
1621                                         break;
1622
1623                                 case ARMV7M_FAULTMASK:
1624                                         buf_set_u32((uint8_t *)&reg, 16, 1, value);
1625                                         break;
1626
1627                                 case ARMV7M_CONTROL:
1628                                         buf_set_u32((uint8_t *)&reg, 24, 2, value);
1629                                         break;
1630                         }
1631
1632                         cortexm_dap_write_coreregister_u32(target, reg, 20);
1633
1634                         LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1635                         break;
1636
1637                 default:
1638                         return ERROR_COMMAND_SYNTAX_ERROR;
1639         }
1640
1641         return ERROR_OK;
1642 }
1643
1644 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1645         uint32_t size, uint32_t count, uint8_t *buffer)
1646 {
1647         struct armv7m_common *armv7m = target_to_armv7m(target);
1648
1649         if (armv7m->arm.is_armv6m) {
1650                 /* armv6m does not handle unaligned memory access */
1651                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1652                         return ERROR_TARGET_UNALIGNED_ACCESS;
1653         }
1654
1655         return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1656 }
1657
1658 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1659         uint32_t size, uint32_t count, const uint8_t *buffer)
1660 {
1661         struct armv7m_common *armv7m = target_to_armv7m(target);
1662
1663         if (armv7m->arm.is_armv6m) {
1664                 /* armv6m does not handle unaligned memory access */
1665                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1666                         return ERROR_TARGET_UNALIGNED_ACCESS;
1667         }
1668
1669         return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1670 }
1671
1672 static int cortex_m_init_target(struct command_context *cmd_ctx,
1673         struct target *target)
1674 {
1675         armv7m_build_reg_cache(target);
1676         arm_semihosting_init(target);
1677         return ERROR_OK;
1678 }
1679
1680 void cortex_m_deinit_target(struct target *target)
1681 {
1682         struct cortex_m_common *cortex_m = target_to_cm(target);
1683
1684         free(cortex_m->fp_comparator_list);
1685
1686         cortex_m_dwt_free(target);
1687         armv7m_free_reg_cache(target);
1688
1689         free(target->private_config);
1690         free(cortex_m);
1691 }
1692
1693 int cortex_m_profiling(struct target *target, uint32_t *samples,
1694                               uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1695 {
1696         struct timeval timeout, now;
1697         struct armv7m_common *armv7m = target_to_armv7m(target);
1698         uint32_t reg_value;
1699         bool use_pcsr = false;
1700         int retval = ERROR_OK;
1701         struct reg *reg;
1702
1703         gettimeofday(&timeout, NULL);
1704         timeval_add_time(&timeout, seconds, 0);
1705
1706         retval = target_read_u32(target, DWT_PCSR, &reg_value);
1707         if (retval != ERROR_OK) {
1708                 LOG_ERROR("Error while reading PCSR");
1709                 return retval;
1710         }
1711
1712         if (reg_value != 0) {
1713                 use_pcsr = true;
1714                 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1715         } else {
1716                 LOG_INFO("Starting profiling. Halting and resuming the"
1717                          " target as often as we can...");
1718                 reg = register_get_by_name(target->reg_cache, "pc", 1);
1719         }
1720
1721         /* Make sure the target is running */
1722         target_poll(target);
1723         if (target->state == TARGET_HALTED)
1724                 retval = target_resume(target, 1, 0, 0, 0);
1725
1726         if (retval != ERROR_OK) {
1727                 LOG_ERROR("Error while resuming target");
1728                 return retval;
1729         }
1730
1731         uint32_t sample_count = 0;
1732
1733         for (;;) {
1734                 if (use_pcsr) {
1735                         if (armv7m && armv7m->debug_ap) {
1736                                 uint32_t read_count = max_num_samples - sample_count;
1737                                 if (read_count > 1024)
1738                                         read_count = 1024;
1739
1740                                 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1741                                                         (void *)&samples[sample_count],
1742                                                         4, read_count, DWT_PCSR);
1743                                 sample_count += read_count;
1744                         } else {
1745                                 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1746                         }
1747                 } else {
1748                         target_poll(target);
1749                         if (target->state == TARGET_HALTED) {
1750                                 reg_value = buf_get_u32(reg->value, 0, 32);
1751                                 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1752                                 retval = target_resume(target, 1, 0, 0, 0);
1753                                 samples[sample_count++] = reg_value;
1754                                 target_poll(target);
1755                                 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1756                         } else if (target->state == TARGET_RUNNING) {
1757                                 /* We want to quickly sample the PC. */
1758                                 retval = target_halt(target);
1759                         } else {
1760                                 LOG_INFO("Target not halted or running");
1761                                 retval = ERROR_OK;
1762                                 break;
1763                         }
1764                 }
1765
1766                 if (retval != ERROR_OK) {
1767                         LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1768                         return retval;
1769                 }
1770
1771
1772                 gettimeofday(&now, NULL);
1773                 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1774                         LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1775                         break;
1776                 }
1777         }
1778
1779         *num_samples = sample_count;
1780         return retval;
1781 }
1782
1783
1784 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1785  * on r/w if the core is not running, and clear on resume or reset ... or
1786  * at least, in a post_restore_context() method.
1787  */
1788
1789 struct dwt_reg_state {
1790         struct target *target;
1791         uint32_t addr;
1792         uint8_t value[4];               /* scratch/cache */
1793 };
1794
1795 static int cortex_m_dwt_get_reg(struct reg *reg)
1796 {
1797         struct dwt_reg_state *state = reg->arch_info;
1798
1799         uint32_t tmp;
1800         int retval = target_read_u32(state->target, state->addr, &tmp);
1801         if (retval != ERROR_OK)
1802                 return retval;
1803
1804         buf_set_u32(state->value, 0, 32, tmp);
1805         return ERROR_OK;
1806 }
1807
1808 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1809 {
1810         struct dwt_reg_state *state = reg->arch_info;
1811
1812         return target_write_u32(state->target, state->addr,
1813                         buf_get_u32(buf, 0, reg->size));
1814 }
1815
1816 struct dwt_reg {
1817         uint32_t addr;
1818         const char *name;
1819         unsigned size;
1820 };
1821
1822 static const struct dwt_reg dwt_base_regs[] = {
1823         { DWT_CTRL, "dwt_ctrl", 32, },
1824         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1825          * increments while the core is asleep.
1826          */
1827         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1828         /* plus some 8 bit counters, useful for profiling with TPIU */
1829 };
1830
1831 static const struct dwt_reg dwt_comp[] = {
1832 #define DWT_COMPARATOR(i) \
1833                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1834                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1835                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1836         DWT_COMPARATOR(0),
1837         DWT_COMPARATOR(1),
1838         DWT_COMPARATOR(2),
1839         DWT_COMPARATOR(3),
1840         DWT_COMPARATOR(4),
1841         DWT_COMPARATOR(5),
1842         DWT_COMPARATOR(6),
1843         DWT_COMPARATOR(7),
1844         DWT_COMPARATOR(8),
1845         DWT_COMPARATOR(9),
1846         DWT_COMPARATOR(10),
1847         DWT_COMPARATOR(11),
1848         DWT_COMPARATOR(12),
1849         DWT_COMPARATOR(13),
1850         DWT_COMPARATOR(14),
1851         DWT_COMPARATOR(15),
1852 #undef DWT_COMPARATOR
1853 };
1854
1855 static const struct reg_arch_type dwt_reg_type = {
1856         .get = cortex_m_dwt_get_reg,
1857         .set = cortex_m_dwt_set_reg,
1858 };
1859
1860 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1861 {
1862         struct dwt_reg_state *state;
1863
1864         state = calloc(1, sizeof *state);
1865         if (!state)
1866                 return;
1867         state->addr = d->addr;
1868         state->target = t;
1869
1870         r->name = d->name;
1871         r->size = d->size;
1872         r->value = state->value;
1873         r->arch_info = state;
1874         r->type = &dwt_reg_type;
1875 }
1876
1877 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1878 {
1879         uint32_t dwtcr;
1880         struct reg_cache *cache;
1881         struct cortex_m_dwt_comparator *comparator;
1882         int reg, i;
1883
1884         target_read_u32(target, DWT_CTRL, &dwtcr);
1885         LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1886         if (!dwtcr) {
1887                 LOG_DEBUG("no DWT");
1888                 return;
1889         }
1890
1891         cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1892         cm->dwt_comp_available = cm->dwt_num_comp;
1893         cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1894                         sizeof(struct cortex_m_dwt_comparator));
1895         if (!cm->dwt_comparator_list) {
1896 fail0:
1897                 cm->dwt_num_comp = 0;
1898                 LOG_ERROR("out of mem");
1899                 return;
1900         }
1901
1902         cache = calloc(1, sizeof *cache);
1903         if (!cache) {
1904 fail1:
1905                 free(cm->dwt_comparator_list);
1906                 goto fail0;
1907         }
1908         cache->name = "Cortex-M DWT registers";
1909         cache->num_regs = 2 + cm->dwt_num_comp * 3;
1910         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1911         if (!cache->reg_list) {
1912                 free(cache);
1913                 goto fail1;
1914         }
1915
1916         for (reg = 0; reg < 2; reg++)
1917                 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1918                         dwt_base_regs + reg);
1919
1920         comparator = cm->dwt_comparator_list;
1921         for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1922                 int j;
1923
1924                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1925                 for (j = 0; j < 3; j++, reg++)
1926                         cortex_m_dwt_addreg(target, cache->reg_list + reg,
1927                                 dwt_comp + 3 * i + j);
1928
1929                 /* make sure we clear any watchpoints enabled on the target */
1930                 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1931         }
1932
1933         *register_get_last_cache_p(&target->reg_cache) = cache;
1934         cm->dwt_cache = cache;
1935
1936         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1937                 dwtcr, cm->dwt_num_comp,
1938                 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1939
1940         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1941          * implement single-address data value watchpoints ... so we
1942          * won't need to check it later, when asked to set one up.
1943          */
1944 }
1945
1946 static void cortex_m_dwt_free(struct target *target)
1947 {
1948         struct cortex_m_common *cm = target_to_cm(target);
1949         struct reg_cache *cache = cm->dwt_cache;
1950
1951         free(cm->dwt_comparator_list);
1952         cm->dwt_comparator_list = NULL;
1953         cm->dwt_num_comp = 0;
1954
1955         if (cache) {
1956                 register_unlink_cache(&target->reg_cache, cache);
1957
1958                 if (cache->reg_list) {
1959                         for (size_t i = 0; i < cache->num_regs; i++)
1960                                 free(cache->reg_list[i].arch_info);
1961                         free(cache->reg_list);
1962                 }
1963                 free(cache);
1964         }
1965         cm->dwt_cache = NULL;
1966 }
1967
1968 #define MVFR0 0xe000ef40
1969 #define MVFR1 0xe000ef44
1970
1971 #define MVFR0_DEFAULT_M4 0x10110021
1972 #define MVFR1_DEFAULT_M4 0x11000011
1973
1974 #define MVFR0_DEFAULT_M7_SP 0x10110021
1975 #define MVFR0_DEFAULT_M7_DP 0x10110221
1976 #define MVFR1_DEFAULT_M7_SP 0x11000011
1977 #define MVFR1_DEFAULT_M7_DP 0x12000011
1978
1979 int cortex_m_examine(struct target *target)
1980 {
1981         int retval;
1982         uint32_t cpuid, fpcr, mvfr0, mvfr1;
1983         int i;
1984         struct cortex_m_common *cortex_m = target_to_cm(target);
1985         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1986         struct armv7m_common *armv7m = target_to_armv7m(target);
1987
1988         /* stlink shares the examine handler but does not support
1989          * all its calls */
1990         if (!armv7m->stlink) {
1991                 if (cortex_m->apsel == DP_APSEL_INVALID) {
1992                         /* Search for the MEM-AP */
1993                         retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
1994                         if (retval != ERROR_OK) {
1995                                 LOG_ERROR("Could not find MEM-AP to control the core");
1996                                 return retval;
1997                         }
1998                 } else {
1999                         armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2000                 }
2001
2002                 /* Leave (only) generic DAP stuff for debugport_init(); */
2003                 armv7m->debug_ap->memaccess_tck = 8;
2004
2005                 retval = mem_ap_init(armv7m->debug_ap);
2006                 if (retval != ERROR_OK)
2007                         return retval;
2008         }
2009
2010         if (!target_was_examined(target)) {
2011                 target_set_examined(target);
2012
2013                 /* Read from Device Identification Registers */
2014                 retval = target_read_u32(target, CPUID, &cpuid);
2015                 if (retval != ERROR_OK)
2016                         return retval;
2017
2018                 /* Get CPU Type */
2019                 i = (cpuid >> 4) & 0xf;
2020
2021                 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2022                                 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2023                 if (i == 7) {
2024                         uint8_t rev, patch;
2025                         rev = (cpuid >> 20) & 0xf;
2026                         patch = (cpuid >> 0) & 0xf;
2027                         if ((rev == 0) && (patch < 2))
2028                                 LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
2029                 }
2030                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2031
2032                 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2033                 cortex_m->vectreset_supported = i > 1;
2034
2035                 if (i == 4) {
2036                         target_read_u32(target, MVFR0, &mvfr0);
2037                         target_read_u32(target, MVFR1, &mvfr1);
2038
2039                         /* test for floating point feature on Cortex-M4 */
2040                         if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2041                                 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2042                                 armv7m->fp_feature = FPv4_SP;
2043                         }
2044                 } else if (i == 7) {
2045                         target_read_u32(target, MVFR0, &mvfr0);
2046                         target_read_u32(target, MVFR1, &mvfr1);
2047
2048                         /* test for floating point features on Cortex-M7 */
2049                         if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2050                                 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2051                                 armv7m->fp_feature = FPv5_SP;
2052                         } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2053                                 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2054                                 armv7m->fp_feature = FPv5_DP;
2055                         }
2056                 } else if (i == 0) {
2057                         /* Cortex-M0 does not support unaligned memory access */
2058                         armv7m->arm.is_armv6m = true;
2059                 }
2060
2061                 if (armv7m->fp_feature == FP_NONE &&
2062                     armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2063                         /* free unavailable FPU registers */
2064                         size_t idx;
2065
2066                         for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2067                              idx < armv7m->arm.core_cache->num_regs;
2068                              idx++) {
2069                                 free(armv7m->arm.core_cache->reg_list[idx].value);
2070                                 free(armv7m->arm.core_cache->reg_list[idx].feature);
2071                                 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2072                         }
2073                         armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2074                 }
2075
2076                 if (!armv7m->stlink) {
2077                         if (i == 3 || i == 4)
2078                                 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2079                                  * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2080                                 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2081                         else if (i == 7)
2082                                 /* Cortex-M7 has only 1024 bytes autoincrement range */
2083                                 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2084                 }
2085
2086                 /* Configure trace modules */
2087                 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2088                 if (retval != ERROR_OK)
2089                         return retval;
2090
2091                 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2092                         armv7m_trace_tpiu_config(target);
2093                         armv7m_trace_itm_config(target);
2094                 }
2095
2096                 /* NOTE: FPB and DWT are both optional. */
2097
2098                 /* Setup FPB */
2099                 target_read_u32(target, FP_CTRL, &fpcr);
2100                 /* bits [14:12] and [7:4] */
2101                 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2102                 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2103                 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2104                    Revision is zero base, fp_rev == 1 means Rev.2 ! */
2105                 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2106                 free(cortex_m->fp_comparator_list);
2107                 cortex_m->fp_comparator_list = calloc(
2108                                 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2109                                 sizeof(struct cortex_m_fp_comparator));
2110                 cortex_m->fpb_enabled = fpcr & 1;
2111                 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2112                         cortex_m->fp_comparator_list[i].type =
2113                                 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2114                         cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2115
2116                         /* make sure we clear any breakpoints enabled on the target */
2117                         target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2118                 }
2119                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2120                         fpcr,
2121                         cortex_m->fp_num_code,
2122                         cortex_m->fp_num_lit);
2123
2124                 /* Setup DWT */
2125                 cortex_m_dwt_free(target);
2126                 cortex_m_dwt_setup(cortex_m, target);
2127
2128                 /* These hardware breakpoints only work for code in flash! */
2129                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2130                         target_name(target),
2131                         cortex_m->fp_num_code,
2132                         cortex_m->dwt_num_comp);
2133         }
2134
2135         return ERROR_OK;
2136 }
2137
2138 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2139 {
2140         struct armv7m_common *armv7m = target_to_armv7m(target);
2141         uint16_t dcrdr;
2142         uint8_t buf[2];
2143         int retval;
2144
2145         retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2146         if (retval != ERROR_OK)
2147                 return retval;
2148
2149         dcrdr = target_buffer_get_u16(target, buf);
2150         *ctrl = (uint8_t)dcrdr;
2151         *value = (uint8_t)(dcrdr >> 8);
2152
2153         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2154
2155         /* write ack back to software dcc register
2156          * signify we have read data */
2157         if (dcrdr & (1 << 0)) {
2158                 target_buffer_set_u16(target, buf, 0);
2159                 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2160                 if (retval != ERROR_OK)
2161                         return retval;
2162         }
2163
2164         return ERROR_OK;
2165 }
2166
2167 static int cortex_m_target_request_data(struct target *target,
2168         uint32_t size, uint8_t *buffer)
2169 {
2170         uint8_t data;
2171         uint8_t ctrl;
2172         uint32_t i;
2173
2174         for (i = 0; i < (size * 4); i++) {
2175                 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2176                 if (retval != ERROR_OK)
2177                         return retval;
2178                 buffer[i] = data;
2179         }
2180
2181         return ERROR_OK;
2182 }
2183
2184 static int cortex_m_handle_target_request(void *priv)
2185 {
2186         struct target *target = priv;
2187         if (!target_was_examined(target))
2188                 return ERROR_OK;
2189
2190         if (!target->dbg_msg_enabled)
2191                 return ERROR_OK;
2192
2193         if (target->state == TARGET_RUNNING) {
2194                 uint8_t data;
2195                 uint8_t ctrl;
2196                 int retval;
2197
2198                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2199                 if (retval != ERROR_OK)
2200                         return retval;
2201
2202                 /* check if we have data */
2203                 if (ctrl & (1 << 0)) {
2204                         uint32_t request;
2205
2206                         /* we assume target is quick enough */
2207                         request = data;
2208                         for (int i = 1; i <= 3; i++) {
2209                                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2210                                 if (retval != ERROR_OK)
2211                                         return retval;
2212                                 request |= ((uint32_t)data << (i * 8));
2213                         }
2214                         target_request(target, request);
2215                 }
2216         }
2217
2218         return ERROR_OK;
2219 }
2220
2221 static int cortex_m_init_arch_info(struct target *target,
2222         struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2223 {
2224         struct armv7m_common *armv7m = &cortex_m->armv7m;
2225
2226         armv7m_init_arch_info(target, armv7m);
2227
2228         /* default reset mode is to use srst if fitted
2229          * if not it will use CORTEX_M3_RESET_VECTRESET */
2230         cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2231
2232         armv7m->arm.dap = dap;
2233
2234         /* register arch-specific functions */
2235         armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2236
2237         armv7m->post_debug_entry = NULL;
2238
2239         armv7m->pre_restore_context = NULL;
2240
2241         armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2242         armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2243
2244         target_register_timer_callback(cortex_m_handle_target_request, 1,
2245                 TARGET_TIMER_TYPE_PERIODIC, target);
2246
2247         return ERROR_OK;
2248 }
2249
2250 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2251 {
2252         struct adiv5_private_config *pc;
2253
2254         pc = (struct adiv5_private_config *)target->private_config;
2255         if (adiv5_verify_config(pc) != ERROR_OK)
2256                 return ERROR_FAIL;
2257
2258         struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2259         if (cortex_m == NULL) {
2260                 LOG_ERROR("No memory creating target");
2261                 return ERROR_FAIL;
2262         }
2263
2264         cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2265         cortex_m->apsel = pc->ap_num;
2266
2267         cortex_m_init_arch_info(target, cortex_m, pc->dap);
2268
2269         return ERROR_OK;
2270 }
2271
2272 /*--------------------------------------------------------------------------*/
2273
2274 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2275         struct cortex_m_common *cm)
2276 {
2277         if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2278                 command_print(cmd_ctx, "target is not a Cortex-M");
2279                 return ERROR_TARGET_INVALID;
2280         }
2281         return ERROR_OK;
2282 }
2283
2284 /*
2285  * Only stuff below this line should need to verify that its target
2286  * is a Cortex-M3.  Everything else should have indirected through the
2287  * cortexm3_target structure, which is only used with CM3 targets.
2288  */
2289
2290 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2291 {
2292         struct target *target = get_current_target(CMD_CTX);
2293         struct cortex_m_common *cortex_m = target_to_cm(target);
2294         struct armv7m_common *armv7m = &cortex_m->armv7m;
2295         uint32_t demcr = 0;
2296         int retval;
2297
2298         static const struct {
2299                 char name[10];
2300                 unsigned mask;
2301         } vec_ids[] = {
2302                 { "hard_err",   VC_HARDERR, },
2303                 { "int_err",    VC_INTERR, },
2304                 { "bus_err",    VC_BUSERR, },
2305                 { "state_err",  VC_STATERR, },
2306                 { "chk_err",    VC_CHKERR, },
2307                 { "nocp_err",   VC_NOCPERR, },
2308                 { "mm_err",     VC_MMERR, },
2309                 { "reset",      VC_CORERESET, },
2310         };
2311
2312         retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2313         if (retval != ERROR_OK)
2314                 return retval;
2315
2316         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2317         if (retval != ERROR_OK)
2318                 return retval;
2319
2320         if (CMD_ARGC > 0) {
2321                 unsigned catch = 0;
2322
2323                 if (CMD_ARGC == 1) {
2324                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2325                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2326                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2327                                         | VC_MMERR | VC_CORERESET;
2328                                 goto write;
2329                         } else if (strcmp(CMD_ARGV[0], "none") == 0)
2330                                 goto write;
2331                 }
2332                 while (CMD_ARGC-- > 0) {
2333                         unsigned i;
2334                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2335                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2336                                         continue;
2337                                 catch |= vec_ids[i].mask;
2338                                 break;
2339                         }
2340                         if (i == ARRAY_SIZE(vec_ids)) {
2341                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2342                                 return ERROR_COMMAND_SYNTAX_ERROR;
2343                         }
2344                 }
2345 write:
2346                 /* For now, armv7m->demcr only stores vector catch flags. */
2347                 armv7m->demcr = catch;
2348
2349                 demcr &= ~0xffff;
2350                 demcr |= catch;
2351
2352                 /* write, but don't assume it stuck (why not??) */
2353                 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2354                 if (retval != ERROR_OK)
2355                         return retval;
2356                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2357                 if (retval != ERROR_OK)
2358                         return retval;
2359
2360                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2361                  * Otherwise the vector catch hardware could fire when there's
2362                  * no debugger hooked up, causing much confusion...
2363                  */
2364         }
2365
2366         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2367                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2368                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2369         }
2370
2371         return ERROR_OK;
2372 }
2373
2374 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2375 {
2376         struct target *target = get_current_target(CMD_CTX);
2377         struct cortex_m_common *cortex_m = target_to_cm(target);
2378         int retval;
2379
2380         static const Jim_Nvp nvp_maskisr_modes[] = {
2381                 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2382                 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2383                 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2384                 { .name = NULL, .value = -1 },
2385         };
2386         const Jim_Nvp *n;
2387
2388
2389         retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2390         if (retval != ERROR_OK)
2391                 return retval;
2392
2393         if (target->state != TARGET_HALTED) {
2394                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2395                 return ERROR_OK;
2396         }
2397
2398         if (CMD_ARGC > 0) {
2399                 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2400                 if (n->name == NULL)
2401                         return ERROR_COMMAND_SYNTAX_ERROR;
2402                 cortex_m->isrmasking_mode = n->value;
2403
2404
2405                 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2406                         cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2407                 else
2408                         cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2409         }
2410
2411         n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2412         command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2413
2414         return ERROR_OK;
2415 }
2416
2417 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2418 {
2419         struct target *target = get_current_target(CMD_CTX);
2420         struct cortex_m_common *cortex_m = target_to_cm(target);
2421         int retval;
2422         char *reset_config;
2423
2424         retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2425         if (retval != ERROR_OK)
2426                 return retval;
2427
2428         if (CMD_ARGC > 0) {
2429                 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2430                         cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2431
2432                 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2433                         if (target_was_examined(target)
2434                                         && !cortex_m->vectreset_supported)
2435                                 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2436                         else
2437                                 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2438
2439                 } else
2440                         return ERROR_COMMAND_SYNTAX_ERROR;
2441         }
2442
2443         switch (cortex_m->soft_reset_config) {
2444                 case CORTEX_M_RESET_SYSRESETREQ:
2445                         reset_config = "sysresetreq";
2446                         break;
2447
2448                 case CORTEX_M_RESET_VECTRESET:
2449                         reset_config = "vectreset";
2450                         break;
2451
2452                 default:
2453                         reset_config = "unknown";
2454                         break;
2455         }
2456
2457         command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2458
2459         return ERROR_OK;
2460 }
2461
2462 static const struct command_registration cortex_m_exec_command_handlers[] = {
2463         {
2464                 .name = "maskisr",
2465                 .handler = handle_cortex_m_mask_interrupts_command,
2466                 .mode = COMMAND_EXEC,
2467                 .help = "mask cortex_m interrupts",
2468                 .usage = "['auto'|'on'|'off']",
2469         },
2470         {
2471                 .name = "vector_catch",
2472                 .handler = handle_cortex_m_vector_catch_command,
2473                 .mode = COMMAND_EXEC,
2474                 .help = "configure hardware vectors to trigger debug entry",
2475                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2476         },
2477         {
2478                 .name = "reset_config",
2479                 .handler = handle_cortex_m_reset_config_command,
2480                 .mode = COMMAND_ANY,
2481                 .help = "configure software reset handling",
2482                 .usage = "['sysresetreq'|'vectreset']",
2483         },
2484         COMMAND_REGISTRATION_DONE
2485 };
2486 static const struct command_registration cortex_m_command_handlers[] = {
2487         {
2488                 .chain = armv7m_command_handlers,
2489         },
2490         {
2491                 .chain = armv7m_trace_command_handlers,
2492         },
2493         {
2494                 .name = "cortex_m",
2495                 .mode = COMMAND_EXEC,
2496                 .help = "Cortex-M command group",
2497                 .usage = "",
2498                 .chain = cortex_m_exec_command_handlers,
2499         },
2500         COMMAND_REGISTRATION_DONE
2501 };
2502
2503 struct target_type cortexm_target = {
2504         .name = "cortex_m",
2505         .deprecated_name = "cortex_m3",
2506
2507         .poll = cortex_m_poll,
2508         .arch_state = armv7m_arch_state,
2509
2510         .target_request_data = cortex_m_target_request_data,
2511
2512         .halt = cortex_m_halt,
2513         .resume = cortex_m_resume,
2514         .step = cortex_m_step,
2515
2516         .assert_reset = cortex_m_assert_reset,
2517         .deassert_reset = cortex_m_deassert_reset,
2518         .soft_reset_halt = cortex_m_soft_reset_halt,
2519
2520         .get_gdb_arch = arm_get_gdb_arch,
2521         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2522
2523         .read_memory = cortex_m_read_memory,
2524         .write_memory = cortex_m_write_memory,
2525         .checksum_memory = armv7m_checksum_memory,
2526         .blank_check_memory = armv7m_blank_check_memory,
2527
2528         .run_algorithm = armv7m_run_algorithm,
2529         .start_algorithm = armv7m_start_algorithm,
2530         .wait_algorithm = armv7m_wait_algorithm,
2531
2532         .add_breakpoint = cortex_m_add_breakpoint,
2533         .remove_breakpoint = cortex_m_remove_breakpoint,
2534         .add_watchpoint = cortex_m_add_watchpoint,
2535         .remove_watchpoint = cortex_m_remove_watchpoint,
2536
2537         .commands = cortex_m_command_handlers,
2538         .target_create = cortex_m_target_create,
2539         .target_jim_configure = adiv5_jim_configure,
2540         .init_target = cortex_m_init_target,
2541         .examine = cortex_m_examine,
2542         .deinit_target = cortex_m_deinit_target,
2543
2544         .profiling = cortex_m_profiling,
2545 };