1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
27 ***************************************************************************/
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_adi_v5.h"
38 #include "arm_disassembler.h"
40 #include "arm_opcodes.h"
41 #include "arm_semihosting.h"
42 #include <helper/time_support.h>
45 /* NOTE: most of this should work fine for the Cortex-M1 and
46 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 * Some differences: M0/M1 doesn't have FPB remapping or the
48 * DWT tracing/profiling support. (So the cycle counter will
49 * not be usable; the other stuff isn't currently used here.)
51 * Although there are some workarounds for errata seen only in r0p0
52 * silicon, such old parts are hard to find and thus not much tested
56 /* Timeout for register r/w */
57 #define DHCSR_S_REGRDY_TIMEOUT (500)
59 /* Supported Cortex-M Cores */
60 static const struct cortex_m_part_info cortex_m_parts[] = {
62 .partno = CORTEX_M0_PARTNO,
67 .partno = CORTEX_M0P_PARTNO,
72 .partno = CORTEX_M1_PARTNO,
77 .partno = CORTEX_M3_PARTNO,
80 .flags = CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
83 .partno = CORTEX_M4_PARTNO,
86 .flags = CORTEX_M_F_HAS_FPV4 | CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
89 .partno = CORTEX_M7_PARTNO,
92 .flags = CORTEX_M_F_HAS_FPV5,
95 .partno = CORTEX_M23_PARTNO,
100 .partno = CORTEX_M33_PARTNO,
101 .name = "Cortex-M33",
102 .arch = ARM_ARCH_V8M,
103 .flags = CORTEX_M_F_HAS_FPV5,
106 .partno = CORTEX_M35P_PARTNO,
107 .name = "Cortex-M35P",
108 .arch = ARM_ARCH_V8M,
109 .flags = CORTEX_M_F_HAS_FPV5,
112 .partno = CORTEX_M55_PARTNO,
113 .name = "Cortex-M55",
114 .arch = ARM_ARCH_V8M,
115 .flags = CORTEX_M_F_HAS_FPV5,
119 /* forward declarations */
120 static int cortex_m_store_core_reg_u32(struct target *target,
121 uint32_t num, uint32_t value);
122 static void cortex_m_dwt_free(struct target *target);
124 /** DCB DHCSR register contains S_RETIRE_ST and S_RESET_ST bits cleared
125 * on a read. Call this helper function each time DHCSR is read
126 * to preserve S_RESET_ST state in case of a reset event was detected.
128 static inline void cortex_m_cumulate_dhcsr_sticky(struct cortex_m_common *cortex_m,
131 cortex_m->dcb_dhcsr_cumulated_sticky |= dhcsr;
134 /** Read DCB DHCSR register to cortex_m->dcb_dhcsr and cumulate
135 * sticky bits in cortex_m->dcb_dhcsr_cumulated_sticky
137 static int cortex_m_read_dhcsr_atomic_sticky(struct target *target)
139 struct cortex_m_common *cortex_m = target_to_cm(target);
140 struct armv7m_common *armv7m = target_to_armv7m(target);
142 int retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
143 &cortex_m->dcb_dhcsr);
144 if (retval != ERROR_OK)
147 cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
151 static int cortex_m_load_core_reg_u32(struct target *target,
152 uint32_t regsel, uint32_t *value)
154 struct cortex_m_common *cortex_m = target_to_cm(target);
155 struct armv7m_common *armv7m = target_to_armv7m(target);
157 uint32_t dcrdr, tmp_value;
160 /* because the DCB_DCRDR is used for the emulated dcc channel
161 * we have to save/restore the DCB_DCRDR when used */
162 if (target->dbg_msg_enabled) {
163 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
164 if (retval != ERROR_OK)
168 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
169 if (retval != ERROR_OK)
172 /* check if value from register is ready and pre-read it */
175 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DHCSR,
176 &cortex_m->dcb_dhcsr);
177 if (retval != ERROR_OK)
179 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR,
181 if (retval != ERROR_OK)
183 cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
184 if (cortex_m->dcb_dhcsr & S_REGRDY)
186 if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
187 LOG_ERROR("Timeout waiting for DCRDR transfer ready");
188 return ERROR_TIMEOUT_REACHED;
195 if (target->dbg_msg_enabled) {
196 /* restore DCB_DCRDR - this needs to be in a separate
197 * transaction otherwise the emulated DCC channel breaks */
198 if (retval == ERROR_OK)
199 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
205 static int cortex_m_store_core_reg_u32(struct target *target,
206 uint32_t regsel, uint32_t value)
208 struct cortex_m_common *cortex_m = target_to_cm(target);
209 struct armv7m_common *armv7m = target_to_armv7m(target);
214 /* because the DCB_DCRDR is used for the emulated dcc channel
215 * we have to save/restore the DCB_DCRDR when used */
216 if (target->dbg_msg_enabled) {
217 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
218 if (retval != ERROR_OK)
222 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
223 if (retval != ERROR_OK)
226 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WNR);
227 if (retval != ERROR_OK)
230 /* check if value is written into register */
233 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
234 &cortex_m->dcb_dhcsr);
235 if (retval != ERROR_OK)
237 cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
238 if (cortex_m->dcb_dhcsr & S_REGRDY)
240 if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
241 LOG_ERROR("Timeout waiting for DCRDR transfer ready");
242 return ERROR_TIMEOUT_REACHED;
247 if (target->dbg_msg_enabled) {
248 /* restore DCB_DCRDR - this needs to be in a separate
249 * transaction otherwise the emulated DCC channel breaks */
250 if (retval == ERROR_OK)
251 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
257 static int cortex_m_write_debug_halt_mask(struct target *target,
258 uint32_t mask_on, uint32_t mask_off)
260 struct cortex_m_common *cortex_m = target_to_cm(target);
261 struct armv7m_common *armv7m = &cortex_m->armv7m;
263 /* mask off status bits */
264 cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
265 /* create new register mask */
266 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
268 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
271 static int cortex_m_set_maskints(struct target *target, bool mask)
273 struct cortex_m_common *cortex_m = target_to_cm(target);
274 if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
275 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
280 static int cortex_m_set_maskints_for_halt(struct target *target)
282 struct cortex_m_common *cortex_m = target_to_cm(target);
283 switch (cortex_m->isrmasking_mode) {
284 case CORTEX_M_ISRMASK_AUTO:
285 /* interrupts taken at resume, whether for step or run -> no mask */
286 return cortex_m_set_maskints(target, false);
288 case CORTEX_M_ISRMASK_OFF:
289 /* interrupts never masked */
290 return cortex_m_set_maskints(target, false);
292 case CORTEX_M_ISRMASK_ON:
293 /* interrupts always masked */
294 return cortex_m_set_maskints(target, true);
296 case CORTEX_M_ISRMASK_STEPONLY:
297 /* interrupts masked for single step only -> mask now if MASKINTS
298 * erratum, otherwise only mask before stepping */
299 return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
304 static int cortex_m_set_maskints_for_run(struct target *target)
306 switch (target_to_cm(target)->isrmasking_mode) {
307 case CORTEX_M_ISRMASK_AUTO:
308 /* interrupts taken at resume, whether for step or run -> no mask */
309 return cortex_m_set_maskints(target, false);
311 case CORTEX_M_ISRMASK_OFF:
312 /* interrupts never masked */
313 return cortex_m_set_maskints(target, false);
315 case CORTEX_M_ISRMASK_ON:
316 /* interrupts always masked */
317 return cortex_m_set_maskints(target, true);
319 case CORTEX_M_ISRMASK_STEPONLY:
320 /* interrupts masked for single step only -> no mask */
321 return cortex_m_set_maskints(target, false);
326 static int cortex_m_set_maskints_for_step(struct target *target)
328 switch (target_to_cm(target)->isrmasking_mode) {
329 case CORTEX_M_ISRMASK_AUTO:
330 /* the auto-interrupt should already be done -> mask */
331 return cortex_m_set_maskints(target, true);
333 case CORTEX_M_ISRMASK_OFF:
334 /* interrupts never masked */
335 return cortex_m_set_maskints(target, false);
337 case CORTEX_M_ISRMASK_ON:
338 /* interrupts always masked */
339 return cortex_m_set_maskints(target, true);
341 case CORTEX_M_ISRMASK_STEPONLY:
342 /* interrupts masked for single step only -> mask */
343 return cortex_m_set_maskints(target, true);
348 static int cortex_m_clear_halt(struct target *target)
350 struct cortex_m_common *cortex_m = target_to_cm(target);
351 struct armv7m_common *armv7m = &cortex_m->armv7m;
354 /* clear step if any */
355 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
357 /* Read Debug Fault Status Register */
358 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
359 if (retval != ERROR_OK)
362 /* Clear Debug Fault Status */
363 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
364 if (retval != ERROR_OK)
366 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
371 static int cortex_m_single_step_core(struct target *target)
373 struct cortex_m_common *cortex_m = target_to_cm(target);
376 /* Mask interrupts before clearing halt, if not done already. This avoids
377 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
378 * HALT can put the core into an unknown state.
380 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
381 retval = cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
382 if (retval != ERROR_OK)
385 retval = cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
386 if (retval != ERROR_OK)
390 /* restore dhcsr reg */
391 cortex_m_clear_halt(target);
396 static int cortex_m_enable_fpb(struct target *target)
398 int retval = target_write_u32(target, FP_CTRL, 3);
399 if (retval != ERROR_OK)
402 /* check the fpb is actually enabled */
404 retval = target_read_u32(target, FP_CTRL, &fpctrl);
405 if (retval != ERROR_OK)
414 static int cortex_m_endreset_event(struct target *target)
418 struct cortex_m_common *cortex_m = target_to_cm(target);
419 struct armv7m_common *armv7m = &cortex_m->armv7m;
420 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
421 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
422 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
424 /* REVISIT The four debug monitor bits are currently ignored... */
425 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
426 if (retval != ERROR_OK)
428 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
430 /* this register is used for emulated dcc channel */
431 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
432 if (retval != ERROR_OK)
435 retval = cortex_m_read_dhcsr_atomic_sticky(target);
436 if (retval != ERROR_OK)
439 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
440 /* Enable debug requests */
441 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
442 if (retval != ERROR_OK)
446 /* Restore proper interrupt masking setting for running CPU. */
447 cortex_m_set_maskints_for_run(target);
449 /* Enable features controlled by ITM and DWT blocks, and catch only
450 * the vectors we were told to pay attention to.
452 * Target firmware is responsible for all fault handling policy
453 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
454 * or manual updates to the NVIC SHCSR and CCR registers.
456 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
457 if (retval != ERROR_OK)
460 /* Paranoia: evidently some (early?) chips don't preserve all the
461 * debug state (including FPB, DWT, etc) across reset...
465 retval = cortex_m_enable_fpb(target);
466 if (retval != ERROR_OK) {
467 LOG_ERROR("Failed to enable the FPB");
471 cortex_m->fpb_enabled = true;
473 /* Restore FPB registers */
474 for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
475 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
476 if (retval != ERROR_OK)
480 /* Restore DWT registers */
481 for (unsigned int i = 0; i < cortex_m->dwt_num_comp; i++) {
482 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
484 if (retval != ERROR_OK)
486 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
488 if (retval != ERROR_OK)
490 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
491 dwt_list[i].function);
492 if (retval != ERROR_OK)
495 retval = dap_run(swjdp);
496 if (retval != ERROR_OK)
499 register_cache_invalidate(armv7m->arm.core_cache);
501 /* make sure we have latest dhcsr flags */
502 retval = cortex_m_read_dhcsr_atomic_sticky(target);
503 if (retval != ERROR_OK)
509 static int cortex_m_examine_debug_reason(struct target *target)
511 struct cortex_m_common *cortex_m = target_to_cm(target);
513 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
514 * only check the debug reason if we don't know it already */
516 if ((target->debug_reason != DBG_REASON_DBGRQ)
517 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
518 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
519 target->debug_reason = DBG_REASON_BREAKPOINT;
520 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
521 target->debug_reason = DBG_REASON_WPTANDBKPT;
522 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
523 target->debug_reason = DBG_REASON_WATCHPOINT;
524 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
525 target->debug_reason = DBG_REASON_BREAKPOINT;
526 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
527 target->debug_reason = DBG_REASON_DBGRQ;
529 target->debug_reason = DBG_REASON_UNDEFINED;
535 static int cortex_m_examine_exception_reason(struct target *target)
537 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
538 struct armv7m_common *armv7m = target_to_armv7m(target);
539 struct adiv5_dap *swjdp = armv7m->arm.dap;
542 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
543 if (retval != ERROR_OK)
545 switch (armv7m->exception_number) {
548 case 3: /* Hard Fault */
549 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
550 if (retval != ERROR_OK)
552 if (except_sr & 0x40000000) {
553 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
554 if (retval != ERROR_OK)
558 case 4: /* Memory Management */
559 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
560 if (retval != ERROR_OK)
562 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
563 if (retval != ERROR_OK)
566 case 5: /* Bus Fault */
567 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
568 if (retval != ERROR_OK)
570 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
571 if (retval != ERROR_OK)
574 case 6: /* Usage Fault */
575 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
576 if (retval != ERROR_OK)
579 case 7: /* Secure Fault */
580 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
581 if (retval != ERROR_OK)
583 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
584 if (retval != ERROR_OK)
587 case 11: /* SVCall */
589 case 12: /* Debug Monitor */
590 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
591 if (retval != ERROR_OK)
594 case 14: /* PendSV */
596 case 15: /* SysTick */
602 retval = dap_run(swjdp);
603 if (retval == ERROR_OK)
604 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
605 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
606 armv7m_exception_string(armv7m->exception_number),
607 shcsr, except_sr, cfsr, except_ar);
611 static int cortex_m_debug_entry(struct target *target)
616 struct cortex_m_common *cortex_m = target_to_cm(target);
617 struct armv7m_common *armv7m = &cortex_m->armv7m;
618 struct arm *arm = &armv7m->arm;
623 /* Do this really early to minimize the window where the MASKINTS erratum
624 * can pile up pending interrupts. */
625 cortex_m_set_maskints_for_halt(target);
627 cortex_m_clear_halt(target);
629 retval = cortex_m_read_dhcsr_atomic_sticky(target);
630 if (retval != ERROR_OK)
633 retval = armv7m->examine_debug_reason(target);
634 if (retval != ERROR_OK)
637 /* examine PE security state */
638 bool secure_state = false;
639 if (armv7m->arm.arch == ARM_ARCH_V8M) {
642 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
643 if (retval != ERROR_OK)
646 secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
649 /* Examine target state and mode
650 * First load register accessible through core debug port */
651 int num_regs = arm->core_cache->num_regs;
653 for (i = 0; i < num_regs; i++) {
654 r = &armv7m->arm.core_cache->reg_list[i];
655 if (r->exist && !r->valid)
656 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
660 xPSR = buf_get_u32(r->value, 0, 32);
662 /* Are we in an exception handler */
664 armv7m->exception_number = (xPSR & 0x1FF);
666 arm->core_mode = ARM_MODE_HANDLER;
667 arm->map = armv7m_msp_reg_map;
669 unsigned control = buf_get_u32(arm->core_cache
670 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
672 /* is this thread privileged? */
673 arm->core_mode = control & 1
674 ? ARM_MODE_USER_THREAD
677 /* which stack is it using? */
679 arm->map = armv7m_psp_reg_map;
681 arm->map = armv7m_msp_reg_map;
683 armv7m->exception_number = 0;
686 if (armv7m->exception_number)
687 cortex_m_examine_exception_reason(target);
689 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
690 arm_mode_name(arm->core_mode),
691 buf_get_u32(arm->pc->value, 0, 32),
692 secure_state ? "Secure" : "Non-Secure",
693 target_state_name(target));
695 if (armv7m->post_debug_entry) {
696 retval = armv7m->post_debug_entry(target);
697 if (retval != ERROR_OK)
704 static int cortex_m_poll(struct target *target)
706 int detected_failure = ERROR_OK;
707 int retval = ERROR_OK;
708 enum target_state prev_target_state = target->state;
709 struct cortex_m_common *cortex_m = target_to_cm(target);
710 struct armv7m_common *armv7m = &cortex_m->armv7m;
712 /* Read from Debug Halting Control and Status Register */
713 retval = cortex_m_read_dhcsr_atomic_sticky(target);
714 if (retval != ERROR_OK) {
715 target->state = TARGET_UNKNOWN;
719 /* Recover from lockup. See ARMv7-M architecture spec,
720 * section B1.5.15 "Unrecoverable exception cases".
722 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
723 LOG_ERROR("%s -- clearing lockup after double fault",
724 target_name(target));
725 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
726 target->debug_reason = DBG_REASON_DBGRQ;
728 /* We have to execute the rest (the "finally" equivalent, but
729 * still throw this exception again).
731 detected_failure = ERROR_FAIL;
733 /* refresh status bits */
734 retval = cortex_m_read_dhcsr_atomic_sticky(target);
735 if (retval != ERROR_OK)
739 if (cortex_m->dcb_dhcsr_cumulated_sticky & S_RESET_ST) {
740 cortex_m->dcb_dhcsr_cumulated_sticky &= ~S_RESET_ST;
741 if (target->state != TARGET_RESET) {
742 target->state = TARGET_RESET;
743 LOG_INFO("%s: external reset detected", target_name(target));
748 if (target->state == TARGET_RESET) {
749 /* Cannot switch context while running so endreset is
750 * called with target->state == TARGET_RESET
752 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
753 cortex_m->dcb_dhcsr);
754 retval = cortex_m_endreset_event(target);
755 if (retval != ERROR_OK) {
756 target->state = TARGET_UNKNOWN;
759 target->state = TARGET_RUNNING;
760 prev_target_state = TARGET_RUNNING;
763 if (cortex_m->dcb_dhcsr & S_HALT) {
764 target->state = TARGET_HALTED;
766 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
767 retval = cortex_m_debug_entry(target);
768 if (retval != ERROR_OK)
771 if (arm_semihosting(target, &retval) != 0)
774 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
776 if (prev_target_state == TARGET_DEBUG_RUNNING) {
778 retval = cortex_m_debug_entry(target);
779 if (retval != ERROR_OK)
782 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
786 if (target->state == TARGET_UNKNOWN) {
787 /* Check if processor is retiring instructions or sleeping.
788 * Unlike S_RESET_ST here we test if the target *is* running now,
789 * not if it has been running (possibly in the past). Instructions are
790 * typically processed much faster than OpenOCD polls DHCSR so S_RETIRE_ST
791 * is read always 1. That's the reason not to use dcb_dhcsr_cumulated_sticky.
793 if (cortex_m->dcb_dhcsr & S_RETIRE_ST || cortex_m->dcb_dhcsr & S_SLEEP) {
794 target->state = TARGET_RUNNING;
799 /* Check that target is truly halted, since the target could be resumed externally */
800 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
801 /* registers are now invalid */
802 register_cache_invalidate(armv7m->arm.core_cache);
804 target->state = TARGET_RUNNING;
805 LOG_WARNING("%s: external resume detected", target_name(target));
806 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
810 /* Did we detect a failure condition that we cleared? */
811 if (detected_failure != ERROR_OK)
812 retval = detected_failure;
816 static int cortex_m_halt(struct target *target)
818 LOG_DEBUG("target->state: %s",
819 target_state_name(target));
821 if (target->state == TARGET_HALTED) {
822 LOG_DEBUG("target was already halted");
826 if (target->state == TARGET_UNKNOWN)
827 LOG_WARNING("target was in unknown state when halt was requested");
829 if (target->state == TARGET_RESET) {
830 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
831 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
832 return ERROR_TARGET_FAILURE;
834 /* we came here in a reset_halt or reset_init sequence
835 * debug entry was already prepared in cortex_m3_assert_reset()
837 target->debug_reason = DBG_REASON_DBGRQ;
843 /* Write to Debug Halting Control and Status Register */
844 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
846 /* Do this really early to minimize the window where the MASKINTS erratum
847 * can pile up pending interrupts. */
848 cortex_m_set_maskints_for_halt(target);
850 target->debug_reason = DBG_REASON_DBGRQ;
855 static int cortex_m_soft_reset_halt(struct target *target)
857 struct cortex_m_common *cortex_m = target_to_cm(target);
858 struct armv7m_common *armv7m = &cortex_m->armv7m;
859 int retval, timeout = 0;
861 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
862 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
863 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
864 * core, not the peripherals */
865 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
867 if (!cortex_m->vectreset_supported) {
868 LOG_ERROR("VECTRESET is not supported on this Cortex-M core");
873 retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
874 if (retval != ERROR_OK)
877 /* Enter debug state on reset; restore DEMCR in endreset_event() */
878 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
879 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
880 if (retval != ERROR_OK)
883 /* Request a core-only reset */
884 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
885 AIRCR_VECTKEY | AIRCR_VECTRESET);
886 if (retval != ERROR_OK)
888 target->state = TARGET_RESET;
890 /* registers are now invalid */
891 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
893 while (timeout < 100) {
894 retval = cortex_m_read_dhcsr_atomic_sticky(target);
895 if (retval == ERROR_OK) {
896 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
897 &cortex_m->nvic_dfsr);
898 if (retval != ERROR_OK)
900 if ((cortex_m->dcb_dhcsr & S_HALT)
901 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
902 LOG_DEBUG("system reset-halted, DHCSR 0x%08" PRIx32 ", DFSR 0x%08" PRIx32,
903 cortex_m->dcb_dhcsr, cortex_m->nvic_dfsr);
904 cortex_m_poll(target);
905 /* FIXME restore user's vector catch config */
908 LOG_DEBUG("waiting for system reset-halt, "
909 "DHCSR 0x%08" PRIx32 ", %d ms",
910 cortex_m->dcb_dhcsr, timeout);
919 void cortex_m_enable_breakpoints(struct target *target)
921 struct breakpoint *breakpoint = target->breakpoints;
923 /* set any pending breakpoints */
925 if (!breakpoint->set)
926 cortex_m_set_breakpoint(target, breakpoint);
927 breakpoint = breakpoint->next;
931 static int cortex_m_resume(struct target *target, int current,
932 target_addr_t address, int handle_breakpoints, int debug_execution)
934 struct armv7m_common *armv7m = target_to_armv7m(target);
935 struct breakpoint *breakpoint = NULL;
939 if (target->state != TARGET_HALTED) {
940 LOG_WARNING("target not halted");
941 return ERROR_TARGET_NOT_HALTED;
944 if (!debug_execution) {
945 target_free_all_working_areas(target);
946 cortex_m_enable_breakpoints(target);
947 cortex_m_enable_watchpoints(target);
950 if (debug_execution) {
951 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
953 /* Disable interrupts */
954 /* We disable interrupts in the PRIMASK register instead of
955 * masking with C_MASKINTS. This is probably the same issue
956 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
957 * in parallel with disabled interrupts can cause local faults
960 * This breaks non-debug (application) execution if not
961 * called from armv7m_start_algorithm() which saves registers.
963 buf_set_u32(r->value, 0, 1, 1);
967 /* Make sure we are in Thumb mode, set xPSR.T bit */
968 /* armv7m_start_algorithm() initializes entire xPSR register.
969 * This duplicity handles the case when cortex_m_resume()
970 * is used with the debug_execution flag directly,
971 * not called through armv7m_start_algorithm().
973 r = armv7m->arm.cpsr;
974 buf_set_u32(r->value, 24, 1, 1);
979 /* current = 1: continue on current pc, otherwise continue at <address> */
982 buf_set_u32(r->value, 0, 32, address);
987 /* if we halted last time due to a bkpt instruction
988 * then we have to manually step over it, otherwise
989 * the core will break again */
991 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
993 armv7m_maybe_skip_bkpt_inst(target, NULL);
995 resume_pc = buf_get_u32(r->value, 0, 32);
997 armv7m_restore_context(target);
999 /* the front-end may request us not to handle breakpoints */
1000 if (handle_breakpoints) {
1001 /* Single step past breakpoint at current address */
1002 breakpoint = breakpoint_find(target, resume_pc);
1004 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
1005 breakpoint->address,
1006 breakpoint->unique_id);
1007 cortex_m_unset_breakpoint(target, breakpoint);
1008 cortex_m_single_step_core(target);
1009 cortex_m_set_breakpoint(target, breakpoint);
1014 cortex_m_set_maskints_for_run(target);
1015 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1017 target->debug_reason = DBG_REASON_NOTHALTED;
1019 /* registers are now invalid */
1020 register_cache_invalidate(armv7m->arm.core_cache);
1022 if (!debug_execution) {
1023 target->state = TARGET_RUNNING;
1024 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1025 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
1027 target->state = TARGET_DEBUG_RUNNING;
1028 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1029 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
1035 /* int irqstepcount = 0; */
1036 static int cortex_m_step(struct target *target, int current,
1037 target_addr_t address, int handle_breakpoints)
1039 struct cortex_m_common *cortex_m = target_to_cm(target);
1040 struct armv7m_common *armv7m = &cortex_m->armv7m;
1041 struct breakpoint *breakpoint = NULL;
1042 struct reg *pc = armv7m->arm.pc;
1043 bool bkpt_inst_found = false;
1045 bool isr_timed_out = false;
1047 if (target->state != TARGET_HALTED) {
1048 LOG_WARNING("target not halted");
1049 return ERROR_TARGET_NOT_HALTED;
1052 /* current = 1: continue on current pc, otherwise continue at <address> */
1054 buf_set_u32(pc->value, 0, 32, address);
1059 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
1061 /* the front-end may request us not to handle breakpoints */
1062 if (handle_breakpoints) {
1063 breakpoint = breakpoint_find(target, pc_value);
1065 cortex_m_unset_breakpoint(target, breakpoint);
1068 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
1070 target->debug_reason = DBG_REASON_SINGLESTEP;
1072 armv7m_restore_context(target);
1074 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1076 /* if no bkpt instruction is found at pc then we can perform
1077 * a normal step, otherwise we have to manually step over the bkpt
1078 * instruction - as such simulate a step */
1079 if (bkpt_inst_found == false) {
1080 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
1081 /* Automatic ISR masking mode off: Just step over the next
1082 * instruction, with interrupts on or off as appropriate. */
1083 cortex_m_set_maskints_for_step(target);
1084 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1086 /* Process interrupts during stepping in a way they don't interfere
1091 * Set a temporary break point at the current pc and let the core run
1092 * with interrupts enabled. Pending interrupts get served and we run
1093 * into the breakpoint again afterwards. Then we step over the next
1094 * instruction with interrupts disabled.
1096 * If the pending interrupts don't complete within time, we leave the
1097 * core running. This may happen if the interrupts trigger faster
1098 * than the core can process them or the handler doesn't return.
1100 * If no more breakpoints are available we simply do a step with
1101 * interrupts enabled.
1107 * If a break point is already set on the lower half word then a break point on
1108 * the upper half word will not break again when the core is restarted. So we
1109 * just step over the instruction with interrupts disabled.
1111 * The documentation has no information about this, it was found by observation
1112 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
1113 * suffer from this problem.
1115 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
1116 * address has it always cleared. The former is done to indicate thumb mode
1120 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
1121 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
1122 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
1123 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1124 /* Re-enable interrupts if appropriate */
1125 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1126 cortex_m_set_maskints_for_halt(target);
1129 /* Set a temporary break point */
1131 retval = cortex_m_set_breakpoint(target, breakpoint);
1133 enum breakpoint_type type = BKPT_HARD;
1134 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
1135 /* FPB rev.1 cannot handle such addr, try BKPT instr */
1138 retval = breakpoint_add(target, pc_value, 2, type);
1141 bool tmp_bp_set = (retval == ERROR_OK);
1143 /* No more breakpoints left, just do a step */
1145 cortex_m_set_maskints_for_step(target);
1146 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1147 /* Re-enable interrupts if appropriate */
1148 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1149 cortex_m_set_maskints_for_halt(target);
1151 /* Start the core */
1152 LOG_DEBUG("Starting core to serve pending interrupts");
1153 int64_t t_start = timeval_ms();
1154 cortex_m_set_maskints_for_run(target);
1155 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
1157 /* Wait for pending handlers to complete or timeout */
1159 retval = cortex_m_read_dhcsr_atomic_sticky(target);
1160 if (retval != ERROR_OK) {
1161 target->state = TARGET_UNKNOWN;
1164 isr_timed_out = ((timeval_ms() - t_start) > 500);
1165 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1167 /* only remove breakpoint if we created it */
1169 cortex_m_unset_breakpoint(target, breakpoint);
1171 /* Remove the temporary breakpoint */
1172 breakpoint_remove(target, pc_value);
1175 if (isr_timed_out) {
1176 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1177 "leaving target running");
1179 /* Step over next instruction with interrupts disabled */
1180 cortex_m_set_maskints_for_step(target);
1181 cortex_m_write_debug_halt_mask(target,
1182 C_HALT | C_MASKINTS,
1184 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1185 /* Re-enable interrupts if appropriate */
1186 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1187 cortex_m_set_maskints_for_halt(target);
1194 retval = cortex_m_read_dhcsr_atomic_sticky(target);
1195 if (retval != ERROR_OK)
1198 /* registers are now invalid */
1199 register_cache_invalidate(armv7m->arm.core_cache);
1202 cortex_m_set_breakpoint(target, breakpoint);
1204 if (isr_timed_out) {
1205 /* Leave the core running. The user has to stop execution manually. */
1206 target->debug_reason = DBG_REASON_NOTHALTED;
1207 target->state = TARGET_RUNNING;
1211 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1212 " nvic_icsr = 0x%" PRIx32,
1213 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1215 retval = cortex_m_debug_entry(target);
1216 if (retval != ERROR_OK)
1218 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1220 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1221 " nvic_icsr = 0x%" PRIx32,
1222 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1227 static int cortex_m_assert_reset(struct target *target)
1229 struct cortex_m_common *cortex_m = target_to_cm(target);
1230 struct armv7m_common *armv7m = &cortex_m->armv7m;
1231 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1233 LOG_DEBUG("target->state: %s",
1234 target_state_name(target));
1236 enum reset_types jtag_reset_config = jtag_get_reset_config();
1238 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1239 /* allow scripts to override the reset event */
1241 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1242 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1243 target->state = TARGET_RESET;
1248 /* some cores support connecting while srst is asserted
1249 * use that mode is it has been configured */
1251 bool srst_asserted = false;
1253 if (!target_was_examined(target)) {
1254 if (jtag_reset_config & RESET_HAS_SRST) {
1255 adapter_assert_reset();
1256 if (target->reset_halt)
1257 LOG_ERROR("Target not examined, will not halt after reset!");
1260 LOG_ERROR("Target not examined, reset NOT asserted!");
1265 if ((jtag_reset_config & RESET_HAS_SRST) &&
1266 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1267 adapter_assert_reset();
1268 srst_asserted = true;
1271 /* Enable debug requests */
1272 int retval = cortex_m_read_dhcsr_atomic_sticky(target);
1274 /* Store important errors instead of failing and proceed to reset assert */
1276 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1277 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1279 /* If the processor is sleeping in a WFI or WFE instruction, the
1280 * C_HALT bit must be asserted to regain control */
1281 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1282 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1284 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1285 /* Ignore less important errors */
1287 if (!target->reset_halt) {
1288 /* Set/Clear C_MASKINTS in a separate operation */
1289 cortex_m_set_maskints_for_run(target);
1291 /* clear any debug flags before resuming */
1292 cortex_m_clear_halt(target);
1294 /* clear C_HALT in dhcsr reg */
1295 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1297 /* Halt in debug on reset; endreset_event() restores DEMCR.
1299 * REVISIT catching BUSERR presumably helps to defend against
1300 * bad vector table entries. Should this include MMERR or
1304 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1305 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1306 if (retval != ERROR_OK || retval2 != ERROR_OK)
1307 LOG_INFO("AP write error, reset will not halt");
1310 if (jtag_reset_config & RESET_HAS_SRST) {
1311 /* default to asserting srst */
1313 adapter_assert_reset();
1315 /* srst is asserted, ignore AP access errors */
1318 /* Use a standard Cortex-M3 software reset mechanism.
1319 * We default to using VECTRESET as it is supported on all current cores
1320 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1321 * This has the disadvantage of not resetting the peripherals, so a
1322 * reset-init event handler is needed to perform any peripheral resets.
1324 if (!cortex_m->vectreset_supported
1325 && reset_config == CORTEX_M_RESET_VECTRESET) {
1326 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1327 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1328 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1331 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1332 ? "SYSRESETREQ" : "VECTRESET");
1334 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1335 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1336 "handler to reset any peripherals or configure hardware srst support.");
1340 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1341 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1342 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1343 if (retval3 != ERROR_OK)
1344 LOG_DEBUG("Ignoring AP write error right after reset");
1346 retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1347 if (retval3 != ERROR_OK) {
1348 LOG_ERROR("DP initialisation failed");
1349 /* The error return value must not be propagated in this case.
1350 * SYSRESETREQ or VECTRESET have been possibly triggered
1351 * so reset processing should continue */
1353 /* I do not know why this is necessary, but it
1354 * fixes strange effects (step/resume cause NMI
1355 * after reset) on LM3S6918 -- Michael Schwingen
1358 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1362 target->state = TARGET_RESET;
1365 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1367 /* now return stored error code if any */
1368 if (retval != ERROR_OK)
1371 if (target->reset_halt) {
1372 retval = target_halt(target);
1373 if (retval != ERROR_OK)
1380 static int cortex_m_deassert_reset(struct target *target)
1382 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1384 LOG_DEBUG("target->state: %s",
1385 target_state_name(target));
1387 /* deassert reset lines */
1388 adapter_deassert_reset();
1390 enum reset_types jtag_reset_config = jtag_get_reset_config();
1392 if ((jtag_reset_config & RESET_HAS_SRST) &&
1393 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1394 target_was_examined(target)) {
1396 int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1397 if (retval != ERROR_OK) {
1398 LOG_ERROR("DP initialisation failed");
1406 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1409 unsigned int fp_num = 0;
1410 struct cortex_m_common *cortex_m = target_to_cm(target);
1411 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1413 if (breakpoint->set) {
1414 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1418 if (breakpoint->type == BKPT_HARD) {
1419 uint32_t fpcr_value;
1420 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1422 if (fp_num >= cortex_m->fp_num_code) {
1423 LOG_ERROR("Can not find free FPB Comparator!");
1424 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1426 breakpoint->set = fp_num + 1;
1427 fpcr_value = breakpoint->address | 1;
1428 if (cortex_m->fp_rev == 0) {
1429 if (breakpoint->address > 0x1FFFFFFF) {
1430 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1434 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1435 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1436 } else if (cortex_m->fp_rev > 1) {
1437 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1440 comparator_list[fp_num].used = true;
1441 comparator_list[fp_num].fpcr_value = fpcr_value;
1442 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1443 comparator_list[fp_num].fpcr_value);
1444 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1446 comparator_list[fp_num].fpcr_value);
1447 if (!cortex_m->fpb_enabled) {
1448 LOG_DEBUG("FPB wasn't enabled, do it now");
1449 retval = cortex_m_enable_fpb(target);
1450 if (retval != ERROR_OK) {
1451 LOG_ERROR("Failed to enable the FPB");
1455 cortex_m->fpb_enabled = true;
1457 } else if (breakpoint->type == BKPT_SOFT) {
1460 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1461 * semihosting; don't use that. Otherwise the BKPT
1462 * parameter is arbitrary.
1464 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1465 retval = target_read_memory(target,
1466 breakpoint->address & 0xFFFFFFFE,
1467 breakpoint->length, 1,
1468 breakpoint->orig_instr);
1469 if (retval != ERROR_OK)
1471 retval = target_write_memory(target,
1472 breakpoint->address & 0xFFFFFFFE,
1473 breakpoint->length, 1,
1475 if (retval != ERROR_OK)
1477 breakpoint->set = true;
1480 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1481 breakpoint->unique_id,
1482 (int)(breakpoint->type),
1483 breakpoint->address,
1490 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1493 struct cortex_m_common *cortex_m = target_to_cm(target);
1494 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1496 if (breakpoint->set <= 0) {
1497 LOG_WARNING("breakpoint not set");
1501 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1502 breakpoint->unique_id,
1503 (int)(breakpoint->type),
1504 breakpoint->address,
1508 if (breakpoint->type == BKPT_HARD) {
1509 unsigned int fp_num = breakpoint->set - 1;
1510 if (fp_num >= cortex_m->fp_num_code) {
1511 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1514 comparator_list[fp_num].used = false;
1515 comparator_list[fp_num].fpcr_value = 0;
1516 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1517 comparator_list[fp_num].fpcr_value);
1519 /* restore original instruction (kept in target endianness) */
1520 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1521 breakpoint->length, 1,
1522 breakpoint->orig_instr);
1523 if (retval != ERROR_OK)
1526 breakpoint->set = false;
1531 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1533 if (breakpoint->length == 3) {
1534 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1535 breakpoint->length = 2;
1538 if ((breakpoint->length != 2)) {
1539 LOG_INFO("only breakpoints of two bytes length supported");
1540 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1543 return cortex_m_set_breakpoint(target, breakpoint);
1546 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1548 if (!breakpoint->set)
1551 return cortex_m_unset_breakpoint(target, breakpoint);
1554 static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1556 unsigned int dwt_num = 0;
1557 struct cortex_m_common *cortex_m = target_to_cm(target);
1559 /* REVISIT Don't fully trust these "not used" records ... users
1560 * may set up breakpoints by hand, e.g. dual-address data value
1561 * watchpoint using comparator #1; comparator #0 matching cycle
1562 * count; send data trace info through ITM and TPIU; etc
1564 struct cortex_m_dwt_comparator *comparator;
1566 for (comparator = cortex_m->dwt_comparator_list;
1567 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1568 comparator++, dwt_num++)
1570 if (dwt_num >= cortex_m->dwt_num_comp) {
1571 LOG_ERROR("Can not find free DWT Comparator");
1574 comparator->used = true;
1575 watchpoint->set = dwt_num + 1;
1577 comparator->comp = watchpoint->address;
1578 target_write_u32(target, comparator->dwt_comparator_address + 0,
1581 if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1582 uint32_t mask = 0, temp;
1584 /* watchpoint params were validated earlier */
1585 temp = watchpoint->length;
1592 comparator->mask = mask;
1593 target_write_u32(target, comparator->dwt_comparator_address + 4,
1596 switch (watchpoint->rw) {
1598 comparator->function = 5;
1601 comparator->function = 6;
1604 comparator->function = 7;
1608 uint32_t data_size = watchpoint->length >> 1;
1609 comparator->mask = (watchpoint->length >> 1) | 1;
1611 switch (watchpoint->rw) {
1613 comparator->function = 4;
1616 comparator->function = 5;
1619 comparator->function = 6;
1622 comparator->function = comparator->function | (1 << 4) |
1626 target_write_u32(target, comparator->dwt_comparator_address + 8,
1627 comparator->function);
1629 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1630 watchpoint->unique_id, dwt_num,
1631 (unsigned) comparator->comp,
1632 (unsigned) comparator->mask,
1633 (unsigned) comparator->function);
1637 static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1639 struct cortex_m_common *cortex_m = target_to_cm(target);
1640 struct cortex_m_dwt_comparator *comparator;
1642 if (watchpoint->set <= 0) {
1643 LOG_WARNING("watchpoint (wpid: %d) not set",
1644 watchpoint->unique_id);
1648 unsigned int dwt_num = watchpoint->set - 1;
1650 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1651 watchpoint->unique_id, dwt_num,
1652 (unsigned) watchpoint->address);
1654 if (dwt_num >= cortex_m->dwt_num_comp) {
1655 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1659 comparator = cortex_m->dwt_comparator_list + dwt_num;
1660 comparator->used = false;
1661 comparator->function = 0;
1662 target_write_u32(target, comparator->dwt_comparator_address + 8,
1663 comparator->function);
1665 watchpoint->set = false;
1670 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1672 struct cortex_m_common *cortex_m = target_to_cm(target);
1674 if (cortex_m->dwt_comp_available < 1) {
1675 LOG_DEBUG("no comparators?");
1676 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1679 /* hardware doesn't support data value masking */
1680 if (watchpoint->mask != ~(uint32_t)0) {
1681 LOG_DEBUG("watchpoint value masks not supported");
1682 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1685 /* hardware allows address masks of up to 32K */
1688 for (mask = 0; mask < 16; mask++) {
1689 if ((1u << mask) == watchpoint->length)
1693 LOG_DEBUG("unsupported watchpoint length");
1694 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1696 if (watchpoint->address & ((1 << mask) - 1)) {
1697 LOG_DEBUG("watchpoint address is unaligned");
1698 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1701 /* Caller doesn't seem to be able to describe watching for data
1702 * values of zero; that flags "no value".
1704 * REVISIT This DWT may well be able to watch for specific data
1705 * values. Requires comparator #1 to set DATAVMATCH and match
1706 * the data, and another comparator (DATAVADDR0) matching addr.
1708 if (watchpoint->value) {
1709 LOG_DEBUG("data value watchpoint not YET supported");
1710 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1713 cortex_m->dwt_comp_available--;
1714 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1719 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1721 struct cortex_m_common *cortex_m = target_to_cm(target);
1723 /* REVISIT why check? DWT can be updated with core running ... */
1724 if (target->state != TARGET_HALTED) {
1725 LOG_WARNING("target not halted");
1726 return ERROR_TARGET_NOT_HALTED;
1729 if (watchpoint->set)
1730 cortex_m_unset_watchpoint(target, watchpoint);
1732 cortex_m->dwt_comp_available++;
1733 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1738 int cortex_m_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1740 if (target->debug_reason != DBG_REASON_WATCHPOINT)
1743 struct cortex_m_common *cortex_m = target_to_cm(target);
1745 for (struct watchpoint *wp = target->watchpoints; wp; wp = wp->next) {
1749 unsigned int dwt_num = wp->set - 1;
1750 struct cortex_m_dwt_comparator *comparator = cortex_m->dwt_comparator_list + dwt_num;
1752 uint32_t dwt_function;
1753 int retval = target_read_u32(target, comparator->dwt_comparator_address + 8, &dwt_function);
1754 if (retval != ERROR_OK)
1757 /* check the MATCHED bit */
1758 if (dwt_function & BIT(24)) {
1759 *hit_watchpoint = wp;
1767 void cortex_m_enable_watchpoints(struct target *target)
1769 struct watchpoint *watchpoint = target->watchpoints;
1771 /* set any pending watchpoints */
1772 while (watchpoint) {
1773 if (!watchpoint->set)
1774 cortex_m_set_watchpoint(target, watchpoint);
1775 watchpoint = watchpoint->next;
1779 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1780 uint32_t size, uint32_t count, uint8_t *buffer)
1782 struct armv7m_common *armv7m = target_to_armv7m(target);
1784 if (armv7m->arm.arch == ARM_ARCH_V6M) {
1785 /* armv6m does not handle unaligned memory access */
1786 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1787 return ERROR_TARGET_UNALIGNED_ACCESS;
1790 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1793 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1794 uint32_t size, uint32_t count, const uint8_t *buffer)
1796 struct armv7m_common *armv7m = target_to_armv7m(target);
1798 if (armv7m->arm.arch == ARM_ARCH_V6M) {
1799 /* armv6m does not handle unaligned memory access */
1800 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1801 return ERROR_TARGET_UNALIGNED_ACCESS;
1804 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1807 static int cortex_m_init_target(struct command_context *cmd_ctx,
1808 struct target *target)
1810 armv7m_build_reg_cache(target);
1811 arm_semihosting_init(target);
1815 void cortex_m_deinit_target(struct target *target)
1817 struct cortex_m_common *cortex_m = target_to_cm(target);
1819 free(cortex_m->fp_comparator_list);
1821 cortex_m_dwt_free(target);
1822 armv7m_free_reg_cache(target);
1824 free(target->private_config);
1828 int cortex_m_profiling(struct target *target, uint32_t *samples,
1829 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1831 struct timeval timeout, now;
1832 struct armv7m_common *armv7m = target_to_armv7m(target);
1836 retval = target_read_u32(target, DWT_PCSR, ®_value);
1837 if (retval != ERROR_OK) {
1838 LOG_ERROR("Error while reading PCSR");
1841 if (reg_value == 0) {
1842 LOG_INFO("PCSR sampling not supported on this processor.");
1843 return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
1846 gettimeofday(&timeout, NULL);
1847 timeval_add_time(&timeout, seconds, 0);
1849 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1851 /* Make sure the target is running */
1852 target_poll(target);
1853 if (target->state == TARGET_HALTED)
1854 retval = target_resume(target, 1, 0, 0, 0);
1856 if (retval != ERROR_OK) {
1857 LOG_ERROR("Error while resuming target");
1861 uint32_t sample_count = 0;
1864 if (armv7m && armv7m->debug_ap) {
1865 uint32_t read_count = max_num_samples - sample_count;
1866 if (read_count > 1024)
1869 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1870 (void *)&samples[sample_count],
1871 4, read_count, DWT_PCSR);
1872 sample_count += read_count;
1874 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1877 if (retval != ERROR_OK) {
1878 LOG_ERROR("Error while reading PCSR");
1883 gettimeofday(&now, NULL);
1884 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1885 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1890 *num_samples = sample_count;
1895 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1896 * on r/w if the core is not running, and clear on resume or reset ... or
1897 * at least, in a post_restore_context() method.
1900 struct dwt_reg_state {
1901 struct target *target;
1903 uint8_t value[4]; /* scratch/cache */
1906 static int cortex_m_dwt_get_reg(struct reg *reg)
1908 struct dwt_reg_state *state = reg->arch_info;
1911 int retval = target_read_u32(state->target, state->addr, &tmp);
1912 if (retval != ERROR_OK)
1915 buf_set_u32(state->value, 0, 32, tmp);
1919 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1921 struct dwt_reg_state *state = reg->arch_info;
1923 return target_write_u32(state->target, state->addr,
1924 buf_get_u32(buf, 0, reg->size));
1933 static const struct dwt_reg dwt_base_regs[] = {
1934 { DWT_CTRL, "dwt_ctrl", 32, },
1935 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1936 * increments while the core is asleep.
1938 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1939 /* plus some 8 bit counters, useful for profiling with TPIU */
1942 static const struct dwt_reg dwt_comp[] = {
1943 #define DWT_COMPARATOR(i) \
1944 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1945 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1946 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1963 #undef DWT_COMPARATOR
1966 static const struct reg_arch_type dwt_reg_type = {
1967 .get = cortex_m_dwt_get_reg,
1968 .set = cortex_m_dwt_set_reg,
1971 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1973 struct dwt_reg_state *state;
1975 state = calloc(1, sizeof(*state));
1978 state->addr = d->addr;
1983 r->value = state->value;
1984 r->arch_info = state;
1985 r->type = &dwt_reg_type;
1988 static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1991 struct reg_cache *cache;
1992 struct cortex_m_dwt_comparator *comparator;
1995 target_read_u32(target, DWT_CTRL, &dwtcr);
1996 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1998 LOG_DEBUG("no DWT");
2002 target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
2003 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
2005 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
2006 cm->dwt_comp_available = cm->dwt_num_comp;
2007 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
2008 sizeof(struct cortex_m_dwt_comparator));
2009 if (!cm->dwt_comparator_list) {
2011 cm->dwt_num_comp = 0;
2012 LOG_ERROR("out of mem");
2016 cache = calloc(1, sizeof(*cache));
2019 free(cm->dwt_comparator_list);
2022 cache->name = "Cortex-M DWT registers";
2023 cache->num_regs = 2 + cm->dwt_num_comp * 3;
2024 cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
2025 if (!cache->reg_list) {
2030 for (reg = 0; reg < 2; reg++)
2031 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2032 dwt_base_regs + reg);
2034 comparator = cm->dwt_comparator_list;
2035 for (unsigned int i = 0; i < cm->dwt_num_comp; i++, comparator++) {
2038 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
2039 for (j = 0; j < 3; j++, reg++)
2040 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2041 dwt_comp + 3 * i + j);
2043 /* make sure we clear any watchpoints enabled on the target */
2044 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
2047 *register_get_last_cache_p(&target->reg_cache) = cache;
2048 cm->dwt_cache = cache;
2050 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
2051 dwtcr, cm->dwt_num_comp,
2052 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
2054 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2055 * implement single-address data value watchpoints ... so we
2056 * won't need to check it later, when asked to set one up.
2060 static void cortex_m_dwt_free(struct target *target)
2062 struct cortex_m_common *cm = target_to_cm(target);
2063 struct reg_cache *cache = cm->dwt_cache;
2065 free(cm->dwt_comparator_list);
2066 cm->dwt_comparator_list = NULL;
2067 cm->dwt_num_comp = 0;
2070 register_unlink_cache(&target->reg_cache, cache);
2072 if (cache->reg_list) {
2073 for (size_t i = 0; i < cache->num_regs; i++)
2074 free(cache->reg_list[i].arch_info);
2075 free(cache->reg_list);
2079 cm->dwt_cache = NULL;
2082 #define MVFR0 0xe000ef40
2083 #define MVFR1 0xe000ef44
2085 #define MVFR0_DEFAULT_M4 0x10110021
2086 #define MVFR1_DEFAULT_M4 0x11000011
2088 #define MVFR0_DEFAULT_M7_SP 0x10110021
2089 #define MVFR0_DEFAULT_M7_DP 0x10110221
2090 #define MVFR1_DEFAULT_M7_SP 0x11000011
2091 #define MVFR1_DEFAULT_M7_DP 0x12000011
2093 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
2094 struct adiv5_ap **debug_ap)
2096 if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
2099 return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
2102 int cortex_m_examine(struct target *target)
2105 uint32_t cpuid, fpcr, mvfr0, mvfr1;
2106 struct cortex_m_common *cortex_m = target_to_cm(target);
2107 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2108 struct armv7m_common *armv7m = target_to_armv7m(target);
2110 /* hla_target shares the examine handler but does not support
2112 if (!armv7m->is_hla_target) {
2113 if (cortex_m->apsel == DP_APSEL_INVALID) {
2114 /* Search for the MEM-AP */
2115 retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
2116 if (retval != ERROR_OK) {
2117 LOG_ERROR("Could not find MEM-AP to control the core");
2121 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2124 /* Leave (only) generic DAP stuff for debugport_init(); */
2125 armv7m->debug_ap->memaccess_tck = 8;
2127 retval = mem_ap_init(armv7m->debug_ap);
2128 if (retval != ERROR_OK)
2132 if (!target_was_examined(target)) {
2133 target_set_examined(target);
2135 /* Read from Device Identification Registers */
2136 retval = target_read_u32(target, CPUID, &cpuid);
2137 if (retval != ERROR_OK)
2140 /* Get ARCH and CPU types */
2141 const enum cortex_m_partno core_partno = (cpuid & ARM_CPUID_PARTNO_MASK) >> ARM_CPUID_PARTNO_POS;
2143 for (unsigned int n = 0; n < ARRAY_SIZE(cortex_m_parts); n++) {
2144 if (core_partno == cortex_m_parts[n].partno) {
2145 cortex_m->core_info = &cortex_m_parts[n];
2150 if (!cortex_m->core_info) {
2151 LOG_ERROR("Cortex-M PARTNO 0x%x is unrecognized", core_partno);
2155 armv7m->arm.arch = cortex_m->core_info->arch;
2157 LOG_INFO("%s: %s r%" PRId8 "p%" PRId8 " processor detected",
2158 target_name(target),
2159 cortex_m->core_info->name,
2160 (uint8_t)((cpuid >> 20) & 0xf),
2161 (uint8_t)((cpuid >> 0) & 0xf));
2163 cortex_m->maskints_erratum = false;
2164 if (core_partno == CORTEX_M7_PARTNO) {
2166 rev = (cpuid >> 20) & 0xf;
2167 patch = (cpuid >> 0) & 0xf;
2168 if ((rev == 0) && (patch < 2)) {
2169 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2170 cortex_m->maskints_erratum = true;
2173 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2175 if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV4) {
2176 target_read_u32(target, MVFR0, &mvfr0);
2177 target_read_u32(target, MVFR1, &mvfr1);
2179 /* test for floating point feature on Cortex-M4 */
2180 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2181 LOG_DEBUG("%s floating point feature FPv4_SP found", cortex_m->core_info->name);
2182 armv7m->fp_feature = FPV4_SP;
2184 } else if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV5) {
2185 target_read_u32(target, MVFR0, &mvfr0);
2186 target_read_u32(target, MVFR1, &mvfr1);
2188 /* test for floating point features on Cortex-M7 */
2189 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2190 LOG_DEBUG("%s floating point feature FPv5_SP found", cortex_m->core_info->name);
2191 armv7m->fp_feature = FPV5_SP;
2192 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2193 LOG_DEBUG("%s floating point feature FPv5_DP found", cortex_m->core_info->name);
2194 armv7m->fp_feature = FPV5_DP;
2198 /* VECTRESET is supported only on ARMv7-M cores */
2199 cortex_m->vectreset_supported = armv7m->arm.arch == ARM_ARCH_V7M;
2201 /* Check for FPU, otherwise mark FPU register as non-existent */
2202 if (armv7m->fp_feature == FP_NONE)
2203 for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
2204 armv7m->arm.core_cache->reg_list[idx].exist = false;
2206 if (armv7m->arm.arch != ARM_ARCH_V8M)
2207 for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
2208 armv7m->arm.core_cache->reg_list[idx].exist = false;
2210 if (!armv7m->is_hla_target) {
2211 if (cortex_m->core_info->flags & CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K)
2212 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2213 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2214 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2217 retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
2218 if (retval != ERROR_OK)
2220 cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
2222 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
2223 /* Enable debug requests */
2224 uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
2226 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
2227 if (retval != ERROR_OK)
2229 cortex_m->dcb_dhcsr = dhcsr;
2232 /* Configure trace modules */
2233 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2234 if (retval != ERROR_OK)
2237 if (armv7m->trace_config.itm_deferred_config)
2238 armv7m_trace_itm_config(target);
2240 /* NOTE: FPB and DWT are both optional. */
2243 target_read_u32(target, FP_CTRL, &fpcr);
2244 /* bits [14:12] and [7:4] */
2245 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2246 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2247 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2248 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2249 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2250 free(cortex_m->fp_comparator_list);
2251 cortex_m->fp_comparator_list = calloc(
2252 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2253 sizeof(struct cortex_m_fp_comparator));
2254 cortex_m->fpb_enabled = fpcr & 1;
2255 for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2256 cortex_m->fp_comparator_list[i].type =
2257 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2258 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2260 /* make sure we clear any breakpoints enabled on the target */
2261 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2263 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2265 cortex_m->fp_num_code,
2266 cortex_m->fp_num_lit);
2269 cortex_m_dwt_free(target);
2270 cortex_m_dwt_setup(cortex_m, target);
2272 /* These hardware breakpoints only work for code in flash! */
2273 LOG_INFO("%s: target has %d breakpoints, %d watchpoints",
2274 target_name(target),
2275 cortex_m->fp_num_code,
2276 cortex_m->dwt_num_comp);
2282 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2284 struct armv7m_common *armv7m = target_to_armv7m(target);
2289 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2290 if (retval != ERROR_OK)
2293 dcrdr = target_buffer_get_u16(target, buf);
2294 *ctrl = (uint8_t)dcrdr;
2295 *value = (uint8_t)(dcrdr >> 8);
2297 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2299 /* write ack back to software dcc register
2300 * signify we have read data */
2301 if (dcrdr & (1 << 0)) {
2302 target_buffer_set_u16(target, buf, 0);
2303 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2304 if (retval != ERROR_OK)
2311 static int cortex_m_target_request_data(struct target *target,
2312 uint32_t size, uint8_t *buffer)
2318 for (i = 0; i < (size * 4); i++) {
2319 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2320 if (retval != ERROR_OK)
2328 static int cortex_m_handle_target_request(void *priv)
2330 struct target *target = priv;
2331 if (!target_was_examined(target))
2334 if (!target->dbg_msg_enabled)
2337 if (target->state == TARGET_RUNNING) {
2342 retval = cortex_m_dcc_read(target, &data, &ctrl);
2343 if (retval != ERROR_OK)
2346 /* check if we have data */
2347 if (ctrl & (1 << 0)) {
2350 /* we assume target is quick enough */
2352 for (int i = 1; i <= 3; i++) {
2353 retval = cortex_m_dcc_read(target, &data, &ctrl);
2354 if (retval != ERROR_OK)
2356 request |= ((uint32_t)data << (i * 8));
2358 target_request(target, request);
2365 static int cortex_m_init_arch_info(struct target *target,
2366 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2368 struct armv7m_common *armv7m = &cortex_m->armv7m;
2370 armv7m_init_arch_info(target, armv7m);
2372 /* default reset mode is to use srst if fitted
2373 * if not it will use CORTEX_M3_RESET_VECTRESET */
2374 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2376 armv7m->arm.dap = dap;
2378 /* register arch-specific functions */
2379 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2381 armv7m->post_debug_entry = NULL;
2383 armv7m->pre_restore_context = NULL;
2385 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2386 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2388 target_register_timer_callback(cortex_m_handle_target_request, 1,
2389 TARGET_TIMER_TYPE_PERIODIC, target);
2394 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2396 struct adiv5_private_config *pc;
2398 pc = (struct adiv5_private_config *)target->private_config;
2399 if (adiv5_verify_config(pc) != ERROR_OK)
2402 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2404 LOG_ERROR("No memory creating target");
2408 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2409 cortex_m->apsel = pc->ap_num;
2411 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2416 /*--------------------------------------------------------------------------*/
2418 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2419 struct cortex_m_common *cm)
2421 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2422 command_print(cmd, "target is not a Cortex-M");
2423 return ERROR_TARGET_INVALID;
2429 * Only stuff below this line should need to verify that its target
2430 * is a Cortex-M3. Everything else should have indirected through the
2431 * cortexm3_target structure, which is only used with CM3 targets.
2434 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2436 struct target *target = get_current_target(CMD_CTX);
2437 struct cortex_m_common *cortex_m = target_to_cm(target);
2438 struct armv7m_common *armv7m = &cortex_m->armv7m;
2442 static const struct {
2446 { "hard_err", VC_HARDERR, },
2447 { "int_err", VC_INTERR, },
2448 { "bus_err", VC_BUSERR, },
2449 { "state_err", VC_STATERR, },
2450 { "chk_err", VC_CHKERR, },
2451 { "nocp_err", VC_NOCPERR, },
2452 { "mm_err", VC_MMERR, },
2453 { "reset", VC_CORERESET, },
2456 retval = cortex_m_verify_pointer(CMD, cortex_m);
2457 if (retval != ERROR_OK)
2460 if (!target_was_examined(target)) {
2461 LOG_ERROR("Target not examined yet");
2465 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2466 if (retval != ERROR_OK)
2472 if (CMD_ARGC == 1) {
2473 if (strcmp(CMD_ARGV[0], "all") == 0) {
2474 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2475 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2476 | VC_MMERR | VC_CORERESET;
2478 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2481 while (CMD_ARGC-- > 0) {
2483 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2484 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2486 catch |= vec_ids[i].mask;
2489 if (i == ARRAY_SIZE(vec_ids)) {
2490 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2491 return ERROR_COMMAND_SYNTAX_ERROR;
2495 /* For now, armv7m->demcr only stores vector catch flags. */
2496 armv7m->demcr = catch;
2501 /* write, but don't assume it stuck (why not??) */
2502 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2503 if (retval != ERROR_OK)
2505 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2506 if (retval != ERROR_OK)
2509 /* FIXME be sure to clear DEMCR on clean server shutdown.
2510 * Otherwise the vector catch hardware could fire when there's
2511 * no debugger hooked up, causing much confusion...
2515 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2516 command_print(CMD, "%9s: %s", vec_ids[i].name,
2517 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2523 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2525 struct target *target = get_current_target(CMD_CTX);
2526 struct cortex_m_common *cortex_m = target_to_cm(target);
2529 static const struct jim_nvp nvp_maskisr_modes[] = {
2530 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2531 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2532 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2533 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2534 { .name = NULL, .value = -1 },
2536 const struct jim_nvp *n;
2539 retval = cortex_m_verify_pointer(CMD, cortex_m);
2540 if (retval != ERROR_OK)
2543 if (target->state != TARGET_HALTED) {
2544 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2549 n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2551 return ERROR_COMMAND_SYNTAX_ERROR;
2552 cortex_m->isrmasking_mode = n->value;
2553 cortex_m_set_maskints_for_halt(target);
2556 n = jim_nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2557 command_print(CMD, "cortex_m interrupt mask %s", n->name);
2562 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2564 struct target *target = get_current_target(CMD_CTX);
2565 struct cortex_m_common *cortex_m = target_to_cm(target);
2569 retval = cortex_m_verify_pointer(CMD, cortex_m);
2570 if (retval != ERROR_OK)
2574 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2575 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2577 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2578 if (target_was_examined(target)
2579 && !cortex_m->vectreset_supported)
2580 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2582 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2585 return ERROR_COMMAND_SYNTAX_ERROR;
2588 switch (cortex_m->soft_reset_config) {
2589 case CORTEX_M_RESET_SYSRESETREQ:
2590 reset_config = "sysresetreq";
2593 case CORTEX_M_RESET_VECTRESET:
2594 reset_config = "vectreset";
2598 reset_config = "unknown";
2602 command_print(CMD, "cortex_m reset_config %s", reset_config);
2607 static const struct command_registration cortex_m_exec_command_handlers[] = {
2610 .handler = handle_cortex_m_mask_interrupts_command,
2611 .mode = COMMAND_EXEC,
2612 .help = "mask cortex_m interrupts",
2613 .usage = "['auto'|'on'|'off'|'steponly']",
2616 .name = "vector_catch",
2617 .handler = handle_cortex_m_vector_catch_command,
2618 .mode = COMMAND_EXEC,
2619 .help = "configure hardware vectors to trigger debug entry",
2620 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2623 .name = "reset_config",
2624 .handler = handle_cortex_m_reset_config_command,
2625 .mode = COMMAND_ANY,
2626 .help = "configure software reset handling",
2627 .usage = "['sysresetreq'|'vectreset']",
2629 COMMAND_REGISTRATION_DONE
2631 static const struct command_registration cortex_m_command_handlers[] = {
2633 .chain = armv7m_command_handlers,
2636 .chain = armv7m_trace_command_handlers,
2638 /* START_DEPRECATED_TPIU */
2640 .chain = arm_tpiu_deprecated_command_handlers,
2642 /* END_DEPRECATED_TPIU */
2645 .mode = COMMAND_EXEC,
2646 .help = "Cortex-M command group",
2648 .chain = cortex_m_exec_command_handlers,
2651 .chain = rtt_target_command_handlers,
2653 COMMAND_REGISTRATION_DONE
2656 struct target_type cortexm_target = {
2659 .poll = cortex_m_poll,
2660 .arch_state = armv7m_arch_state,
2662 .target_request_data = cortex_m_target_request_data,
2664 .halt = cortex_m_halt,
2665 .resume = cortex_m_resume,
2666 .step = cortex_m_step,
2668 .assert_reset = cortex_m_assert_reset,
2669 .deassert_reset = cortex_m_deassert_reset,
2670 .soft_reset_halt = cortex_m_soft_reset_halt,
2672 .get_gdb_arch = arm_get_gdb_arch,
2673 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2675 .read_memory = cortex_m_read_memory,
2676 .write_memory = cortex_m_write_memory,
2677 .checksum_memory = armv7m_checksum_memory,
2678 .blank_check_memory = armv7m_blank_check_memory,
2680 .run_algorithm = armv7m_run_algorithm,
2681 .start_algorithm = armv7m_start_algorithm,
2682 .wait_algorithm = armv7m_wait_algorithm,
2684 .add_breakpoint = cortex_m_add_breakpoint,
2685 .remove_breakpoint = cortex_m_remove_breakpoint,
2686 .add_watchpoint = cortex_m_add_watchpoint,
2687 .remove_watchpoint = cortex_m_remove_watchpoint,
2688 .hit_watchpoint = cortex_m_hit_watchpoint,
2690 .commands = cortex_m_command_handlers,
2691 .target_create = cortex_m_target_create,
2692 .target_jim_configure = adiv5_jim_configure,
2693 .init_target = cortex_m_init_target,
2694 .examine = cortex_m_examine,
2695 .deinit_target = cortex_m_deinit_target,
2697 .profiling = cortex_m_profiling,