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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  *                                                                         *
  24  *                                                                         *
  25  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  26  *                                                                         *
  27  ***************************************************************************/
  28 #ifdef HAVE_CONFIG_H
  29 #include "config.h"
  30 #endif
  31
  32 #include "jtag/interface.h"
  33 #include "breakpoints.h"
  34 #include "cortex_m.h"
  35 #include "target_request.h"
  36 #include "target_type.h"
  37 #include "arm_disassembler.h"
  38 #include "register.h"
  39 #include "arm_opcodes.h"
  40 #include "arm_semihosting.h"
  41 #include <helper/time_support.h>
  42
  43 /* NOTE:  most of this should work fine for the Cortex-M1 and
  44  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  45  * Some differences:  M0/M1 doesn't have FPB remapping or the
  46  * DWT tracing/profiling support.  (So the cycle counter will
  47  * not be usable; the other stuff isn't currently used here.)
  48  *
  49  * Although there are some workarounds for errata seen only in r0p0
  50  * silicon, such old parts are hard to find and thus not much tested
  51  * any longer.
  52  */
  53
  54 /* forward declarations */
  55 static int cortex_m_store_core_reg_u32(struct target *target,
  56                 uint32_t num, uint32_t value);
  57 static void cortex_m_dwt_free(struct target *target);
  58
  59 static int cortexm_dap_read_coreregister_u32(struct target *target,
  60         uint32_t *value, int regnum)
  61 {
  62         struct armv7m_common *armv7m = target_to_armv7m(target);
  63         int retval;
  64         uint32_t dcrdr;
  65
  66         /* because the DCB_DCRDR is used for the emulated dcc channel
  67          * we have to save/restore the DCB_DCRDR when used */
  68         if (target->dbg_msg_enabled) {
  69                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
  70                 if (retval != ERROR_OK)
  71                         return retval;
  72         }
  73
  74         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
  75         if (retval != ERROR_OK)
  76                 return retval;
  77
  78         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
  79         if (retval != ERROR_OK)
  80                 return retval;
  81
  82         if (target->dbg_msg_enabled) {
  83                 /* restore DCB_DCRDR - this needs to be in a separate
  84                  * transaction otherwise the emulated DCC channel breaks */
  85                 if (retval == ERROR_OK)
  86                         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
  87         }
  88
  89         return retval;
  90 }
  91
  92 static int cortexm_dap_write_coreregister_u32(struct target *target,
  93         uint32_t value, int regnum)
  94 {
  95         struct armv7m_common *armv7m = target_to_armv7m(target);
  96         int retval;
  97         uint32_t dcrdr;
  98
  99         /* because the DCB_DCRDR is used for the emulated dcc channel
 100          * we have to save/restore the DCB_DCRDR when used */
 101         if (target->dbg_msg_enabled) {
 102                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
 103                 if (retval != ERROR_OK)
 104                         return retval;
 105         }
 106
 107         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
 108         if (retval != ERROR_OK)
 109                 return retval;
 110
 111         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
 112         if (retval != ERROR_OK)
 113                 return retval;
 114
 115         if (target->dbg_msg_enabled) {
 116                 /* restore DCB_DCRDR - this needs to be in a separate
 117                  * transaction otherwise the emulated DCC channel breaks */
 118                 if (retval == ERROR_OK)
 119                         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
 120         }
 121
 122         return retval;
 123 }
 124
 125 static int cortex_m_write_debug_halt_mask(struct target *target,
 126         uint32_t mask_on, uint32_t mask_off)
 127 {
 128         struct cortex_m_common *cortex_m = target_to_cm(target);
 129         struct armv7m_common *armv7m = &cortex_m->armv7m;
 130
 131         /* mask off status bits */
 132         cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
 133         /* create new register mask */
 134         cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 135
 136         return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
 137 }
 138
 139 static int cortex_m_set_maskints(struct target *target, bool mask)
 140 {
 141         struct cortex_m_common *cortex_m = target_to_cm(target);
 142         if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
 143                 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
 144         else
 145                 return ERROR_OK;
 146 }
 147
 148 static int cortex_m_set_maskints_for_halt(struct target *target)
 149 {
 150         struct cortex_m_common *cortex_m = target_to_cm(target);
 151         switch (cortex_m->isrmasking_mode) {
 152                 case CORTEX_M_ISRMASK_AUTO:
 153                         /* interrupts taken at resume, whether for step or run -> no mask */
 154                         return cortex_m_set_maskints(target, false);
 155
 156                 case CORTEX_M_ISRMASK_OFF:
 157                         /* interrupts never masked */
 158                         return cortex_m_set_maskints(target, false);
 159
 160                 case CORTEX_M_ISRMASK_ON:
 161                         /* interrupts always masked */
 162                         return cortex_m_set_maskints(target, true);
 163
 164                 case CORTEX_M_ISRMASK_STEPONLY:
 165                         /* interrupts masked for single step only -> mask now if MASKINTS
 166                          * erratum, otherwise only mask before stepping */
 167                         return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
 168         }
 169         return ERROR_OK;
 170 }
 171
 172 static int cortex_m_set_maskints_for_run(struct target *target)
 173 {
 174         switch (target_to_cm(target)->isrmasking_mode) {
 175                 case CORTEX_M_ISRMASK_AUTO:
 176                         /* interrupts taken at resume, whether for step or run -> no mask */
 177                         return cortex_m_set_maskints(target, false);
 178
 179                 case CORTEX_M_ISRMASK_OFF:
 180                         /* interrupts never masked */
 181                         return cortex_m_set_maskints(target, false);
 182
 183                 case CORTEX_M_ISRMASK_ON:
 184                         /* interrupts always masked */
 185                         return cortex_m_set_maskints(target, true);
 186
 187                 case CORTEX_M_ISRMASK_STEPONLY:
 188                         /* interrupts masked for single step only -> no mask */
 189                         return cortex_m_set_maskints(target, false);
 190         }
 191         return ERROR_OK;
 192 }
 193
 194 static int cortex_m_set_maskints_for_step(struct target *target)
 195 {
 196         switch (target_to_cm(target)->isrmasking_mode) {
 197                 case CORTEX_M_ISRMASK_AUTO:
 198                         /* the auto-interrupt should already be done -> mask */
 199                         return cortex_m_set_maskints(target, true);
 200
 201                 case CORTEX_M_ISRMASK_OFF:
 202                         /* interrupts never masked */
 203                         return cortex_m_set_maskints(target, false);
 204
 205                 case CORTEX_M_ISRMASK_ON:
 206                         /* interrupts always masked */
 207                         return cortex_m_set_maskints(target, true);
 208
 209                 case CORTEX_M_ISRMASK_STEPONLY:
 210                         /* interrupts masked for single step only -> mask */
 211                         return cortex_m_set_maskints(target, true);
 212         }
 213         return ERROR_OK;
 214 }
 215
 216 static int cortex_m_clear_halt(struct target *target)
 217 {
 218         struct cortex_m_common *cortex_m = target_to_cm(target);
 219         struct armv7m_common *armv7m = &cortex_m->armv7m;
 220         int retval;
 221
 222         /* clear step if any */
 223         cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
 224
 225         /* Read Debug Fault Status Register */
 226         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
 227         if (retval != ERROR_OK)
 228                 return retval;
 229
 230         /* Clear Debug Fault Status */
 231         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
 232         if (retval != ERROR_OK)
 233                 return retval;
 234         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
 235
 236         return ERROR_OK;
 237 }
 238
 239 static int cortex_m_single_step_core(struct target *target)
 240 {
 241         struct cortex_m_common *cortex_m = target_to_cm(target);
 242         struct armv7m_common *armv7m = &cortex_m->armv7m;
 243         int retval;
 244
 245         /* Mask interrupts before clearing halt, if not done already.  This avoids
 246          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 247          * HALT can put the core into an unknown state.
 248          */
 249         if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
 250                 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
 251                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 252                 if (retval != ERROR_OK)
 253                         return retval;
 254         }
 255         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
 256                         DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 257         if (retval != ERROR_OK)
 258                 return retval;
 259         LOG_DEBUG(" ");
 260
 261         /* restore dhcsr reg */
 262         cortex_m_clear_halt(target);
 263
 264         return ERROR_OK;
 265 }
 266
 267 static int cortex_m_enable_fpb(struct target *target)
 268 {
 269         int retval = target_write_u32(target, FP_CTRL, 3);
 270         if (retval != ERROR_OK)
 271                 return retval;
 272
 273         /* check the fpb is actually enabled */
 274         uint32_t fpctrl;
 275         retval = target_read_u32(target, FP_CTRL, &fpctrl);
 276         if (retval != ERROR_OK)
 277                 return retval;
 278
 279         if (fpctrl & 1)
 280                 return ERROR_OK;
 281
 282         return ERROR_FAIL;
 283 }
 284
 285 static int cortex_m_endreset_event(struct target *target)
 286 {
 287         int i;
 288         int retval;
 289         uint32_t dcb_demcr;
 290         struct cortex_m_common *cortex_m = target_to_cm(target);
 291         struct armv7m_common *armv7m = &cortex_m->armv7m;
 292         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 293         struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
 294         struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
 295
 296         /* REVISIT The four debug monitor bits are currently ignored... */
 297         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
 298         if (retval != ERROR_OK)
 299                 return retval;
 300         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
 301
 302         /* this register is used for emulated dcc channel */
 303         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
 304         if (retval != ERROR_OK)
 305                 return retval;
 306
 307         /* Enable debug requests */
 308         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 309         if (retval != ERROR_OK)
 310                 return retval;
 311         if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
 312                 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
 313                 if (retval != ERROR_OK)
 314                         return retval;
 315         }
 316
 317         /* Restore proper interrupt masking setting for running CPU. */
 318         cortex_m_set_maskints_for_run(target);
 319
 320         /* Enable features controlled by ITM and DWT blocks, and catch only
 321          * the vectors we were told to pay attention to.
 322          *
 323          * Target firmware is responsible for all fault handling policy
 324          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 325          * or manual updates to the NVIC SHCSR and CCR registers.
 326          */
 327         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
 328         if (retval != ERROR_OK)
 329                 return retval;
 330
 331         /* Paranoia: evidently some (early?) chips don't preserve all the
 332          * debug state (including FPB, DWT, etc) across reset...
 333          */
 334
 335         /* Enable FPB */
 336         retval = cortex_m_enable_fpb(target);
 337         if (retval != ERROR_OK) {
 338                 LOG_ERROR("Failed to enable the FPB");
 339                 return retval;
 340         }
 341
 342         cortex_m->fpb_enabled = true;
 343
 344         /* Restore FPB registers */
 345         for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
 346                 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 347                 if (retval != ERROR_OK)
 348                         return retval;
 349         }
 350
 351         /* Restore DWT registers */
 352         for (i = 0; i < cortex_m->dwt_num_comp; i++) {
 353                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 354                                 dwt_list[i].comp);
 355                 if (retval != ERROR_OK)
 356                         return retval;
 357                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 358                                 dwt_list[i].mask);
 359                 if (retval != ERROR_OK)
 360                         return retval;
 361                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 362                                 dwt_list[i].function);
 363                 if (retval != ERROR_OK)
 364                         return retval;
 365         }
 366         retval = dap_run(swjdp);
 367         if (retval != ERROR_OK)
 368                 return retval;
 369
 370         register_cache_invalidate(armv7m->arm.core_cache);
 371
 372         /* make sure we have latest dhcsr flags */
 373         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 374
 375         return retval;
 376 }
 377
 378 static int cortex_m_examine_debug_reason(struct target *target)
 379 {
 380         struct cortex_m_common *cortex_m = target_to_cm(target);
 381
 382         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
 383          * only check the debug reason if we don't know it already */
 384
 385         if ((target->debug_reason != DBG_REASON_DBGRQ)
 386                 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
 387                 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
 388                         target->debug_reason = DBG_REASON_BREAKPOINT;
 389                         if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 390                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 391                 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
 392                         target->debug_reason = DBG_REASON_WATCHPOINT;
 393                 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
 394                         target->debug_reason = DBG_REASON_BREAKPOINT;
 395                 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
 396                         target->debug_reason = DBG_REASON_DBGRQ;
 397                 else    /* HALTED */
 398                         target->debug_reason = DBG_REASON_UNDEFINED;
 399         }
 400
 401         return ERROR_OK;
 402 }
 403
 404 static int cortex_m_examine_exception_reason(struct target *target)
 405 {
 406         uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
 407         struct armv7m_common *armv7m = target_to_armv7m(target);
 408         struct adiv5_dap *swjdp = armv7m->arm.dap;
 409         int retval;
 410
 411         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
 412         if (retval != ERROR_OK)
 413                 return retval;
 414         switch (armv7m->exception_number) {
 415                 case 2: /* NMI */
 416                         break;
 417                 case 3: /* Hard Fault */
 418                         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
 419                         if (retval != ERROR_OK)
 420                                 return retval;
 421                         if (except_sr & 0x40000000) {
 422                                 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
 423                                 if (retval != ERROR_OK)
 424                                         return retval;
 425                         }
 426                         break;
 427                 case 4: /* Memory Management */
 428                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 429                         if (retval != ERROR_OK)
 430                                 return retval;
 431                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
 432                         if (retval != ERROR_OK)
 433                                 return retval;
 434                         break;
 435                 case 5: /* Bus Fault */
 436                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 437                         if (retval != ERROR_OK)
 438                                 return retval;
 439                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
 440                         if (retval != ERROR_OK)
 441                                 return retval;
 442                         break;
 443                 case 6: /* Usage Fault */
 444                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
 445                         if (retval != ERROR_OK)
 446                                 return retval;
 447                         break;
 448                 case 7: /* Secure Fault */
 449                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
 450                         if (retval != ERROR_OK)
 451                                 return retval;
 452                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
 453                         if (retval != ERROR_OK)
 454                                 return retval;
 455                         break;
 456                 case 11:        /* SVCall */
 457                         break;
 458                 case 12:        /* Debug Monitor */
 459                         retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
 460                         if (retval != ERROR_OK)
 461                                 return retval;
 462                         break;
 463                 case 14:        /* PendSV */
 464                         break;
 465                 case 15:        /* SysTick */
 466                         break;
 467                 default:
 468                         except_sr = 0;
 469                         break;
 470         }
 471         retval = dap_run(swjdp);
 472         if (retval == ERROR_OK)
 473                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 474                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 475                         armv7m_exception_string(armv7m->exception_number),
 476                         shcsr, except_sr, cfsr, except_ar);
 477         return retval;
 478 }
 479
 480 static int cortex_m_debug_entry(struct target *target)
 481 {
 482         int i;
 483         uint32_t xPSR;
 484         int retval;
 485         struct cortex_m_common *cortex_m = target_to_cm(target);
 486         struct armv7m_common *armv7m = &cortex_m->armv7m;
 487         struct arm *arm = &armv7m->arm;
 488         struct reg *r;
 489
 490         LOG_DEBUG(" ");
 491
 492         /* Do this really early to minimize the window where the MASKINTS erratum
 493          * can pile up pending interrupts. */
 494         cortex_m_set_maskints_for_halt(target);
 495
 496         cortex_m_clear_halt(target);
 497         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 498         if (retval != ERROR_OK)
 499                 return retval;
 500
 501         retval = armv7m->examine_debug_reason(target);
 502         if (retval != ERROR_OK)
 503                 return retval;
 504
 505         /* examine PE security state */
 506         bool secure_state = false;
 507         if (armv7m->arm.is_armv8m) {
 508                 uint32_t dscsr;
 509
 510                 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
 511                 if (retval != ERROR_OK)
 512                         return retval;
 513
 514                 secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
 515         }
 516
 517         /* Examine target state and mode
 518          * First load register accessible through core debug port */
 519         int num_regs = arm->core_cache->num_regs;
 520
 521         for (i = 0; i < num_regs; i++) {
 522                 r = &armv7m->arm.core_cache->reg_list[i];
 523                 if (!r->valid)
 524                         arm->read_core_reg(target, r, i, ARM_MODE_ANY);
 525         }
 526
 527         r = arm->cpsr;
 528         xPSR = buf_get_u32(r->value, 0, 32);
 529
 530         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 531         if (xPSR & 0xf00) {
 532                 r->dirty = r->valid;
 533                 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
 534         }
 535
 536         /* Are we in an exception handler */
 537         if (xPSR & 0x1FF) {
 538                 armv7m->exception_number = (xPSR & 0x1FF);
 539
 540                 arm->core_mode = ARM_MODE_HANDLER;
 541                 arm->map = armv7m_msp_reg_map;
 542         } else {
 543                 unsigned control = buf_get_u32(arm->core_cache
 544                                 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
 545
 546                 /* is this thread privileged? */
 547                 arm->core_mode = control & 1
 548                         ? ARM_MODE_USER_THREAD
 549                         : ARM_MODE_THREAD;
 550
 551                 /* which stack is it using? */
 552                 if (control & 2)
 553                         arm->map = armv7m_psp_reg_map;
 554                 else
 555                         arm->map = armv7m_msp_reg_map;
 556
 557                 armv7m->exception_number = 0;
 558         }
 559
 560         if (armv7m->exception_number)
 561                 cortex_m_examine_exception_reason(target);
 562
 563         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
 564                 arm_mode_name(arm->core_mode),
 565                 buf_get_u32(arm->pc->value, 0, 32),
 566                 secure_state ? "Secure" : "Non-Secure",
 567                 target_state_name(target));
 568
 569         if (armv7m->post_debug_entry) {
 570                 retval = armv7m->post_debug_entry(target);
 571                 if (retval != ERROR_OK)
 572                         return retval;
 573         }
 574
 575         return ERROR_OK;
 576 }
 577
 578 static int cortex_m_poll(struct target *target)
 579 {
 580         int detected_failure = ERROR_OK;
 581         int retval = ERROR_OK;
 582         enum target_state prev_target_state = target->state;
 583         struct cortex_m_common *cortex_m = target_to_cm(target);
 584         struct armv7m_common *armv7m = &cortex_m->armv7m;
 585
 586         /* Read from Debug Halting Control and Status Register */
 587         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 588         if (retval != ERROR_OK) {
 589                 target->state = TARGET_UNKNOWN;
 590                 return retval;
 591         }
 592
 593         /* Recover from lockup.  See ARMv7-M architecture spec,
 594          * section B1.5.15 "Unrecoverable exception cases".
 595          */
 596         if (cortex_m->dcb_dhcsr & S_LOCKUP) {
 597                 LOG_ERROR("%s -- clearing lockup after double fault",
 598                         target_name(target));
 599                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 600                 target->debug_reason = DBG_REASON_DBGRQ;
 601
 602                 /* We have to execute the rest (the "finally" equivalent, but
 603                  * still throw this exception again).
 604                  */
 605                 detected_failure = ERROR_FAIL;
 606
 607                 /* refresh status bits */
 608                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 609                 if (retval != ERROR_OK)
 610                         return retval;
 611         }
 612
 613         if (cortex_m->dcb_dhcsr & S_RESET_ST) {
 614                 if (target->state != TARGET_RESET) {
 615                         target->state = TARGET_RESET;
 616                         LOG_INFO("%s: external reset detected", target_name(target));
 617                 }
 618                 return ERROR_OK;
 619         }
 620
 621         if (target->state == TARGET_RESET) {
 622                 /* Cannot switch context while running so endreset is
 623                  * called with target->state == TARGET_RESET
 624                  */
 625                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 626                         cortex_m->dcb_dhcsr);
 627                 retval = cortex_m_endreset_event(target);
 628                 if (retval != ERROR_OK) {
 629                         target->state = TARGET_UNKNOWN;
 630                         return retval;
 631                 }
 632                 target->state = TARGET_RUNNING;
 633                 prev_target_state = TARGET_RUNNING;
 634         }
 635
 636         if (cortex_m->dcb_dhcsr & S_HALT) {
 637                 target->state = TARGET_HALTED;
 638
 639                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
 640                         retval = cortex_m_debug_entry(target);
 641                         if (retval != ERROR_OK)
 642                                 return retval;
 643
 644                         if (arm_semihosting(target, &retval) != 0)
 645                                 return retval;
 646
 647                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 648                 }
 649                 if (prev_target_state == TARGET_DEBUG_RUNNING) {
 650                         LOG_DEBUG(" ");
 651                         retval = cortex_m_debug_entry(target);
 652                         if (retval != ERROR_OK)
 653                                 return retval;
 654
 655                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 656                 }
 657         }
 658
 659         if (target->state == TARGET_UNKNOWN) {
 660                 /* check if processor is retiring instructions or sleeping */
 661                 if (cortex_m->dcb_dhcsr & S_RETIRE_ST || cortex_m->dcb_dhcsr & S_SLEEP) {
 662                         target->state = TARGET_RUNNING;
 663                         retval = ERROR_OK;
 664                 }
 665         }
 666
 667         /* Check that target is truly halted, since the target could be resumed externally */
 668         if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
 669                 /* registers are now invalid */
 670                 register_cache_invalidate(armv7m->arm.core_cache);
 671
 672                 target->state = TARGET_RUNNING;
 673                 LOG_WARNING("%s: external resume detected", target_name(target));
 674                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 675                 retval = ERROR_OK;
 676         }
 677
 678         /* Did we detect a failure condition that we cleared? */
 679         if (detected_failure != ERROR_OK)
 680                 retval = detected_failure;
 681         return retval;
 682 }
 683
 684 static int cortex_m_halt(struct target *target)
 685 {
 686         LOG_DEBUG("target->state: %s",
 687                 target_state_name(target));
 688
 689         if (target->state == TARGET_HALTED) {
 690                 LOG_DEBUG("target was already halted");
 691                 return ERROR_OK;
 692         }
 693
 694         if (target->state == TARGET_UNKNOWN)
 695                 LOG_WARNING("target was in unknown state when halt was requested");
 696
 697         if (target->state == TARGET_RESET) {
 698                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 699                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 700                         return ERROR_TARGET_FAILURE;
 701                 } else {
 702                         /* we came here in a reset_halt or reset_init sequence
 703                          * debug entry was already prepared in cortex_m3_assert_reset()
 704                          */
 705                         target->debug_reason = DBG_REASON_DBGRQ;
 706
 707                         return ERROR_OK;
 708                 }
 709         }
 710
 711         /* Write to Debug Halting Control and Status Register */
 712         cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 713
 714         /* Do this really early to minimize the window where the MASKINTS erratum
 715          * can pile up pending interrupts. */
 716         cortex_m_set_maskints_for_halt(target);
 717
 718         target->debug_reason = DBG_REASON_DBGRQ;
 719
 720         return ERROR_OK;
 721 }
 722
 723 static int cortex_m_soft_reset_halt(struct target *target)
 724 {
 725         struct cortex_m_common *cortex_m = target_to_cm(target);
 726         struct armv7m_common *armv7m = &cortex_m->armv7m;
 727         uint32_t dcb_dhcsr = 0;
 728         int retval, timeout = 0;
 729
 730         /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
 731          * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
 732          * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
 733          * core, not the peripherals */
 734         LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
 735
 736         /* Set C_DEBUGEN */
 737         retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
 738         if (retval != ERROR_OK)
 739                 return retval;
 740
 741         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 742         retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
 743                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 744         if (retval != ERROR_OK)
 745                 return retval;
 746
 747         /* Request a core-only reset */
 748         retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
 749                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 750         if (retval != ERROR_OK)
 751                 return retval;
 752         target->state = TARGET_RESET;
 753
 754         /* registers are now invalid */
 755         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 756
 757         while (timeout < 100) {
 758                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
 759                 if (retval == ERROR_OK) {
 760                         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
 761                                         &cortex_m->nvic_dfsr);
 762                         if (retval != ERROR_OK)
 763                                 return retval;
 764                         if ((dcb_dhcsr & S_HALT)
 765                                 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
 766                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 767                                         "DFSR 0x%08x",
 768                                         (unsigned) dcb_dhcsr,
 769                                         (unsigned) cortex_m->nvic_dfsr);
 770                                 cortex_m_poll(target);
 771                                 /* FIXME restore user's vector catch config */
 772                                 return ERROR_OK;
 773                         } else
 774                                 LOG_DEBUG("waiting for system reset-halt, "
 775                                         "DHCSR 0x%08x, %d ms",
 776                                         (unsigned) dcb_dhcsr, timeout);
 777                 }
 778                 timeout++;
 779                 alive_sleep(1);
 780         }
 781
 782         return ERROR_OK;
 783 }
 784
 785 void cortex_m_enable_breakpoints(struct target *target)
 786 {
 787         struct breakpoint *breakpoint = target->breakpoints;
 788
 789         /* set any pending breakpoints */
 790         while (breakpoint) {
 791                 if (!breakpoint->set)
 792                         cortex_m_set_breakpoint(target, breakpoint);
 793                 breakpoint = breakpoint->next;
 794         }
 795 }
 796
 797 static int cortex_m_resume(struct target *target, int current,
 798         target_addr_t address, int handle_breakpoints, int debug_execution)
 799 {
 800         struct armv7m_common *armv7m = target_to_armv7m(target);
 801         struct breakpoint *breakpoint = NULL;
 802         uint32_t resume_pc;
 803         struct reg *r;
 804
 805         if (target->state != TARGET_HALTED) {
 806                 LOG_WARNING("target not halted");
 807                 return ERROR_TARGET_NOT_HALTED;
 808         }
 809
 810         if (!debug_execution) {
 811                 target_free_all_working_areas(target);
 812                 cortex_m_enable_breakpoints(target);
 813                 cortex_m_enable_watchpoints(target);
 814         }
 815
 816         if (debug_execution) {
 817                 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
 818
 819                 /* Disable interrupts */
 820                 /* We disable interrupts in the PRIMASK register instead of
 821                  * masking with C_MASKINTS.  This is probably the same issue
 822                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 823                  * in parallel with disabled interrupts can cause local faults
 824                  * to not be taken.
 825                  *
 826                  * REVISIT this clearly breaks non-debug execution, since the
 827                  * PRIMASK register state isn't saved/restored...  workaround
 828                  * by never resuming app code after debug execution.
 829                  */
 830                 buf_set_u32(r->value, 0, 1, 1);
 831                 r->dirty = true;
 832                 r->valid = true;
 833
 834                 /* Make sure we are in Thumb mode */
 835                 r = armv7m->arm.cpsr;
 836                 buf_set_u32(r->value, 24, 1, 1);
 837                 r->dirty = true;
 838                 r->valid = true;
 839         }
 840
 841         /* current = 1: continue on current pc, otherwise continue at <address> */
 842         r = armv7m->arm.pc;
 843         if (!current) {
 844                 buf_set_u32(r->value, 0, 32, address);
 845                 r->dirty = true;
 846                 r->valid = true;
 847         }
 848
 849         /* if we halted last time due to a bkpt instruction
 850          * then we have to manually step over it, otherwise
 851          * the core will break again */
 852
 853         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 854                 && !debug_execution)
 855                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 856
 857         resume_pc = buf_get_u32(r->value, 0, 32);
 858
 859         armv7m_restore_context(target);
 860
 861         /* the front-end may request us not to handle breakpoints */
 862         if (handle_breakpoints) {
 863                 /* Single step past breakpoint at current address */
 864                 breakpoint = breakpoint_find(target, resume_pc);
 865                 if (breakpoint) {
 866                         LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
 867                                 breakpoint->address,
 868                                 breakpoint->unique_id);
 869                         cortex_m_unset_breakpoint(target, breakpoint);
 870                         cortex_m_single_step_core(target);
 871                         cortex_m_set_breakpoint(target, breakpoint);
 872                 }
 873         }
 874
 875         /* Restart core */
 876         cortex_m_set_maskints_for_run(target);
 877         cortex_m_write_debug_halt_mask(target, 0, C_HALT);
 878
 879         target->debug_reason = DBG_REASON_NOTHALTED;
 880
 881         /* registers are now invalid */
 882         register_cache_invalidate(armv7m->arm.core_cache);
 883
 884         if (!debug_execution) {
 885                 target->state = TARGET_RUNNING;
 886                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 887                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 888         } else {
 889                 target->state = TARGET_DEBUG_RUNNING;
 890                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 891                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 892         }
 893
 894         return ERROR_OK;
 895 }
 896
 897 /* int irqstepcount = 0; */
 898 static int cortex_m_step(struct target *target, int current,
 899         target_addr_t address, int handle_breakpoints)
 900 {
 901         struct cortex_m_common *cortex_m = target_to_cm(target);
 902         struct armv7m_common *armv7m = &cortex_m->armv7m;
 903         struct breakpoint *breakpoint = NULL;
 904         struct reg *pc = armv7m->arm.pc;
 905         bool bkpt_inst_found = false;
 906         int retval;
 907         bool isr_timed_out = false;
 908
 909         if (target->state != TARGET_HALTED) {
 910                 LOG_WARNING("target not halted");
 911                 return ERROR_TARGET_NOT_HALTED;
 912         }
 913
 914         /* current = 1: continue on current pc, otherwise continue at <address> */
 915         if (!current)
 916                 buf_set_u32(pc->value, 0, 32, address);
 917
 918         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
 919
 920         /* the front-end may request us not to handle breakpoints */
 921         if (handle_breakpoints) {
 922                 breakpoint = breakpoint_find(target, pc_value);
 923                 if (breakpoint)
 924                         cortex_m_unset_breakpoint(target, breakpoint);
 925         }
 926
 927         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 928
 929         target->debug_reason = DBG_REASON_SINGLESTEP;
 930
 931         armv7m_restore_context(target);
 932
 933         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 934
 935         /* if no bkpt instruction is found at pc then we can perform
 936          * a normal step, otherwise we have to manually step over the bkpt
 937          * instruction - as such simulate a step */
 938         if (bkpt_inst_found == false) {
 939                 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
 940                         /* Automatic ISR masking mode off: Just step over the next
 941                          * instruction, with interrupts on or off as appropriate. */
 942                         cortex_m_set_maskints_for_step(target);
 943                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 944                 } else {
 945                         /* Process interrupts during stepping in a way they don't interfere
 946                          * debugging.
 947                          *
 948                          * Principle:
 949                          *
 950                          * Set a temporary break point at the current pc and let the core run
 951                          * with interrupts enabled. Pending interrupts get served and we run
 952                          * into the breakpoint again afterwards. Then we step over the next
 953                          * instruction with interrupts disabled.
 954                          *
 955                          * If the pending interrupts don't complete within time, we leave the
 956                          * core running. This may happen if the interrupts trigger faster
 957                          * than the core can process them or the handler doesn't return.
 958                          *
 959                          * If no more breakpoints are available we simply do a step with
 960                          * interrupts enabled.
 961                          *
 962                          */
 963
 964                         /* 2012-09-29 ph
 965                          *
 966                          * If a break point is already set on the lower half word then a break point on
 967                          * the upper half word will not break again when the core is restarted. So we
 968                          * just step over the instruction with interrupts disabled.
 969                          *
 970                          * The documentation has no information about this, it was found by observation
 971                          * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
 972                          * suffer from this problem.
 973                          *
 974                          * To add some confusion: pc_value has bit 0 always set, while the breakpoint
 975                          * address has it always cleared. The former is done to indicate thumb mode
 976                          * to gdb.
 977                          *
 978                          */
 979                         if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
 980                                 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
 981                                 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
 982                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
 983                                 /* Re-enable interrupts if appropriate */
 984                                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 985                                 cortex_m_set_maskints_for_halt(target);
 986                         } else {
 987
 988                                 /* Set a temporary break point */
 989                                 if (breakpoint) {
 990                                         retval = cortex_m_set_breakpoint(target, breakpoint);
 991                                 } else {
 992                                         enum breakpoint_type type = BKPT_HARD;
 993                                         if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
 994                                                 /* FPB rev.1 cannot handle such addr, try BKPT instr */
 995                                                 type = BKPT_SOFT;
 996                                         }
 997                                         retval = breakpoint_add(target, pc_value, 2, type);
 998                                 }
 999
1000                                 bool tmp_bp_set = (retval == ERROR_OK);
1001
1002                                 /* No more breakpoints left, just do a step */
1003                                 if (!tmp_bp_set) {
1004                                         cortex_m_set_maskints_for_step(target);
1005                                         cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1006                                         /* Re-enable interrupts if appropriate */
1007                                         cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1008                                         cortex_m_set_maskints_for_halt(target);
1009                                 } else {
1010                                         /* Start the core */
1011                                         LOG_DEBUG("Starting core to serve pending interrupts");
1012                                         int64_t t_start = timeval_ms();
1013                                         cortex_m_set_maskints_for_run(target);
1014                                         cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
1015
1016                                         /* Wait for pending handlers to complete or timeout */
1017                                         do {
1018                                                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
1019                                                                 DCB_DHCSR,
1020                                                                 &cortex_m->dcb_dhcsr);
1021                                                 if (retval != ERROR_OK) {
1022                                                         target->state = TARGET_UNKNOWN;
1023                                                         return retval;
1024                                                 }
1025                                                 isr_timed_out = ((timeval_ms() - t_start) > 500);
1026                                         } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1027
1028                                         /* only remove breakpoint if we created it */
1029                                         if (breakpoint)
1030                                                 cortex_m_unset_breakpoint(target, breakpoint);
1031                                         else {
1032                                                 /* Remove the temporary breakpoint */
1033                                                 breakpoint_remove(target, pc_value);
1034                                         }
1035
1036                                         if (isr_timed_out) {
1037                                                 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1038                                                         "leaving target running");
1039                                         } else {
1040                                                 /* Step over next instruction with interrupts disabled */
1041                                                 cortex_m_set_maskints_for_step(target);
1042                                                 cortex_m_write_debug_halt_mask(target,
1043                                                         C_HALT | C_MASKINTS,
1044                                                         0);
1045                                                 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1046                                                 /* Re-enable interrupts if appropriate */
1047                                                 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1048                                                 cortex_m_set_maskints_for_halt(target);
1049                                         }
1050                                 }
1051                         }
1052                 }
1053         }
1054
1055         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1056         if (retval != ERROR_OK)
1057                 return retval;
1058
1059         /* registers are now invalid */
1060         register_cache_invalidate(armv7m->arm.core_cache);
1061
1062         if (breakpoint)
1063                 cortex_m_set_breakpoint(target, breakpoint);
1064
1065         if (isr_timed_out) {
1066                 /* Leave the core running. The user has to stop execution manually. */
1067                 target->debug_reason = DBG_REASON_NOTHALTED;
1068                 target->state = TARGET_RUNNING;
1069                 return ERROR_OK;
1070         }
1071
1072         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1073                 " nvic_icsr = 0x%" PRIx32,
1074                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1075
1076         retval = cortex_m_debug_entry(target);
1077         if (retval != ERROR_OK)
1078                 return retval;
1079         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1080
1081         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1082                 " nvic_icsr = 0x%" PRIx32,
1083                 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1084
1085         return ERROR_OK;
1086 }
1087
1088 static int cortex_m_assert_reset(struct target *target)
1089 {
1090         struct cortex_m_common *cortex_m = target_to_cm(target);
1091         struct armv7m_common *armv7m = &cortex_m->armv7m;
1092         enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1093
1094         LOG_DEBUG("target->state: %s",
1095                 target_state_name(target));
1096
1097         enum reset_types jtag_reset_config = jtag_get_reset_config();
1098
1099         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1100                 /* allow scripts to override the reset event */
1101
1102                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1103                 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1104                 target->state = TARGET_RESET;
1105
1106                 return ERROR_OK;
1107         }
1108
1109         /* some cores support connecting while srst is asserted
1110          * use that mode is it has been configured */
1111
1112         bool srst_asserted = false;
1113
1114         if (!target_was_examined(target)) {
1115                 if (jtag_reset_config & RESET_HAS_SRST) {
1116                         adapter_assert_reset();
1117                         if (target->reset_halt)
1118                                 LOG_ERROR("Target not examined, will not halt after reset!");
1119                         return ERROR_OK;
1120                 } else {
1121                         LOG_ERROR("Target not examined, reset NOT asserted!");
1122                         return ERROR_FAIL;
1123                 }
1124         }
1125
1126         if ((jtag_reset_config & RESET_HAS_SRST) &&
1127             (jtag_reset_config & RESET_SRST_NO_GATING)) {
1128                 adapter_assert_reset();
1129                 srst_asserted = true;
1130         }
1131
1132         /* Enable debug requests */
1133         int retval;
1134         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1135         /* Store important errors instead of failing and proceed to reset assert */
1136
1137         if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1138                 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1139
1140         /* If the processor is sleeping in a WFI or WFE instruction, the
1141          * C_HALT bit must be asserted to regain control */
1142         if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1143                 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1144
1145         mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1146         /* Ignore less important errors */
1147
1148         if (!target->reset_halt) {
1149                 /* Set/Clear C_MASKINTS in a separate operation */
1150                 cortex_m_set_maskints_for_run(target);
1151
1152                 /* clear any debug flags before resuming */
1153                 cortex_m_clear_halt(target);
1154
1155                 /* clear C_HALT in dhcsr reg */
1156                 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1157         } else {
1158                 /* Halt in debug on reset; endreset_event() restores DEMCR.
1159                  *
1160                  * REVISIT catching BUSERR presumably helps to defend against
1161                  * bad vector table entries.  Should this include MMERR or
1162                  * other flags too?
1163                  */
1164                 int retval2;
1165                 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1166                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1167                 if (retval != ERROR_OK || retval2 != ERROR_OK)
1168                         LOG_INFO("AP write error, reset will not halt");
1169         }
1170
1171         if (jtag_reset_config & RESET_HAS_SRST) {
1172                 /* default to asserting srst */
1173                 if (!srst_asserted)
1174                         adapter_assert_reset();
1175
1176                 /* srst is asserted, ignore AP access errors */
1177                 retval = ERROR_OK;
1178         } else {
1179                 /* Use a standard Cortex-M3 software reset mechanism.
1180                  * We default to using VECRESET as it is supported on all current cores
1181                  * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1182                  * This has the disadvantage of not resetting the peripherals, so a
1183                  * reset-init event handler is needed to perform any peripheral resets.
1184                  */
1185                 if (!cortex_m->vectreset_supported
1186                                 && reset_config == CORTEX_M_RESET_VECTRESET) {
1187                         reset_config = CORTEX_M_RESET_SYSRESETREQ;
1188                         LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1189                         LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1190                 }
1191
1192                 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1193                         ? "SYSRESETREQ" : "VECTRESET");
1194
1195                 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1196                         LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1197                                 "handler to reset any peripherals or configure hardware srst support.");
1198                 }
1199
1200                 int retval3;
1201                 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1202                                 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1203                                 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1204                 if (retval3 != ERROR_OK)
1205                         LOG_DEBUG("Ignoring AP write error right after reset");
1206
1207                 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1208                 if (retval3 != ERROR_OK)
1209                         LOG_ERROR("DP initialisation failed");
1210
1211                 else {
1212                         /* I do not know why this is necessary, but it
1213                          * fixes strange effects (step/resume cause NMI
1214                          * after reset) on LM3S6918 -- Michael Schwingen
1215                          */
1216                         uint32_t tmp;
1217                         mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1218                 }
1219         }
1220
1221         target->state = TARGET_RESET;
1222         jtag_sleep(50000);
1223
1224         register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1225
1226         /* now return stored error code if any */
1227         if (retval != ERROR_OK)
1228                 return retval;
1229
1230         if (target->reset_halt) {
1231                 retval = target_halt(target);
1232                 if (retval != ERROR_OK)
1233                         return retval;
1234         }
1235
1236         return ERROR_OK;
1237 }
1238
1239 static int cortex_m_deassert_reset(struct target *target)
1240 {
1241         struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1242
1243         LOG_DEBUG("target->state: %s",
1244                 target_state_name(target));
1245
1246         /* deassert reset lines */
1247         adapter_deassert_reset();
1248
1249         enum reset_types jtag_reset_config = jtag_get_reset_config();
1250
1251         if ((jtag_reset_config & RESET_HAS_SRST) &&
1252             !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1253                 target_was_examined(target)) {
1254                 int retval = dap_dp_init(armv7m->debug_ap->dap);
1255                 if (retval != ERROR_OK) {
1256                         LOG_ERROR("DP initialisation failed");
1257                         return retval;
1258                 }
1259         }
1260
1261         return ERROR_OK;
1262 }
1263
1264 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1265 {
1266         int retval;
1267         int fp_num = 0;
1268         struct cortex_m_common *cortex_m = target_to_cm(target);
1269         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1270
1271         if (breakpoint->set) {
1272                 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1273                 return ERROR_OK;
1274         }
1275
1276         if (breakpoint->type == BKPT_HARD) {
1277                 uint32_t fpcr_value;
1278                 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1279                         fp_num++;
1280                 if (fp_num >= cortex_m->fp_num_code) {
1281                         LOG_ERROR("Can not find free FPB Comparator!");
1282                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1283                 }
1284                 breakpoint->set = fp_num + 1;
1285                 fpcr_value = breakpoint->address | 1;
1286                 if (cortex_m->fp_rev == 0) {
1287                         if (breakpoint->address > 0x1FFFFFFF) {
1288                                 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1289                                 return ERROR_FAIL;
1290                         }
1291                         uint32_t hilo;
1292                         hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1293                         fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1294                 } else if (cortex_m->fp_rev > 1) {
1295                         LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1296                         return ERROR_FAIL;
1297                 }
1298                 comparator_list[fp_num].used = true;
1299                 comparator_list[fp_num].fpcr_value = fpcr_value;
1300                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1301                         comparator_list[fp_num].fpcr_value);
1302                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1303                         fp_num,
1304                         comparator_list[fp_num].fpcr_value);
1305                 if (!cortex_m->fpb_enabled) {
1306                         LOG_DEBUG("FPB wasn't enabled, do it now");
1307                         retval = cortex_m_enable_fpb(target);
1308                         if (retval != ERROR_OK) {
1309                                 LOG_ERROR("Failed to enable the FPB");
1310                                 return retval;
1311                         }
1312
1313                         cortex_m->fpb_enabled = true;
1314                 }
1315         } else if (breakpoint->type == BKPT_SOFT) {
1316                 uint8_t code[4];
1317
1318                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1319                  * semihosting; don't use that.  Otherwise the BKPT
1320                  * parameter is arbitrary.
1321                  */
1322                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1323                 retval = target_read_memory(target,
1324                                 breakpoint->address & 0xFFFFFFFE,
1325                                 breakpoint->length, 1,
1326                                 breakpoint->orig_instr);
1327                 if (retval != ERROR_OK)
1328                         return retval;
1329                 retval = target_write_memory(target,
1330                                 breakpoint->address & 0xFFFFFFFE,
1331                                 breakpoint->length, 1,
1332                                 code);
1333                 if (retval != ERROR_OK)
1334                         return retval;
1335                 breakpoint->set = true;
1336         }
1337
1338         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1339                 breakpoint->unique_id,
1340                 (int)(breakpoint->type),
1341                 breakpoint->address,
1342                 breakpoint->length,
1343                 breakpoint->set);
1344
1345         return ERROR_OK;
1346 }
1347
1348 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1349 {
1350         int retval;
1351         struct cortex_m_common *cortex_m = target_to_cm(target);
1352         struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1353
1354         if (!breakpoint->set) {
1355                 LOG_WARNING("breakpoint not set");
1356                 return ERROR_OK;
1357         }
1358
1359         LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1360                 breakpoint->unique_id,
1361                 (int)(breakpoint->type),
1362                 breakpoint->address,
1363                 breakpoint->length,
1364                 breakpoint->set);
1365
1366         if (breakpoint->type == BKPT_HARD) {
1367                 int fp_num = breakpoint->set - 1;
1368                 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1369                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1370                         return ERROR_OK;
1371                 }
1372                 comparator_list[fp_num].used = false;
1373                 comparator_list[fp_num].fpcr_value = 0;
1374                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1375                         comparator_list[fp_num].fpcr_value);
1376         } else {
1377                 /* restore original instruction (kept in target endianness) */
1378                 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1379                                         breakpoint->length, 1,
1380                                         breakpoint->orig_instr);
1381                 if (retval != ERROR_OK)
1382                         return retval;
1383         }
1384         breakpoint->set = false;
1385
1386         return ERROR_OK;
1387 }
1388
1389 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1390 {
1391         if (breakpoint->length == 3) {
1392                 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1393                 breakpoint->length = 2;
1394         }
1395
1396         if ((breakpoint->length != 2)) {
1397                 LOG_INFO("only breakpoints of two bytes length supported");
1398                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1399         }
1400
1401         return cortex_m_set_breakpoint(target, breakpoint);
1402 }
1403
1404 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1405 {
1406         if (!breakpoint->set)
1407                 return ERROR_OK;
1408
1409         return cortex_m_unset_breakpoint(target, breakpoint);
1410 }
1411
1412 static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1413 {
1414         int dwt_num = 0;
1415         struct cortex_m_common *cortex_m = target_to_cm(target);
1416
1417         /* REVISIT Don't fully trust these "not used" records ... users
1418          * may set up breakpoints by hand, e.g. dual-address data value
1419          * watchpoint using comparator #1; comparator #0 matching cycle
1420          * count; send data trace info through ITM and TPIU; etc
1421          */
1422         struct cortex_m_dwt_comparator *comparator;
1423
1424         for (comparator = cortex_m->dwt_comparator_list;
1425                 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1426                 comparator++, dwt_num++)
1427                 continue;
1428         if (dwt_num >= cortex_m->dwt_num_comp) {
1429                 LOG_ERROR("Can not find free DWT Comparator");
1430                 return ERROR_FAIL;
1431         }
1432         comparator->used = true;
1433         watchpoint->set = dwt_num + 1;
1434
1435         comparator->comp = watchpoint->address;
1436         target_write_u32(target, comparator->dwt_comparator_address + 0,
1437                 comparator->comp);
1438
1439         if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1440                 uint32_t mask = 0, temp;
1441
1442                 /* watchpoint params were validated earlier */
1443                 temp = watchpoint->length;
1444                 while (temp) {
1445                         temp >>= 1;
1446                         mask++;
1447                 }
1448                 mask--;
1449
1450                 comparator->mask = mask;
1451                 target_write_u32(target, comparator->dwt_comparator_address + 4,
1452                         comparator->mask);
1453
1454                 switch (watchpoint->rw) {
1455                 case WPT_READ:
1456                         comparator->function = 5;
1457                         break;
1458                 case WPT_WRITE:
1459                         comparator->function = 6;
1460                         break;
1461                 case WPT_ACCESS:
1462                         comparator->function = 7;
1463                         break;
1464                 }
1465         } else {
1466                 uint32_t data_size = watchpoint->length >> 1;
1467                 comparator->mask = (watchpoint->length >> 1) | 1;
1468
1469                 switch (watchpoint->rw) {
1470                 case WPT_ACCESS:
1471                         comparator->function = 4;
1472                         break;
1473                 case WPT_WRITE:
1474                         comparator->function = 5;
1475                         break;
1476                 case WPT_READ:
1477                         comparator->function = 6;
1478                         break;
1479                 }
1480                 comparator->function = comparator->function | (1 << 4) |
1481                                 (data_size << 10);
1482         }
1483
1484         target_write_u32(target, comparator->dwt_comparator_address + 8,
1485                 comparator->function);
1486
1487         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1488                 watchpoint->unique_id, dwt_num,
1489                 (unsigned) comparator->comp,
1490                 (unsigned) comparator->mask,
1491                 (unsigned) comparator->function);
1492         return ERROR_OK;
1493 }
1494
1495 static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1496 {
1497         struct cortex_m_common *cortex_m = target_to_cm(target);
1498         struct cortex_m_dwt_comparator *comparator;
1499         int dwt_num;
1500
1501         if (!watchpoint->set) {
1502                 LOG_WARNING("watchpoint (wpid: %d) not set",
1503                         watchpoint->unique_id);
1504                 return ERROR_OK;
1505         }
1506
1507         dwt_num = watchpoint->set - 1;
1508
1509         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1510                 watchpoint->unique_id, dwt_num,
1511                 (unsigned) watchpoint->address);
1512
1513         if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1514                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1515                 return ERROR_OK;
1516         }
1517
1518         comparator = cortex_m->dwt_comparator_list + dwt_num;
1519         comparator->used = false;
1520         comparator->function = 0;
1521         target_write_u32(target, comparator->dwt_comparator_address + 8,
1522                 comparator->function);
1523
1524         watchpoint->set = false;
1525
1526         return ERROR_OK;
1527 }
1528
1529 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1530 {
1531         struct cortex_m_common *cortex_m = target_to_cm(target);
1532
1533         if (cortex_m->dwt_comp_available < 1) {
1534                 LOG_DEBUG("no comparators?");
1535                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1536         }
1537
1538         /* hardware doesn't support data value masking */
1539         if (watchpoint->mask != ~(uint32_t)0) {
1540                 LOG_DEBUG("watchpoint value masks not supported");
1541                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1542         }
1543
1544         /* hardware allows address masks of up to 32K */
1545         unsigned mask;
1546
1547         for (mask = 0; mask < 16; mask++) {
1548                 if ((1u << mask) == watchpoint->length)
1549                         break;
1550         }
1551         if (mask == 16) {
1552                 LOG_DEBUG("unsupported watchpoint length");
1553                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1554         }
1555         if (watchpoint->address & ((1 << mask) - 1)) {
1556                 LOG_DEBUG("watchpoint address is unaligned");
1557                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1558         }
1559
1560         /* Caller doesn't seem to be able to describe watching for data
1561          * values of zero; that flags "no value".
1562          *
1563          * REVISIT This DWT may well be able to watch for specific data
1564          * values.  Requires comparator #1 to set DATAVMATCH and match
1565          * the data, and another comparator (DATAVADDR0) matching addr.
1566          */
1567         if (watchpoint->value) {
1568                 LOG_DEBUG("data value watchpoint not YET supported");
1569                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1570         }
1571
1572         cortex_m->dwt_comp_available--;
1573         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1574
1575         return ERROR_OK;
1576 }
1577
1578 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1579 {
1580         struct cortex_m_common *cortex_m = target_to_cm(target);
1581
1582         /* REVISIT why check? DWT can be updated with core running ... */
1583         if (target->state != TARGET_HALTED) {
1584                 LOG_WARNING("target not halted");
1585                 return ERROR_TARGET_NOT_HALTED;
1586         }
1587
1588         if (watchpoint->set)
1589                 cortex_m_unset_watchpoint(target, watchpoint);
1590
1591         cortex_m->dwt_comp_available++;
1592         LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1593
1594         return ERROR_OK;
1595 }
1596
1597 void cortex_m_enable_watchpoints(struct target *target)
1598 {
1599         struct watchpoint *watchpoint = target->watchpoints;
1600
1601         /* set any pending watchpoints */
1602         while (watchpoint) {
1603                 if (!watchpoint->set)
1604                         cortex_m_set_watchpoint(target, watchpoint);
1605                 watchpoint = watchpoint->next;
1606         }
1607 }
1608
1609 static int cortex_m_load_core_reg_u32(struct target *target,
1610                 uint32_t regsel, uint32_t *value)
1611 {
1612         int retval;
1613
1614         switch (regsel) {
1615                 case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
1616                         /* read a normal core register */
1617                         retval = cortexm_dap_read_coreregister_u32(target, value, regsel);
1618
1619                         if (retval != ERROR_OK) {
1620                                 LOG_ERROR("JTAG failure %i", retval);
1621                                 return ERROR_JTAG_DEVICE_ERROR;
1622                         }
1623                         LOG_DEBUG("load from core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
1624                         break;
1625
1626                 case ARMV7M_REGSEL_FPSCR:
1627                         /* Floating-point Status and Registers */
1628                         retval = target_write_u32(target, DCB_DCRSR, ARMV7M_REGSEL_FPSCR);
1629                         if (retval != ERROR_OK)
1630                                 return retval;
1631                         retval = target_read_u32(target, DCB_DCRDR, value);
1632                         if (retval != ERROR_OK)
1633                                 return retval;
1634                         LOG_DEBUG("load from FPSCR  value 0x%" PRIx32, *value);
1635                         break;
1636
1637                 case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
1638                         /* Floating-point Status and Registers */
1639                         retval = target_write_u32(target, DCB_DCRSR, regsel);
1640                         if (retval != ERROR_OK)
1641                                 return retval;
1642                         retval = target_read_u32(target, DCB_DCRDR, value);
1643                         if (retval != ERROR_OK)
1644                                 return retval;
1645                         LOG_DEBUG("load from FPU reg S%d  value 0x%" PRIx32,
1646                                   (int)(regsel - ARMV7M_REGSEL_S0), *value);
1647                         break;
1648
1649                 case ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL:
1650                         retval = cortexm_dap_read_coreregister_u32(target, value, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
1651                         if (retval != ERROR_OK)
1652                                 return retval;
1653
1654                         LOG_DEBUG("load from special reg PRIMASK/BASEPRI/FAULTMASK/CONTROL value 0x%" PRIx32, *value);
1655                         break;
1656
1657                 default:
1658                         return ERROR_COMMAND_SYNTAX_ERROR;
1659         }
1660
1661         return ERROR_OK;
1662 }
1663
1664 static int cortex_m_store_core_reg_u32(struct target *target,
1665                 uint32_t regsel, uint32_t value)
1666 {
1667         int retval;
1668         struct armv7m_common *armv7m = target_to_armv7m(target);
1669
1670         switch (regsel) {
1671                 case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
1672                         retval = cortexm_dap_write_coreregister_u32(target, value, regsel);
1673                         if (retval != ERROR_OK) {
1674                                 struct reg *r;
1675
1676                                 LOG_ERROR("JTAG failure");
1677                                 r = armv7m->arm.core_cache->reg_list + regsel; /* TODO: don't use regsel as register index */
1678                                 r->dirty = r->valid;
1679                                 return ERROR_JTAG_DEVICE_ERROR;
1680                         }
1681                         LOG_DEBUG("write core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, value);
1682                         break;
1683
1684                 case ARMV7M_REGSEL_FPSCR:
1685                         /* Floating-point Status and Registers */
1686                         retval = target_write_u32(target, DCB_DCRDR, value);
1687                         if (retval != ERROR_OK)
1688                                 return retval;
1689                         retval = target_write_u32(target, DCB_DCRSR, ARMV7M_REGSEL_FPSCR | DCRSR_WnR);
1690                         if (retval != ERROR_OK)
1691                                 return retval;
1692                         LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1693                         break;
1694
1695                 case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
1696                         /* Floating-point Status and Registers */
1697                         retval = target_write_u32(target, DCB_DCRDR, value);
1698                         if (retval != ERROR_OK)
1699                                 return retval;
1700                         retval = target_write_u32(target, DCB_DCRSR, regsel | DCRSR_WnR);
1701                         if (retval != ERROR_OK)
1702                                 return retval;
1703                         LOG_DEBUG("write FPU reg S%d  value 0x%" PRIx32,
1704                                   (int)(regsel - ARMV7M_REGSEL_S0), value);
1705                         break;
1706
1707                 case ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL:
1708                         cortexm_dap_write_coreregister_u32(target, value, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
1709
1710                         LOG_DEBUG("write special reg PRIMASK/BASEPRI/FAULTMASK/CONTROL value 0x%" PRIx32, value);
1711                         break;
1712
1713                 default:
1714                         return ERROR_COMMAND_SYNTAX_ERROR;
1715         }
1716
1717         return ERROR_OK;
1718 }
1719
1720 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1721         uint32_t size, uint32_t count, uint8_t *buffer)
1722 {
1723         struct armv7m_common *armv7m = target_to_armv7m(target);
1724
1725         if (armv7m->arm.is_armv6m) {
1726                 /* armv6m does not handle unaligned memory access */
1727                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1728                         return ERROR_TARGET_UNALIGNED_ACCESS;
1729         }
1730
1731         return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1732 }
1733
1734 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1735         uint32_t size, uint32_t count, const uint8_t *buffer)
1736 {
1737         struct armv7m_common *armv7m = target_to_armv7m(target);
1738
1739         if (armv7m->arm.is_armv6m) {
1740                 /* armv6m does not handle unaligned memory access */
1741                 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1742                         return ERROR_TARGET_UNALIGNED_ACCESS;
1743         }
1744
1745         return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1746 }
1747
1748 static int cortex_m_init_target(struct command_context *cmd_ctx,
1749         struct target *target)
1750 {
1751         armv7m_build_reg_cache(target);
1752         arm_semihosting_init(target);
1753         return ERROR_OK;
1754 }
1755
1756 void cortex_m_deinit_target(struct target *target)
1757 {
1758         struct cortex_m_common *cortex_m = target_to_cm(target);
1759
1760         free(cortex_m->fp_comparator_list);
1761
1762         cortex_m_dwt_free(target);
1763         armv7m_free_reg_cache(target);
1764
1765         free(target->private_config);
1766         free(cortex_m);
1767 }
1768
1769 int cortex_m_profiling(struct target *target, uint32_t *samples,
1770                               uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1771 {
1772         struct timeval timeout, now;
1773         struct armv7m_common *armv7m = target_to_armv7m(target);
1774         uint32_t reg_value;
1775         int retval;
1776
1777         retval = target_read_u32(target, DWT_PCSR, &reg_value);
1778         if (retval != ERROR_OK) {
1779                 LOG_ERROR("Error while reading PCSR");
1780                 return retval;
1781         }
1782         if (reg_value == 0) {
1783                 LOG_INFO("PCSR sampling not supported on this processor.");
1784                 return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
1785         }
1786
1787         gettimeofday(&timeout, NULL);
1788         timeval_add_time(&timeout, seconds, 0);
1789
1790         LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1791
1792         /* Make sure the target is running */
1793         target_poll(target);
1794         if (target->state == TARGET_HALTED)
1795                 retval = target_resume(target, 1, 0, 0, 0);
1796
1797         if (retval != ERROR_OK) {
1798                 LOG_ERROR("Error while resuming target");
1799                 return retval;
1800         }
1801
1802         uint32_t sample_count = 0;
1803
1804         for (;;) {
1805                 if (armv7m && armv7m->debug_ap) {
1806                         uint32_t read_count = max_num_samples - sample_count;
1807                         if (read_count > 1024)
1808                                 read_count = 1024;
1809
1810                         retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1811                                                 (void *)&samples[sample_count],
1812                                                 4, read_count, DWT_PCSR);
1813                         sample_count += read_count;
1814                 } else {
1815                         target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1816                 }
1817
1818                 if (retval != ERROR_OK) {
1819                         LOG_ERROR("Error while reading PCSR");
1820                         return retval;
1821                 }
1822
1823
1824                 gettimeofday(&now, NULL);
1825                 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1826                         LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1827                         break;
1828                 }
1829         }
1830
1831         *num_samples = sample_count;
1832         return retval;
1833 }
1834
1835
1836 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1837  * on r/w if the core is not running, and clear on resume or reset ... or
1838  * at least, in a post_restore_context() method.
1839  */
1840
1841 struct dwt_reg_state {
1842         struct target *target;
1843         uint32_t addr;
1844         uint8_t value[4];               /* scratch/cache */
1845 };
1846
1847 static int cortex_m_dwt_get_reg(struct reg *reg)
1848 {
1849         struct dwt_reg_state *state = reg->arch_info;
1850
1851         uint32_t tmp;
1852         int retval = target_read_u32(state->target, state->addr, &tmp);
1853         if (retval != ERROR_OK)
1854                 return retval;
1855
1856         buf_set_u32(state->value, 0, 32, tmp);
1857         return ERROR_OK;
1858 }
1859
1860 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1861 {
1862         struct dwt_reg_state *state = reg->arch_info;
1863
1864         return target_write_u32(state->target, state->addr,
1865                         buf_get_u32(buf, 0, reg->size));
1866 }
1867
1868 struct dwt_reg {
1869         uint32_t addr;
1870         const char *name;
1871         unsigned size;
1872 };
1873
1874 static const struct dwt_reg dwt_base_regs[] = {
1875         { DWT_CTRL, "dwt_ctrl", 32, },
1876         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1877          * increments while the core is asleep.
1878          */
1879         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1880         /* plus some 8 bit counters, useful for profiling with TPIU */
1881 };
1882
1883 static const struct dwt_reg dwt_comp[] = {
1884 #define DWT_COMPARATOR(i) \
1885                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1886                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1887                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1888         DWT_COMPARATOR(0),
1889         DWT_COMPARATOR(1),
1890         DWT_COMPARATOR(2),
1891         DWT_COMPARATOR(3),
1892         DWT_COMPARATOR(4),
1893         DWT_COMPARATOR(5),
1894         DWT_COMPARATOR(6),
1895         DWT_COMPARATOR(7),
1896         DWT_COMPARATOR(8),
1897         DWT_COMPARATOR(9),
1898         DWT_COMPARATOR(10),
1899         DWT_COMPARATOR(11),
1900         DWT_COMPARATOR(12),
1901         DWT_COMPARATOR(13),
1902         DWT_COMPARATOR(14),
1903         DWT_COMPARATOR(15),
1904 #undef DWT_COMPARATOR
1905 };
1906
1907 static const struct reg_arch_type dwt_reg_type = {
1908         .get = cortex_m_dwt_get_reg,
1909         .set = cortex_m_dwt_set_reg,
1910 };
1911
1912 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1913 {
1914         struct dwt_reg_state *state;
1915
1916         state = calloc(1, sizeof(*state));
1917         if (!state)
1918                 return;
1919         state->addr = d->addr;
1920         state->target = t;
1921
1922         r->name = d->name;
1923         r->size = d->size;
1924         r->value = state->value;
1925         r->arch_info = state;
1926         r->type = &dwt_reg_type;
1927 }
1928
1929 static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1930 {
1931         uint32_t dwtcr;
1932         struct reg_cache *cache;
1933         struct cortex_m_dwt_comparator *comparator;
1934         int reg, i;
1935
1936         target_read_u32(target, DWT_CTRL, &dwtcr);
1937         LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1938         if (!dwtcr) {
1939                 LOG_DEBUG("no DWT");
1940                 return;
1941         }
1942
1943         target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
1944         LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
1945
1946         cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1947         cm->dwt_comp_available = cm->dwt_num_comp;
1948         cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1949                         sizeof(struct cortex_m_dwt_comparator));
1950         if (!cm->dwt_comparator_list) {
1951 fail0:
1952                 cm->dwt_num_comp = 0;
1953                 LOG_ERROR("out of mem");
1954                 return;
1955         }
1956
1957         cache = calloc(1, sizeof(*cache));
1958         if (!cache) {
1959 fail1:
1960                 free(cm->dwt_comparator_list);
1961                 goto fail0;
1962         }
1963         cache->name = "Cortex-M DWT registers";
1964         cache->num_regs = 2 + cm->dwt_num_comp * 3;
1965         cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
1966         if (!cache->reg_list) {
1967                 free(cache);
1968                 goto fail1;
1969         }
1970
1971         for (reg = 0; reg < 2; reg++)
1972                 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1973                         dwt_base_regs + reg);
1974
1975         comparator = cm->dwt_comparator_list;
1976         for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1977                 int j;
1978
1979                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1980                 for (j = 0; j < 3; j++, reg++)
1981                         cortex_m_dwt_addreg(target, cache->reg_list + reg,
1982                                 dwt_comp + 3 * i + j);
1983
1984                 /* make sure we clear any watchpoints enabled on the target */
1985                 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1986         }
1987
1988         *register_get_last_cache_p(&target->reg_cache) = cache;
1989         cm->dwt_cache = cache;
1990
1991         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1992                 dwtcr, cm->dwt_num_comp,
1993                 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1994
1995         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1996          * implement single-address data value watchpoints ... so we
1997          * won't need to check it later, when asked to set one up.
1998          */
1999 }
2000
2001 static void cortex_m_dwt_free(struct target *target)
2002 {
2003         struct cortex_m_common *cm = target_to_cm(target);
2004         struct reg_cache *cache = cm->dwt_cache;
2005
2006         free(cm->dwt_comparator_list);
2007         cm->dwt_comparator_list = NULL;
2008         cm->dwt_num_comp = 0;
2009
2010         if (cache) {
2011                 register_unlink_cache(&target->reg_cache, cache);
2012
2013                 if (cache->reg_list) {
2014                         for (size_t i = 0; i < cache->num_regs; i++)
2015                                 free(cache->reg_list[i].arch_info);
2016                         free(cache->reg_list);
2017                 }
2018                 free(cache);
2019         }
2020         cm->dwt_cache = NULL;
2021 }
2022
2023 #define MVFR0 0xe000ef40
2024 #define MVFR1 0xe000ef44
2025
2026 #define MVFR0_DEFAULT_M4 0x10110021
2027 #define MVFR1_DEFAULT_M4 0x11000011
2028
2029 #define MVFR0_DEFAULT_M7_SP 0x10110021
2030 #define MVFR0_DEFAULT_M7_DP 0x10110221
2031 #define MVFR1_DEFAULT_M7_SP 0x11000011
2032 #define MVFR1_DEFAULT_M7_DP 0x12000011
2033
2034 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
2035                 struct adiv5_ap **debug_ap)
2036 {
2037         if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
2038                 return ERROR_OK;
2039
2040         return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
2041 }
2042
2043 int cortex_m_examine(struct target *target)
2044 {
2045         int retval;
2046         uint32_t cpuid, fpcr, mvfr0, mvfr1;
2047         int i;
2048         struct cortex_m_common *cortex_m = target_to_cm(target);
2049         struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2050         struct armv7m_common *armv7m = target_to_armv7m(target);
2051
2052         /* stlink shares the examine handler but does not support
2053          * all its calls */
2054         if (!armv7m->stlink) {
2055                 if (cortex_m->apsel == DP_APSEL_INVALID) {
2056                         /* Search for the MEM-AP */
2057                         retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
2058                         if (retval != ERROR_OK) {
2059                                 LOG_ERROR("Could not find MEM-AP to control the core");
2060                                 return retval;
2061                         }
2062                 } else {
2063                         armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2064                 }
2065
2066                 /* Leave (only) generic DAP stuff for debugport_init(); */
2067                 armv7m->debug_ap->memaccess_tck = 8;
2068
2069                 retval = mem_ap_init(armv7m->debug_ap);
2070                 if (retval != ERROR_OK)
2071                         return retval;
2072         }
2073
2074         if (!target_was_examined(target)) {
2075                 target_set_examined(target);
2076
2077                 /* Read from Device Identification Registers */
2078                 retval = target_read_u32(target, CPUID, &cpuid);
2079                 if (retval != ERROR_OK)
2080                         return retval;
2081
2082                 /* Get CPU Type */
2083                 i = (cpuid >> 4) & 0xf;
2084
2085                 /* Check if it is an ARMv8-M core */
2086                 armv7m->arm.is_armv8m = true;
2087
2088                 switch (cpuid & ARM_CPUID_PARTNO_MASK) {
2089                         case CORTEX_M23_PARTNO:
2090                                 i = 23;
2091                                 break;
2092                         case CORTEX_M33_PARTNO:
2093                                 i = 33;
2094                                 break;
2095                         case CORTEX_M35P_PARTNO:
2096                                 i = 35;
2097                                 break;
2098                         case CORTEX_M55_PARTNO:
2099                                 i = 55;
2100                                 break;
2101                         default:
2102                                 armv7m->arm.is_armv8m = false;
2103                                 break;
2104                 }
2105
2106
2107                 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2108                                 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2109                 cortex_m->maskints_erratum = false;
2110                 if (i == 7) {
2111                         uint8_t rev, patch;
2112                         rev = (cpuid >> 20) & 0xf;
2113                         patch = (cpuid >> 0) & 0xf;
2114                         if ((rev == 0) && (patch < 2)) {
2115                                 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2116                                 cortex_m->maskints_erratum = true;
2117                         }
2118                 }
2119                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2120
2121                 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2122                 cortex_m->vectreset_supported = i > 1;
2123
2124                 if (i == 4) {
2125                         target_read_u32(target, MVFR0, &mvfr0);
2126                         target_read_u32(target, MVFR1, &mvfr1);
2127
2128                         /* test for floating point feature on Cortex-M4 */
2129                         if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2130                                 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2131                                 armv7m->fp_feature = FPv4_SP;
2132                         }
2133                 } else if (i == 7 || i == 33 || i == 35 || i == 55) {
2134                         target_read_u32(target, MVFR0, &mvfr0);
2135                         target_read_u32(target, MVFR1, &mvfr1);
2136
2137                         /* test for floating point features on Cortex-M7 */
2138                         if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2139                                 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2140                                 armv7m->fp_feature = FPv5_SP;
2141                         } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2142                                 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2143                                 armv7m->fp_feature = FPv5_DP;
2144                         }
2145                 } else if (i == 0) {
2146                         /* Cortex-M0 does not support unaligned memory access */
2147                         armv7m->arm.is_armv6m = true;
2148                 }
2149
2150                 if (armv7m->fp_feature == FP_NONE &&
2151                     armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2152                         /* free unavailable FPU registers */
2153                         size_t idx;
2154
2155                         for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2156                              idx < armv7m->arm.core_cache->num_regs;
2157                              idx++) {
2158                                 free(armv7m->arm.core_cache->reg_list[idx].value);
2159                                 free(armv7m->arm.core_cache->reg_list[idx].feature);
2160                                 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2161                         }
2162                         armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2163                 }
2164
2165                 if (!armv7m->stlink) {
2166                         if (i == 3 || i == 4)
2167                                 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2168                                  * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2169                                 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2170                         else if (i == 7)
2171                                 /* Cortex-M7 has only 1024 bytes autoincrement range */
2172                                 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2173                 }
2174
2175                 /* Enable debug requests */
2176                 retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
2177                 if (retval != ERROR_OK)
2178                         return retval;
2179                 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
2180                         uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
2181
2182                         retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
2183                         if (retval != ERROR_OK)
2184                                 return retval;
2185                         cortex_m->dcb_dhcsr = dhcsr;
2186                 }
2187
2188                 /* Configure trace modules */
2189                 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2190                 if (retval != ERROR_OK)
2191                         return retval;
2192
2193                 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2194                         armv7m_trace_tpiu_config(target);
2195                         armv7m_trace_itm_config(target);
2196                 }
2197
2198                 /* NOTE: FPB and DWT are both optional. */
2199
2200                 /* Setup FPB */
2201                 target_read_u32(target, FP_CTRL, &fpcr);
2202                 /* bits [14:12] and [7:4] */
2203                 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2204                 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2205                 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2206                    Revision is zero base, fp_rev == 1 means Rev.2 ! */
2207                 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2208                 free(cortex_m->fp_comparator_list);
2209                 cortex_m->fp_comparator_list = calloc(
2210                                 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2211                                 sizeof(struct cortex_m_fp_comparator));
2212                 cortex_m->fpb_enabled = fpcr & 1;
2213                 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2214                         cortex_m->fp_comparator_list[i].type =
2215                                 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2216                         cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2217
2218                         /* make sure we clear any breakpoints enabled on the target */
2219                         target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2220                 }
2221                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2222                         fpcr,
2223                         cortex_m->fp_num_code,
2224                         cortex_m->fp_num_lit);
2225
2226                 /* Setup DWT */
2227                 cortex_m_dwt_free(target);
2228                 cortex_m_dwt_setup(cortex_m, target);
2229
2230                 /* These hardware breakpoints only work for code in flash! */
2231                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2232                         target_name(target),
2233                         cortex_m->fp_num_code,
2234                         cortex_m->dwt_num_comp);
2235         }
2236
2237         return ERROR_OK;
2238 }
2239
2240 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2241 {
2242         struct armv7m_common *armv7m = target_to_armv7m(target);
2243         uint16_t dcrdr;
2244         uint8_t buf[2];
2245         int retval;
2246
2247         retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2248         if (retval != ERROR_OK)
2249                 return retval;
2250
2251         dcrdr = target_buffer_get_u16(target, buf);
2252         *ctrl = (uint8_t)dcrdr;
2253         *value = (uint8_t)(dcrdr >> 8);
2254
2255         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2256
2257         /* write ack back to software dcc register
2258          * signify we have read data */
2259         if (dcrdr & (1 << 0)) {
2260                 target_buffer_set_u16(target, buf, 0);
2261                 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2262                 if (retval != ERROR_OK)
2263                         return retval;
2264         }
2265
2266         return ERROR_OK;
2267 }
2268
2269 static int cortex_m_target_request_data(struct target *target,
2270         uint32_t size, uint8_t *buffer)
2271 {
2272         uint8_t data;
2273         uint8_t ctrl;
2274         uint32_t i;
2275
2276         for (i = 0; i < (size * 4); i++) {
2277                 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2278                 if (retval != ERROR_OK)
2279                         return retval;
2280                 buffer[i] = data;
2281         }
2282
2283         return ERROR_OK;
2284 }
2285
2286 static int cortex_m_handle_target_request(void *priv)
2287 {
2288         struct target *target = priv;
2289         if (!target_was_examined(target))
2290                 return ERROR_OK;
2291
2292         if (!target->dbg_msg_enabled)
2293                 return ERROR_OK;
2294
2295         if (target->state == TARGET_RUNNING) {
2296                 uint8_t data;
2297                 uint8_t ctrl;
2298                 int retval;
2299
2300                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2301                 if (retval != ERROR_OK)
2302                         return retval;
2303
2304                 /* check if we have data */
2305                 if (ctrl & (1 << 0)) {
2306                         uint32_t request;
2307
2308                         /* we assume target is quick enough */
2309                         request = data;
2310                         for (int i = 1; i <= 3; i++) {
2311                                 retval = cortex_m_dcc_read(target, &data, &ctrl);
2312                                 if (retval != ERROR_OK)
2313                                         return retval;
2314                                 request |= ((uint32_t)data << (i * 8));
2315                         }
2316                         target_request(target, request);
2317                 }
2318         }
2319
2320         return ERROR_OK;
2321 }
2322
2323 static int cortex_m_init_arch_info(struct target *target,
2324         struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2325 {
2326         struct armv7m_common *armv7m = &cortex_m->armv7m;
2327
2328         armv7m_init_arch_info(target, armv7m);
2329
2330         /* default reset mode is to use srst if fitted
2331          * if not it will use CORTEX_M3_RESET_VECTRESET */
2332         cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2333
2334         armv7m->arm.dap = dap;
2335
2336         /* register arch-specific functions */
2337         armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2338
2339         armv7m->post_debug_entry = NULL;
2340
2341         armv7m->pre_restore_context = NULL;
2342
2343         armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2344         armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2345
2346         target_register_timer_callback(cortex_m_handle_target_request, 1,
2347                 TARGET_TIMER_TYPE_PERIODIC, target);
2348
2349         return ERROR_OK;
2350 }
2351
2352 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2353 {
2354         struct adiv5_private_config *pc;
2355
2356         pc = (struct adiv5_private_config *)target->private_config;
2357         if (adiv5_verify_config(pc) != ERROR_OK)
2358                 return ERROR_FAIL;
2359
2360         struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2361         if (cortex_m == NULL) {
2362                 LOG_ERROR("No memory creating target");
2363                 return ERROR_FAIL;
2364         }
2365
2366         cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2367         cortex_m->apsel = pc->ap_num;
2368
2369         cortex_m_init_arch_info(target, cortex_m, pc->dap);
2370
2371         return ERROR_OK;
2372 }
2373
2374 /*--------------------------------------------------------------------------*/
2375
2376 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2377         struct cortex_m_common *cm)
2378 {
2379         if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2380                 command_print(cmd, "target is not a Cortex-M");
2381                 return ERROR_TARGET_INVALID;
2382         }
2383         return ERROR_OK;
2384 }
2385
2386 /*
2387  * Only stuff below this line should need to verify that its target
2388  * is a Cortex-M3.  Everything else should have indirected through the
2389  * cortexm3_target structure, which is only used with CM3 targets.
2390  */
2391
2392 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2393 {
2394         struct target *target = get_current_target(CMD_CTX);
2395         struct cortex_m_common *cortex_m = target_to_cm(target);
2396         struct armv7m_common *armv7m = &cortex_m->armv7m;
2397         uint32_t demcr = 0;
2398         int retval;
2399
2400         static const struct {
2401                 char name[10];
2402                 unsigned mask;
2403         } vec_ids[] = {
2404                 { "hard_err",   VC_HARDERR, },
2405                 { "int_err",    VC_INTERR, },
2406                 { "bus_err",    VC_BUSERR, },
2407                 { "state_err",  VC_STATERR, },
2408                 { "chk_err",    VC_CHKERR, },
2409                 { "nocp_err",   VC_NOCPERR, },
2410                 { "mm_err",     VC_MMERR, },
2411                 { "reset",      VC_CORERESET, },
2412         };
2413
2414         retval = cortex_m_verify_pointer(CMD, cortex_m);
2415         if (retval != ERROR_OK)
2416                 return retval;
2417
2418         if (!target_was_examined(target)) {
2419                 LOG_ERROR("Target not examined yet");
2420                 return ERROR_FAIL;
2421         }
2422
2423         retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2424         if (retval != ERROR_OK)
2425                 return retval;
2426
2427         if (CMD_ARGC > 0) {
2428                 unsigned catch = 0;
2429
2430                 if (CMD_ARGC == 1) {
2431                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2432                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2433                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2434                                         | VC_MMERR | VC_CORERESET;
2435                                 goto write;
2436                         } else if (strcmp(CMD_ARGV[0], "none") == 0)
2437                                 goto write;
2438                 }
2439                 while (CMD_ARGC-- > 0) {
2440                         unsigned i;
2441                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2442                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2443                                         continue;
2444                                 catch |= vec_ids[i].mask;
2445                                 break;
2446                         }
2447                         if (i == ARRAY_SIZE(vec_ids)) {
2448                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2449                                 return ERROR_COMMAND_SYNTAX_ERROR;
2450                         }
2451                 }
2452 write:
2453                 /* For now, armv7m->demcr only stores vector catch flags. */
2454                 armv7m->demcr = catch;
2455
2456                 demcr &= ~0xffff;
2457                 demcr |= catch;
2458
2459                 /* write, but don't assume it stuck (why not??) */
2460                 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2461                 if (retval != ERROR_OK)
2462                         return retval;
2463                 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2464                 if (retval != ERROR_OK)
2465                         return retval;
2466
2467                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2468                  * Otherwise the vector catch hardware could fire when there's
2469                  * no debugger hooked up, causing much confusion...
2470                  */
2471         }
2472
2473         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2474                 command_print(CMD, "%9s: %s", vec_ids[i].name,
2475                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2476         }
2477
2478         return ERROR_OK;
2479 }
2480
2481 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2482 {
2483         struct target *target = get_current_target(CMD_CTX);
2484         struct cortex_m_common *cortex_m = target_to_cm(target);
2485         int retval;
2486
2487         static const Jim_Nvp nvp_maskisr_modes[] = {
2488                 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2489                 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2490                 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2491                 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2492                 { .name = NULL, .value = -1 },
2493         };
2494         const Jim_Nvp *n;
2495
2496
2497         retval = cortex_m_verify_pointer(CMD, cortex_m);
2498         if (retval != ERROR_OK)
2499                 return retval;
2500
2501         if (target->state != TARGET_HALTED) {
2502                 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2503                 return ERROR_OK;
2504         }
2505
2506         if (CMD_ARGC > 0) {
2507                 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2508                 if (n->name == NULL)
2509                         return ERROR_COMMAND_SYNTAX_ERROR;
2510                 cortex_m->isrmasking_mode = n->value;
2511                 cortex_m_set_maskints_for_halt(target);
2512         }
2513
2514         n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2515         command_print(CMD, "cortex_m interrupt mask %s", n->name);
2516
2517         return ERROR_OK;
2518 }
2519
2520 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2521 {
2522         struct target *target = get_current_target(CMD_CTX);
2523         struct cortex_m_common *cortex_m = target_to_cm(target);
2524         int retval;
2525         char *reset_config;
2526
2527         retval = cortex_m_verify_pointer(CMD, cortex_m);
2528         if (retval != ERROR_OK)
2529                 return retval;
2530
2531         if (CMD_ARGC > 0) {
2532                 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2533                         cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2534
2535                 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2536                         if (target_was_examined(target)
2537                                         && !cortex_m->vectreset_supported)
2538                                 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2539                         else
2540                                 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2541
2542                 } else
2543                         return ERROR_COMMAND_SYNTAX_ERROR;
2544         }
2545
2546         switch (cortex_m->soft_reset_config) {
2547                 case CORTEX_M_RESET_SYSRESETREQ:
2548                         reset_config = "sysresetreq";
2549                         break;
2550
2551                 case CORTEX_M_RESET_VECTRESET:
2552                         reset_config = "vectreset";
2553                         break;
2554
2555                 default:
2556                         reset_config = "unknown";
2557                         break;
2558         }
2559
2560         command_print(CMD, "cortex_m reset_config %s", reset_config);
2561
2562         return ERROR_OK;
2563 }
2564
2565 static const struct command_registration cortex_m_exec_command_handlers[] = {
2566         {
2567                 .name = "maskisr",
2568                 .handler = handle_cortex_m_mask_interrupts_command,
2569                 .mode = COMMAND_EXEC,
2570                 .help = "mask cortex_m interrupts",
2571                 .usage = "['auto'|'on'|'off'|'steponly']",
2572         },
2573         {
2574                 .name = "vector_catch",
2575                 .handler = handle_cortex_m_vector_catch_command,
2576                 .mode = COMMAND_EXEC,
2577                 .help = "configure hardware vectors to trigger debug entry",
2578                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2579         },
2580         {
2581                 .name = "reset_config",
2582                 .handler = handle_cortex_m_reset_config_command,
2583                 .mode = COMMAND_ANY,
2584                 .help = "configure software reset handling",
2585                 .usage = "['sysresetreq'|'vectreset']",
2586         },
2587         COMMAND_REGISTRATION_DONE
2588 };
2589 static const struct command_registration cortex_m_command_handlers[] = {
2590         {
2591                 .chain = armv7m_command_handlers,
2592         },
2593         {
2594                 .chain = armv7m_trace_command_handlers,
2595         },
2596         {
2597                 .name = "cortex_m",
2598                 .mode = COMMAND_EXEC,
2599                 .help = "Cortex-M command group",
2600                 .usage = "",
2601                 .chain = cortex_m_exec_command_handlers,
2602         },
2603         COMMAND_REGISTRATION_DONE
2604 };
2605
2606 struct target_type cortexm_target = {
2607         .name = "cortex_m",
2608         .deprecated_name = "cortex_m3",
2609
2610         .poll = cortex_m_poll,
2611         .arch_state = armv7m_arch_state,
2612
2613         .target_request_data = cortex_m_target_request_data,
2614
2615         .halt = cortex_m_halt,
2616         .resume = cortex_m_resume,
2617         .step = cortex_m_step,
2618
2619         .assert_reset = cortex_m_assert_reset,
2620         .deassert_reset = cortex_m_deassert_reset,
2621         .soft_reset_halt = cortex_m_soft_reset_halt,
2622
2623         .get_gdb_arch = arm_get_gdb_arch,
2624         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2625
2626         .read_memory = cortex_m_read_memory,
2627         .write_memory = cortex_m_write_memory,
2628         .checksum_memory = armv7m_checksum_memory,
2629         .blank_check_memory = armv7m_blank_check_memory,
2630
2631         .run_algorithm = armv7m_run_algorithm,
2632         .start_algorithm = armv7m_start_algorithm,
2633         .wait_algorithm = armv7m_wait_algorithm,
2634
2635         .add_breakpoint = cortex_m_add_breakpoint,
2636         .remove_breakpoint = cortex_m_remove_breakpoint,
2637         .add_watchpoint = cortex_m_add_watchpoint,
2638         .remove_watchpoint = cortex_m_remove_watchpoint,
2639
2640         .commands = cortex_m_command_handlers,
2641         .target_create = cortex_m_target_create,
2642         .target_jim_configure = adiv5_jim_configure,
2643         .init_target = cortex_m_init_target,
2644         .examine = cortex_m_examine,
2645         .deinit_target = cortex_m_deinit_target,
2646
2647         .profiling = cortex_m_profiling,
2648 };