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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2009 by Dirk Behme                                      *
  12  *   dirk.behme@gmail.com - copy from cortex_m3                            *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  ***************************************************************************/
  29 #ifndef CORTEX_A8_H
  30 #define CORTEX_A8_H
  31
  32 #include "register.h"
  33 #include "target.h"
  34 #include "armv7a.h"
  35
  36 extern char* cortex_a8_state_strings[];
  37
  38 #define CORTEX_A8_COMMON_MAGIC 0x411fc082
  39
  40 #define CPUID           0x54011D00
  41 /* Debug Control Block */
  42 #define CPUDBG_DIDR             0x000
  43 #define CPUDBG_WFAR             0x018
  44 #define CPUDBG_VCR      0x01C
  45 #define CPUDBG_ECR      0x024
  46 #define CPUDBG_DSCCR    0x028
  47 #define CPUDBG_DTRRX    0x080
  48 #define CPUDBG_ITR      0x084
  49 #define CPUDBG_DSCR     0x088
  50 #define CPUDBG_DTRTX    0x08c
  51 #define CPUDBG_DRCR     0x090
  52 #define CPUDBG_BVR_BASE 0x100
  53 #define CPUDBG_BCR_BASE 0x140
  54 #define CPUDBG_WVR_BASE 0x180
  55 #define CPUDBG_WCR_BASE 0x1C0
  56
  57 #define CPUDBG_OSLAR    0x300
  58 #define CPUDBG_OSLSR    0x304
  59 #define CPUDBG_OSSRR    0x308
  60
  61 #define CPUDBG_PRCR     0x310
  62 #define CPUDBG_PRSR     0x314
  63
  64 #define CPUDBG_CPUID    0xD00
  65 #define CPUDBG_CTYPR    0xD04
  66 #define CPUDBG_TTYPR    0xD0C
  67 #define CPUDBG_LOCKACCESS 0xFB0
  68 #define CPUDBG_LOCKSTATUS 0xFB4
  69 #define CPUDBG_AUTHSTATUS 0xFB8
  70
  71 #define BRP_NORMAL 0
  72 #define BRP_CONTEXT 1
  73
  74 /* DSCR Bit offset */
  75 #define DSCR_CORE_HALTED                0
  76 #define DSCR_CORE_RESTARTED     1
  77 #define DSCR_EXT_INT_EN                 13
  78 #define DSCR_HALT_DBG_MODE              14
  79 #define DSCR_MON_DBG_MODE               15
  80 #define DSCR_INSTR_COMP                 24
  81 #define DSCR_DTR_TX_FULL                29
  82 #define DSCR_DTR_RX_FULL                30
  83
  84 struct cortex_a8_brp
  85 {
  86         int used;
  87         int type;
  88         uint32_t value;
  89         uint32_t control;
  90         uint8_t         BRPn;
  91 };
  92
  93 struct cortex_a8_wrp
  94 {
  95         int used;
  96         int type;
  97         uint32_t value;
  98         uint32_t control;
  99         uint8_t         WRPn;
 100 };
 101
 102 struct cortex_a8_common
 103 {
 104         int common_magic;
 105         struct arm_jtag jtag_info;
 106
 107         /* Context information */
 108         uint32_t cpudbg_dscr;
 109         uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
 110         uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
 111
 112         /* Saved cp15 registers */
 113         uint32_t cp15_control_reg;
 114         uint32_t cp15_aux_control_reg;
 115
 116         /* Breakpoint register pairs */
 117         int brp_num_context;
 118         int brp_num;
 119         int brp_num_available;
 120 //      int brp_enabled;
 121         struct cortex_a8_brp *brp_list;
 122
 123         /* Watchpoint register pairs */
 124         int wrp_num;
 125         int wrp_num_available;
 126         struct cortex_a8_wrp *wrp_list;
 127
 128         /* Interrupts */
 129         int intlinesnum;
 130         uint32_t *intsetenable;
 131
 132         /* Use cortex_a8_read_regs_through_mem for fast register reads */
 133         int fast_reg_read;
 134
 135         struct armv7a_common armv7a_common;
 136 };
 137
 138 static inline struct cortex_a8_common *
 139 target_to_cortex_a8(struct target *target)
 140 {
 141         return container_of(target->arch_info, struct cortex_a8_common,
 142                         armv7a_common.armv4_5_common);
 143 }
 144
 145 int cortex_a8_init_arch_info(struct target *target,
 146                 struct cortex_a8_common *cortex_a8, struct jtag_tap *tap);
 147
 148 #endif /* CORTEX_A8_H */