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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2009 by Dirk Behme                                      *
  12  *   dirk.behme@gmail.com - copy from cortex_m3                            *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  ***************************************************************************/
  29 #ifndef CORTEX_A8_H
  30 #define CORTEX_A8_H
  31
  32 #include "register.h"
  33 #include "target.h"
  34 #include "armv7m.h"
  35
  36 extern char* cortex_a8_state_strings[];
  37
  38 #define CORTEX_A8_COMMON_MAGIC 0x411fc082
  39
  40 #define CPUID           0x54011D00
  41 /* Debug Control Block */
  42 #define DCB_DHCSR       0x54011DF0
  43 #define DCB_DCRSR       0x54011DF4
  44 #define DCB_DCRDR       0x54011DF8
  45 #define DCB_DEMCR       0x54011DFC
  46
  47 typedef struct  cortex_a8_fp_comparator_s
  48 {
  49         int used;
  50         int type;
  51         u32 fpcr_value;
  52         u32 fpcr_address;
  53 } cortex_a8_fp_comparator_t;
  54
  55 typedef struct  cortex_a8_dwt_comparator_s
  56 {
  57         int used;
  58         u32 comp;
  59         u32 mask;
  60         u32 function;
  61         u32 dwt_comparator_address;
  62 } cortex_a8_dwt_comparator_t;
  63
  64 typedef struct cortex_a8_common_s
  65 {
  66         int common_magic;
  67         arm_jtag_t jtag_info;
  68
  69         /* Context information */
  70         u32 dcb_dhcsr;
  71         u32 nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
  72         u32 nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
  73
  74         /* Flash Patch and Breakpoint (FPB) */
  75         int fp_num_lit;
  76         int fp_num_code;
  77         int fp_code_available;
  78         int fpb_enabled;
  79         int auto_bp_type;
  80         cortex_a8_fp_comparator_t *fp_comparator_list;
  81
  82         /* Data Watchpoint and Trace (DWT) */
  83         int dwt_num_comp;
  84         int dwt_comp_available;
  85         cortex_a8_dwt_comparator_t *dwt_comparator_list;
  86
  87         /* Interrupts */
  88         int intlinesnum;
  89         u32 *intsetenable;
  90
  91         armv7m_common_t armv7m;
  92         void *arch_info;
  93 } cortex_a8_common_t;
  94
  95 extern int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap);
  96 int cortex_a8_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  97 int cortex_a8_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  98
  99 #endif /* CORTEX_A8_H */