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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2009 by Dirk Behme                                      *
  12  *   dirk.behme@gmail.com - copy from cortex_m3                            *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  *                                                                         *
  29  *   Cortex-A8(tm) TRM, ARM DDI 0344H                                      *
  30  *                                                                         *
  31  ***************************************************************************/
  32 #ifdef HAVE_CONFIG_H
  33 #include "config.h"
  34 #endif
  35
  36 #include "cortex_a8.h"
  37 #include "target_request.h"
  38
  39
  40 /* cli handling */
  41 int cortex_a8_register_commands(struct command_context_s *cmd_ctx);
  42
  43 /* forward declarations */
  44 int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp);
  45
  46 target_type_t cortexa8_target =
  47 {
  48         .name = "cortex_a8",
  49
  50         .poll = NULL,
  51         .arch_state = armv7m_arch_state,
  52
  53         .target_request_data = NULL,
  54
  55         .halt = NULL,
  56         .resume = NULL,
  57         .step = NULL,
  58
  59         .assert_reset = NULL,
  60         .deassert_reset = NULL,
  61         .soft_reset_halt = NULL,
  62
  63         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
  64
  65         .read_memory = cortex_a8_read_memory,
  66         .write_memory = cortex_a8_write_memory,
  67         .bulk_write_memory = NULL,
  68         .checksum_memory = NULL,
  69         .blank_check_memory = NULL,
  70
  71         .run_algorithm = armv7m_run_algorithm,
  72
  73         .add_breakpoint = NULL,
  74         .remove_breakpoint = NULL,
  75         .add_watchpoint = NULL,
  76         .remove_watchpoint = NULL,
  77
  78         .register_commands = cortex_a8_register_commands,
  79         .target_create = cortex_a8_target_create,
  80         .init_target = NULL,
  81         .examine = NULL,
  82         .quit = NULL
  83 };
  84
  85 int cortex_a8_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
  86 {
  87         u16 dcrdr;
  88
  89         mem_ap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
  90         *ctrl = (u8)dcrdr;
  91         *value = (u8)(dcrdr >> 8);
  92
  93         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
  94
  95         /* write ack back to software dcc register
  96          * signify we have read data */
  97         if (dcrdr & (1 << 0))
  98         {
  99                 dcrdr = 0;
 100                 mem_ap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
 101         }
 102
 103         return ERROR_OK;
 104 }
 105
 106 int cortex_a8_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 107 {
 108         /* get pointers to arch-specific information */
 109         armv7m_common_t *armv7m = target->arch_info;
 110         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 111         int retval;
 112
 113         /* sanitize arguments */
 114         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 115                 return ERROR_INVALID_ARGUMENTS;
 116
 117         /* cortex_a8 handles unaligned memory access */
 118
 119         switch (size)
 120         {
 121                 case 4:
 122                         retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
 123                         break;
 124                 case 2:
 125                         retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
 126                         break;
 127                 case 1:
 128                         retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
 129                         break;
 130                 default:
 131                         LOG_ERROR("BUG: we shouldn't get here");
 132                         exit(-1);
 133         }
 134
 135         return retval;
 136 }
 137
 138 int cortex_a8_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 139 {
 140         /* get pointers to arch-specific information */
 141         armv7m_common_t *armv7m = target->arch_info;
 142         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 143         int retval;
 144
 145         /* sanitize arguments */
 146         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 147                 return ERROR_INVALID_ARGUMENTS;
 148
 149         switch (size)
 150         {
 151                 case 4:
 152                         retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
 153                         break;
 154                 case 2:
 155                         retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
 156                         break;
 157                 case 1:
 158                         retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
 159                         break;
 160                 default:
 161                         LOG_ERROR("BUG: we shouldn't get here");
 162                         exit(-1);
 163         }
 164
 165         return retval;
 166 }
 167
 168 int cortex_a8_handle_target_request(void *priv)
 169 {
 170         target_t *target = priv;
 171         if (!target->type->examined)
 172                 return ERROR_OK;
 173         armv7m_common_t *armv7m = target->arch_info;
 174         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 175
 176         if (!target->dbg_msg_enabled)
 177                 return ERROR_OK;
 178
 179         if (target->state == TARGET_RUNNING)
 180         {
 181                 u8 data;
 182                 u8 ctrl;
 183
 184                 cortex_a8_dcc_read(swjdp, &data, &ctrl);
 185
 186                 /* check if we have data */
 187                 if (ctrl & (1 << 0))
 188                 {
 189                         u32 request;
 190
 191                         /* we assume target is quick enough */
 192                         request = data;
 193                         cortex_a8_dcc_read(swjdp, &data, &ctrl);
 194                         request |= (data << 8);
 195                         cortex_a8_dcc_read(swjdp, &data, &ctrl);
 196                         request |= (data << 16);
 197                         cortex_a8_dcc_read(swjdp, &data, &ctrl);
 198                         request |= (data << 24);
 199                         target_request(target, request);
 200                 }
 201         }
 202
 203         return ERROR_OK;
 204 }
 205
 206 int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap)
 207 {
 208         armv7m_common_t *armv7m;
 209         armv7m = &cortex_a8->armv7m;
 210
 211         /* prepare JTAG information for the new target */
 212         cortex_a8->jtag_info.tap = tap;
 213         cortex_a8->jtag_info.scann_size = 4;
 214
 215         armv7m->swjdp_info.dp_select_value = -1;
 216         armv7m->swjdp_info.ap_csw_value = -1;
 217         armv7m->swjdp_info.ap_tar_value = -1;
 218         armv7m->swjdp_info.jtag_info = &cortex_a8->jtag_info;
 219
 220         /* initialize arch-specific breakpoint handling */
 221
 222         cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
 223         cortex_a8->arch_info = NULL;
 224
 225         /* register arch-specific functions */
 226         armv7m->examine_debug_reason = NULL;
 227
 228         armv7m->pre_debug_entry = NULL;
 229         armv7m->post_debug_entry = NULL;
 230
 231         armv7m->pre_restore_context = NULL;
 232         armv7m->post_restore_context = NULL;
 233
 234         armv7m_init_arch_info(target, armv7m);
 235         armv7m->arch_info = cortex_a8;
 236         armv7m->load_core_reg_u32 = NULL;
 237         armv7m->store_core_reg_u32 = NULL;
 238
 239         target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
 240
 241         return ERROR_OK;
 242 }
 243
 244 int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp)
 245 {
 246         cortex_a8_common_t *cortex_a8 = calloc(1,sizeof(cortex_a8_common_t));
 247
 248         cortex_a8_init_arch_info(target, cortex_a8, target->tap);
 249
 250         return ERROR_OK;
 251 }
 252
 253 int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
 254 {
 255         int retval;
 256
 257         retval = armv7m_register_commands(cmd_ctx);
 258
 259         register_command(cmd_ctx, NULL, "cortex_a8", NULL, COMMAND_ANY, "cortex_a8 specific commands");
 260
 261         return retval;
 262 }