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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2009 by Dirk Behme                                      *
  12  *   dirk.behme@gmail.com - copy from cortex_m3                            *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  26  ***************************************************************************/
  27
  28 #ifndef OPENOCD_TARGET_CORTEX_A_H
  29 #define OPENOCD_TARGET_CORTEX_A_H
  30
  31 #include "armv7a.h"
  32
  33 #define CORTEX_A_COMMON_MAGIC 0x411fc082
  34 #define CORTEX_A15_COMMON_MAGIC 0x413fc0f1
  35
  36 #define CORTEX_A5_PARTNUM 0xc05
  37 #define CORTEX_A7_PARTNUM 0xc07
  38 #define CORTEX_A8_PARTNUM 0xc08
  39 #define CORTEX_A9_PARTNUM 0xc09
  40 #define CORTEX_A15_PARTNUM 0xc0f
  41 #define CORTEX_A_MIDR_PARTNUM_MASK 0x0000fff0
  42 #define CORTEX_A_MIDR_PARTNUM_SHIFT 4
  43
  44 #define CPUDBG_CPUID    0xD00
  45 #define CPUDBG_CTYPR    0xD04
  46 #define CPUDBG_TTYPR    0xD0C
  47 #define CPUDBG_LOCKACCESS 0xFB0
  48 #define CPUDBG_LOCKSTATUS 0xFB4
  49 #define CPUDBG_OSLAR_LK_MASK (1 << 1)
  50
  51 #define BRP_NORMAL 0
  52 #define BRP_CONTEXT 1
  53
  54 #define CORTEX_A_PADDRDBG_CPU_SHIFT 13
  55
  56 enum cortex_a_isrmasking_mode {
  57         CORTEX_A_ISRMASK_OFF,
  58         CORTEX_A_ISRMASK_ON,
  59 };
  60
  61 enum cortex_a_dacrfixup_mode {
  62         CORTEX_A_DACRFIXUP_OFF,
  63         CORTEX_A_DACRFIXUP_ON
  64 };
  65
  66 struct cortex_a_brp {
  67         bool used;
  68         int type;
  69         uint32_t value;
  70         uint32_t control;
  71         uint8_t BRPn;
  72 };
  73
  74 struct cortex_a_wrp {
  75         bool used;
  76         uint32_t value;
  77         uint32_t control;
  78         uint8_t WRPn;
  79 };
  80
  81 struct cortex_a_common {
  82         int common_magic;
  83
  84         /* Context information */
  85         uint32_t cpudbg_dscr;
  86
  87         /* Saved cp15 registers */
  88         uint32_t cp15_control_reg;
  89         /* latest cp15 register value written and cpsr processor mode */
  90         uint32_t cp15_control_reg_curr;
  91         /* auxiliary control reg */
  92         uint32_t cp15_aux_control_reg;
  93         /* DACR */
  94         uint32_t cp15_dacr_reg;
  95         enum arm_mode curr_mode;
  96
  97         /* Breakpoint register pairs */
  98         int brp_num_context;
  99         int brp_num;
 100         int brp_num_available;
 101         struct cortex_a_brp *brp_list;
 102         int wrp_num;
 103         int wrp_num_available;
 104         struct cortex_a_wrp *wrp_list;
 105
 106         uint32_t cpuid;
 107         uint32_t didr;
 108
 109         enum cortex_a_isrmasking_mode isrmasking_mode;
 110         enum cortex_a_dacrfixup_mode dacrfixup_mode;
 111
 112         struct armv7a_common armv7a_common;
 113
 114 };
 115
 116 static inline struct cortex_a_common *
 117 target_to_cortex_a(struct target *target)
 118 {
 119         return container_of(target->arch_info, struct cortex_a_common, armv7a_common.arm);
 120 }
 121
 122 #endif /* OPENOCD_TARGET_CORTEX_A_H */