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   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Oleksandr Tymoshenko <gonzo@bluezbox.com>       *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19 #ifndef AVR32_JTAG
  20 #define AVR32_JTAG
  21
  22 #define AVR32NUMCOREREGS        17
  23
  24 /* tap instructions */
  25 #define AVR32_INST_IDCODE               0x01
  26 #define AVR32_INST_NEXUS_ACCESS 0x10
  27 #define AVR32_INST_MW_ACCESS    0x11
  28 #define AVR32_INST_MB_ACCESS    0x12
  29
  30 #define SLAVE_OCD                               0x01
  31 #define SLAVE_HSB_CACHED                0x04
  32 #define SLAVE_HSB_UNCACHED              0x05
  33
  34 /*
  35  * Registers
  36  */
  37
  38 #define AVR32_OCDREG_DID                0x00
  39 #define AVR32_OCDREG_DC                 0x02
  40 #define         OCDREG_DC_SS                    (1 <<  8)
  41 #define         OCDREG_DC_DBR                   (1 << 12)
  42 #define         OCDREG_DC_DBE                   (1 << 13)
  43 #define         OCDREG_DC_SQA                   (1 << 22)
  44 #define         OCDREG_DC_RES                   (1 << 30)
  45 #define         OCDREG_DC_ABORT                 (1 << 31)
  46 #define AVR32_OCDREG_DS                 0x04
  47 #define         OCDREG_DS_SSS                   (1 <<  0)
  48 #define         OCDREG_DS_SWB                   (1 <<  1)
  49 #define         OCDREG_DS_HWB                   (1 <<  2)
  50 #define         OCDREG_DS_STP                   (1 <<  4)
  51 #define         OCDREG_DS_DBS                   (1 <<  5)
  52 #define         OCDREG_DS_BP_SHIFT              8
  53 #define         OCDREG_DS_BP_MASK               0xff
  54 #define         OCDREG_DS_INC                   (1 << 24)
  55 #define         OCDREG_DS_BOZ                   (1 << 25)
  56 #define         OCDREG_DS_DBA                   (1 << 26)
  57 #define         OCDREG_DS_EXB                   (1 << 27)
  58 #define         OCDREG_DS_NTBF                  (1 << 28)
  59
  60 #define AVR32_OCDREG_DINST              0x41
  61 #define AVR32_OCDREG_DPC                0x42
  62 #define AVR32_OCDREG_DCCPU              0x44
  63 #define AVR32_OCDREG_DCEMU              0x45
  64 #define AVR32_OCDREG_DCSR               0x46
  65 #define         OCDREG_DCSR_CPUD                (1 <<  0)
  66 #define         OCDREG_DCSR_EMUD                (1 <<  1)
  67
  68 /*
  69  * Direction bit
  70  */
  71 #define MODE_WRITE                              0x00
  72 #define MODE_READ                               0x01
  73
  74 /*
  75  * Some instructions
  76  */
  77
  78 #define RETD                                    0xd703d623
  79 #define MTDR(dreg, reg)                 (0xe7b00044 | ((reg) << 16) | dreg)
  80 #define MFDR(reg, dreg)                 (0xe5b00044 | ((reg) << 16) | dreg)
  81 #define MTSR(sysreg, reg)               (0xe3b00002 | ((reg) << 16) | sysreg)
  82 #define MFSR(reg, sysreg)               (0xe1b00002 | ((reg) << 16) | sysreg)
  83
  84 struct avr32_jtag
  85 {
  86         struct jtag_tap *tap;
  87         uint32_t dpc; /* Debug PC value */
  88 };
  89
  90 int avr32_jtag_nexus_read(struct avr32_jtag *jtag_info,
  91                 uint32_t addr, uint32_t *value);
  92 int avr32_jtag_nexus_write(struct avr32_jtag *jtag_info,
  93                 uint32_t addr, uint32_t value);
  94
  95 int avr32_jtag_mwa_read(struct avr32_jtag *jtag_info, int slave,
  96                 uint32_t addr, uint32_t *value);
  97 int avr32_jtag_mwa_write(struct avr32_jtag *jtag_info, int slave,
  98                 uint32_t addr, uint32_t value);
  99
 100
 101 int avr32_ocd_setbits(struct avr32_jtag *jtag, int reg, uint32_t bits);
 102 int avr32_ocd_clearbits(struct avr32_jtag *jtag, int reg, uint32_t bits);
 103
 104 int avr32_jtag_exec(struct avr32_jtag *jtag_info, uint32_t inst);
 105
 106 #endif /* AVR32_JTAG */
 107