aarch64: fix mode switching
[fw/openocd] / src / target / armv8_opcodes.c
1 /*
2  * Copyright (C) 2015 by Matthias Welwarsky <matthias.welwarsky@sysgo.com>
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  */
15
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19
20 #include <stdint.h>
21 #include <stdbool.h>
22
23 #include "armv8.h"
24 #include "armv8_opcodes.h"
25
26 static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
27                 [READ_REG_CLIDR]        = ARMV8_MRS(SYSTEM_CLIDR, 0),
28                 [READ_REG_CSSELR]       = ARMV8_MRS(SYSTEM_CSSELR, 0),
29                 [READ_REG_CCSIDR]       = ARMV8_MRS(SYSTEM_CCSIDR, 0),
30                 [WRITE_REG_CSSELR]      = ARMV8_MSR_GP(SYSTEM_CSSELR, 0),
31                 [READ_REG_MPIDR]        = ARMV8_MRS(SYSTEM_MPIDR, 0),
32                 [READ_REG_DTRRX]        = ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 0),
33                 [WRITE_REG_DTRTX]       = ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 0),
34                 [WRITE_REG_DSPSR]       = ARMV8_MSR_DSPSR(0),
35                 [READ_REG_DSPSR]        = ARMV8_MRS_DSPSR(0),
36                 [ARMV8_OPC_DSB_SY]      = ARMV8_DSB_SY,
37                 [ARMV8_OPC_DCPS]        = ARMV8_DCPS(0, 11),
38                 [ARMV8_OPC_DRPS]        = ARMV8_DRPS,
39 };
40
41 static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
42                 [READ_REG_CLIDR]        = ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
43                 [READ_REG_CSSELR]       = ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
44                 [READ_REG_CCSIDR]       = ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
45                 [WRITE_REG_CSSELR]      = ARMV4_5_MCR(15, 2, 0, 0, 0, 0),
46                 [READ_REG_MPIDR]        = ARMV4_5_MRC(15, 0, 0, 0, 0, 5),
47                 [READ_REG_DTRRX]        = ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
48                 [WRITE_REG_DTRTX]       = ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
49                 [WRITE_REG_DSPSR]       = ARMV8_MCR_DSPSR(0),
50                 [READ_REG_DSPSR]        = ARMV8_MRC_DSPSR(0),
51                 [ARMV8_OPC_DSB_SY]      = ARMV8_DSB_SY_T1,
52                 [ARMV8_OPC_DCPS]        = ARMV8_DCPS_T1(0),
53                 [ARMV8_OPC_DRPS]        = ARMV8_ERET_T1,
54 };
55
56 void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)
57 {
58         if (state_is_aarch64)
59                 armv8->opcodes = &a64_opcodes[0];
60         else
61                 armv8->opcodes = &t32_opcodes[0];
62 }
63
64 uint32_t armv8_opcode(struct armv8_common *armv8, enum armv8_opcode code)
65 {
66         if ((int)code >= ARMV8_OPC_NUM)
67                 return -1;
68
69         return *(armv8->opcodes + code);
70 }