1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2015 Paul Fertser <fercerpav@gmail.com> *
5 ***************************************************************************/
11 #include <target/target.h>
12 #include <target/armv7m.h>
13 #include <target/cortex_m.h>
14 #include <target/armv7m_trace.h>
15 #include <jtag/interface.h>
16 #include <helper/time_support.h>
18 int armv7m_trace_itm_config(struct target *target)
20 struct armv7m_common *armv7m = target_to_armv7m(target);
21 struct armv7m_trace_config *trace_config = &armv7m->trace_config;
24 retval = target_write_u32(target, ITM_LAR, ITM_LAR_KEY);
25 if (retval != ERROR_OK)
28 /* pg315 of CoreSight Components
29 * It is recommended that the ITMEn bit is cleared and waits for the
30 * ITMBusy bit to be cleared, before changing any fields in the
31 * Control Register, otherwise the behavior can be unpredictable.
34 retval = target_read_u32(target, ITM_TCR, &itm_tcr);
35 if (retval != ERROR_OK)
37 retval = target_write_u32(target,
39 itm_tcr & ~ITM_TCR_ITMENA_BIT
41 if (retval != ERROR_OK)
44 int64_t then = timeval_ms() + 1000;
46 retval = target_read_u32(target, ITM_TCR, &itm_tcr);
47 if (retval != ERROR_OK)
49 if (timeval_ms() > then) {
50 LOG_ERROR("timeout waiting for ITM_TCR_BUSY_BIT");
53 } while (itm_tcr & ITM_TCR_BUSY_BIT);
55 /* Enable ITM, TXENA, set TraceBusID and other parameters */
56 retval = target_write_u32(target, ITM_TCR, (1 << 0) | (1 << 3) |
57 (trace_config->itm_diff_timestamps << 1) |
58 (trace_config->itm_synchro_packets << 2) |
59 (trace_config->itm_async_timestamps << 4) |
60 (trace_config->itm_ts_prescale << 8) |
61 (trace_config->trace_bus_id << 16));
62 if (retval != ERROR_OK)
65 for (unsigned int i = 0; i < 8; i++) {
66 retval = target_write_u32(target, ITM_TER0 + i * 4,
67 trace_config->itm_ter[i]);
68 if (retval != ERROR_OK)
75 COMMAND_HANDLER(handle_itm_port_command)
77 struct target *target = get_current_target(CMD_CTX);
78 struct armv7m_common *armv7m = target_to_armv7m(target);
84 return ERROR_COMMAND_SYNTAX_ERROR;
86 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], port);
87 COMMAND_PARSE_ON_OFF(CMD_ARGV[1], enable);
91 armv7m->trace_config.itm_ter[reg_idx] |= (1 << port);
93 armv7m->trace_config.itm_ter[reg_idx] &= ~(1 << port);
95 if (CMD_CTX->mode == COMMAND_EXEC)
96 return armv7m_trace_itm_config(target);
98 armv7m->trace_config.itm_deferred_config = true;
102 COMMAND_HANDLER(handle_itm_ports_command)
104 struct target *target = get_current_target(CMD_CTX);
105 struct armv7m_common *armv7m = target_to_armv7m(target);
109 return ERROR_COMMAND_SYNTAX_ERROR;
111 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
112 memset(armv7m->trace_config.itm_ter, enable ? 0xff : 0,
113 sizeof(armv7m->trace_config.itm_ter));
115 if (CMD_CTX->mode == COMMAND_EXEC)
116 return armv7m_trace_itm_config(target);
118 armv7m->trace_config.itm_deferred_config = true;
122 static const struct command_registration itm_command_handlers[] = {
125 .handler = handle_itm_port_command,
127 .help = "Enable or disable ITM stimulus port",
128 .usage = "<port> (0|1|on|off)",
132 .handler = handle_itm_ports_command,
134 .help = "Enable or disable all ITM stimulus ports",
135 .usage = "(0|1|on|off)",
137 COMMAND_REGISTRATION_DONE
140 const struct command_registration armv7m_trace_command_handlers[] = {
144 .help = "itm command group",
146 .chain = itm_command_handlers,
148 COMMAND_REGISTRATION_DONE