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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 #ifndef ARMV7M_COMMON_H
  28 #define ARMV7M_COMMON_H
  29
  30 #include "arm_adi_v5.h"
  31 #include "arm.h"
  32
  33 /* define for enabling armv7 gdb workarounds */
  34 #if 1
  35 #define ARMV7_GDB_HACKS
  36 #endif
  37
  38 #ifdef ARMV7_GDB_HACKS
  39 extern uint8_t armv7m_gdb_dummy_cpsr_value[];
  40 extern struct reg armv7m_gdb_dummy_cpsr_reg;
  41 #endif
  42
  43 extern const int armv7m_psp_reg_map[];
  44 extern const int armv7m_msp_reg_map[];
  45
  46 enum armv7m_regtype {
  47         ARMV7M_REGISTER_CORE_GP,
  48         ARMV7M_REGISTER_CORE_SP,
  49         ARMV7M_REGISTER_MEMMAP
  50 };
  51
  52 char *armv7m_exception_string(int number);
  53
  54 /* offsets into armv7m core register cache */
  55 enum {
  56         /* for convenience, the first set of indices match
  57          * the Cortex-M3/-M4 DCRSR selectors
  58          */
  59         ARMV7M_R0,
  60         ARMV7M_R1,
  61         ARMV7M_R2,
  62         ARMV7M_R3,
  63
  64         ARMV7M_R4,
  65         ARMV7M_R5,
  66         ARMV7M_R6,
  67         ARMV7M_R7,
  68
  69         ARMV7M_R8,
  70         ARMV7M_R9,
  71         ARMV7M_R10,
  72         ARMV7M_R11,
  73
  74         ARMV7M_R12,
  75         ARMV7M_R13,
  76         ARMV7M_R14,
  77         ARMV7M_PC = 15,
  78
  79         ARMV7M_xPSR = 16,
  80         ARMV7M_MSP,
  81         ARMV7M_PSP,
  82
  83         /* this next set of indices is arbitrary */
  84         ARMV7M_PRIMASK,
  85         ARMV7M_BASEPRI,
  86         ARMV7M_FAULTMASK,
  87         ARMV7M_CONTROL,
  88
  89         /* 32bit Floating-point registers */
  90         ARMV7M_S0,
  91         ARMV7M_S1,
  92         ARMV7M_S2,
  93         ARMV7M_S3,
  94         ARMV7M_S4,
  95         ARMV7M_S5,
  96         ARMV7M_S6,
  97         ARMV7M_S7,
  98         ARMV7M_S8,
  99         ARMV7M_S9,
 100         ARMV7M_S10,
 101         ARMV7M_S11,
 102         ARMV7M_S12,
 103         ARMV7M_S13,
 104         ARMV7M_S14,
 105         ARMV7M_S15,
 106         ARMV7M_S16,
 107         ARMV7M_S17,
 108         ARMV7M_S18,
 109         ARMV7M_S19,
 110         ARMV7M_S20,
 111         ARMV7M_S21,
 112         ARMV7M_S22,
 113         ARMV7M_S23,
 114         ARMV7M_S24,
 115         ARMV7M_S25,
 116         ARMV7M_S26,
 117         ARMV7M_S27,
 118         ARMV7M_S28,
 119         ARMV7M_S29,
 120         ARMV7M_S30,
 121         ARMV7M_S31,
 122
 123         /* 64bit Floating-point registers */
 124         ARMV7M_D0,
 125         ARMV7M_D1,
 126         ARMV7M_D2,
 127         ARMV7M_D3,
 128         ARMV7M_D4,
 129         ARMV7M_D5,
 130         ARMV7M_D6,
 131         ARMV7M_D7,
 132         ARMV7M_D8,
 133         ARMV7M_D9,
 134         ARMV7M_D10,
 135         ARMV7M_D11,
 136         ARMV7M_D12,
 137         ARMV7M_D13,
 138         ARMV7M_D14,
 139         ARMV7M_D15,
 140
 141         /* Floating-point status registers */
 142         ARMV7M_FPSID,
 143         ARMV7M_FPSCR,
 144         ARMV7M_FPEXC,
 145
 146         ARMV7M_LAST_REG,
 147 };
 148
 149 enum {
 150         FP_NONE = 0,
 151         FPv4_SP,
 152 };
 153
 154 #define ARMV7M_COMMON_MAGIC 0x2A452A45
 155
 156 struct armv7m_common {
 157         struct arm      arm;
 158
 159         int common_magic;
 160         struct reg_cache *core_cache;
 161         int exception_number;
 162         struct adiv5_dap dap;
 163
 164         int fp_feature;
 165         uint32_t demcr;
 166
 167         /* stlink is a high level adapter, does not support all functions */
 168         bool stlink;
 169
 170         /* Direct processor core register read and writes */
 171         int (*load_core_reg_u32)(struct target *target,
 172                 enum armv7m_regtype type, uint32_t num, uint32_t *value);
 173         int (*store_core_reg_u32)(struct target *target,
 174                 enum armv7m_regtype type, uint32_t num, uint32_t value);
 175
 176         /* register cache to processor synchronization */
 177         int (*read_core_reg)(struct target *target, unsigned num);
 178         int (*write_core_reg)(struct target *target, unsigned num);
 179
 180         int (*examine_debug_reason)(struct target *target);
 181         int (*post_debug_entry)(struct target *target);
 182
 183         void (*pre_restore_context)(struct target *target);
 184 };
 185
 186 static inline struct armv7m_common *
 187 target_to_armv7m(struct target *target)
 188 {
 189         return container_of(target->arch_info, struct armv7m_common, arm);
 190 }
 191
 192 static inline bool is_armv7m(struct armv7m_common *armv7m)
 193 {
 194         return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
 195 }
 196
 197 struct armv7m_algorithm {
 198         int common_magic;
 199
 200         enum arm_mode core_mode;
 201
 202         uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */
 203 };
 204
 205 struct armv7m_core_reg {
 206         uint32_t num;
 207         enum armv7m_regtype type;
 208         struct target *target;
 209         struct armv7m_common *armv7m_common;
 210 };
 211
 212 struct reg_cache *armv7m_build_reg_cache(struct target *target);
 213 enum armv7m_mode armv7m_number_to_mode(int number);
 214 int armv7m_mode_to_number(enum armv7m_mode mode);
 215
 216 int armv7m_arch_state(struct target *target);
 217 int armv7m_get_gdb_reg_list(struct target *target,
 218                 struct reg **reg_list[], int *reg_list_size);
 219
 220 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
 221
 222 int armv7m_run_algorithm(struct target *target,
 223                 int num_mem_params, struct mem_param *mem_params,
 224                 int num_reg_params, struct reg_param *reg_params,
 225                 uint32_t entry_point, uint32_t exit_point,
 226                 int timeout_ms, void *arch_info);
 227
 228 int armv7m_start_algorithm(struct target *target,
 229                 int num_mem_params, struct mem_param *mem_params,
 230                 int num_reg_params, struct reg_param *reg_params,
 231                 uint32_t entry_point, uint32_t exit_point,
 232                 void *arch_info);
 233
 234 int armv7m_wait_algorithm(struct target *target,
 235                 int num_mem_params, struct mem_param *mem_params,
 236                 int num_reg_params, struct reg_param *reg_params,
 237                 uint32_t exit_point, int timeout_ms,
 238                 void *arch_info);
 239
 240 int armv7m_invalidate_core_regs(struct target *target);
 241
 242 int armv7m_restore_context(struct target *target);
 243
 244 int armv7m_checksum_memory(struct target *target,
 245                 uint32_t address, uint32_t count, uint32_t *checksum);
 246 int armv7m_blank_check_memory(struct target *target,
 247                 uint32_t address, uint32_t count, uint32_t *blank);
 248
 249 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
 250
 251 extern const struct command_registration armv7m_command_handlers[];
 252
 253 #endif /* ARMV7M_H */