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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 #ifndef ARMV7M_COMMON_H
  28 #define ARMV7M_COMMON_H
  29
  30 #include "arm_adi_v5.h"
  31 #include "arm.h"
  32
  33 /* define for enabling armv7 gdb workarounds */
  34 #if 1
  35 #define ARMV7_GDB_HACKS
  36 #endif
  37
  38 #ifdef ARMV7_GDB_HACKS
  39 extern uint8_t armv7m_gdb_dummy_cpsr_value[];
  40 extern struct reg armv7m_gdb_dummy_cpsr_reg;
  41 #endif
  42
  43 enum armv7m_mode {
  44         ARMV7M_MODE_THREAD = 0,
  45         ARMV7M_MODE_USER_THREAD = 1,
  46         ARMV7M_MODE_HANDLER = 2,
  47         ARMV7M_MODE_ANY = -1
  48 };
  49
  50 extern char *armv7m_mode_strings[];
  51 extern const int armv7m_psp_reg_map[];
  52 extern const int armv7m_msp_reg_map[];
  53
  54 enum armv7m_regtype {
  55         ARMV7M_REGISTER_CORE_GP,
  56         ARMV7M_REGISTER_CORE_SP,
  57         ARMV7M_REGISTER_MEMMAP
  58 };
  59
  60 char *armv7m_exception_string(int number);
  61
  62 /* offsets into armv7m core register cache */
  63 enum {
  64         /* for convenience, the first set of indices match
  65          * the Cortex-M3 DCRSR selectors
  66          */
  67         ARMV7M_R0,
  68         ARMV7M_R1,
  69         ARMV7M_R2,
  70         ARMV7M_R3,
  71
  72         ARMV7M_R4,
  73         ARMV7M_R5,
  74         ARMV7M_R6,
  75         ARMV7M_R7,
  76
  77         ARMV7M_R8,
  78         ARMV7M_R9,
  79         ARMV7M_R10,
  80         ARMV7M_R11,
  81
  82         ARMV7M_R12,
  83         ARMV7M_R13,
  84         ARMV7M_R14,
  85         ARMV7M_PC = 15,
  86
  87         ARMV7M_xPSR = 16,
  88         ARMV7M_MSP,
  89         ARMV7M_PSP,
  90
  91         /* this next set of indices is arbitrary */
  92         ARMV7M_PRIMASK,
  93         ARMV7M_BASEPRI,
  94         ARMV7M_FAULTMASK,
  95         ARMV7M_CONTROL,
  96
  97         ARMV7M_LAST_REG,
  98 };
  99
 100 #define ARMV7M_COMMON_MAGIC 0x2A452A45
 101
 102 struct armv7m_common {
 103         struct arm      arm;
 104
 105         int common_magic;
 106         struct reg_cache *core_cache;
 107         enum armv7m_mode core_mode;
 108         int exception_number;
 109         struct adiv5_dap dap;
 110
 111         uint32_t demcr;
 112
 113         /* Direct processor core register read and writes */
 114         int (*load_core_reg_u32)(struct target *target,
 115                 enum armv7m_regtype type, uint32_t num, uint32_t *value);
 116         int (*store_core_reg_u32)(struct target *target,
 117                 enum armv7m_regtype type, uint32_t num, uint32_t value);
 118
 119         /* register cache to processor synchronization */
 120         int (*read_core_reg)(struct target *target, unsigned num);
 121         int (*write_core_reg)(struct target *target, unsigned num);
 122
 123         int (*examine_debug_reason)(struct target *target);
 124         int (*post_debug_entry)(struct target *target);
 125
 126         void (*pre_restore_context)(struct target *target);
 127 };
 128
 129 static inline struct armv7m_common *
 130 target_to_armv7m(struct target *target)
 131 {
 132         return container_of(target->arch_info, struct armv7m_common, arm);
 133 }
 134
 135 static inline bool is_armv7m(struct armv7m_common *armv7m)
 136 {
 137         return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
 138 }
 139
 140 struct armv7m_algorithm {
 141         int common_magic;
 142
 143         enum armv7m_mode core_mode;
 144
 145         uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */
 146 };
 147
 148 struct armv7m_core_reg {
 149         uint32_t num;
 150         enum armv7m_regtype type;
 151         struct target *target;
 152         struct armv7m_common *armv7m_common;
 153 };
 154
 155 struct reg_cache *armv7m_build_reg_cache(struct target *target);
 156 enum armv7m_mode armv7m_number_to_mode(int number);
 157 int armv7m_mode_to_number(enum armv7m_mode mode);
 158
 159 int armv7m_arch_state(struct target *target);
 160 int armv7m_get_gdb_reg_list(struct target *target,
 161                 struct reg **reg_list[], int *reg_list_size);
 162
 163 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
 164
 165 int armv7m_run_algorithm(struct target *target,
 166                 int num_mem_params, struct mem_param *mem_params,
 167                 int num_reg_params, struct reg_param *reg_params,
 168                 uint32_t entry_point, uint32_t exit_point,
 169                 int timeout_ms, void *arch_info);
 170
 171 int armv7m_start_algorithm(struct target *target,
 172                 int num_mem_params, struct mem_param *mem_params,
 173                 int num_reg_params, struct reg_param *reg_params,
 174                 uint32_t entry_point, uint32_t exit_point,
 175                 void *arch_info);
 176
 177 int armv7m_wait_algorithm(struct target *target,
 178                 int num_mem_params, struct mem_param *mem_params,
 179                 int num_reg_params, struct reg_param *reg_params,
 180                 uint32_t exit_point, int timeout_ms,
 181                 void *arch_info);
 182
 183 int armv7m_invalidate_core_regs(struct target *target);
 184
 185 int armv7m_restore_context(struct target *target);
 186
 187 int armv7m_checksum_memory(struct target *target,
 188                 uint32_t address, uint32_t count, uint32_t *checksum);
 189 int armv7m_blank_check_memory(struct target *target,
 190                 uint32_t address, uint32_t count, uint32_t *blank);
 191
 192 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
 193
 194 extern const struct command_registration armv7m_command_handlers[];
 195
 196 #endif /* ARMV7M_H */