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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifndef OPENOCD_TARGET_ARMV7M_H
  26 #define OPENOCD_TARGET_ARMV7M_H
  27
  28 #include "arm.h"
  29 #include "armv7m_trace.h"
  30
  31 struct adiv5_ap;
  32
  33 extern const int armv7m_psp_reg_map[];
  34 extern const int armv7m_msp_reg_map[];
  35
  36 const char *armv7m_exception_string(int number);
  37
  38 /* Cortex-M DCRSR.REGSEL selectors */
  39 enum {
  40         ARMV7M_REGSEL_R0,
  41         ARMV7M_REGSEL_R1,
  42         ARMV7M_REGSEL_R2,
  43         ARMV7M_REGSEL_R3,
  44
  45         ARMV7M_REGSEL_R4,
  46         ARMV7M_REGSEL_R5,
  47         ARMV7M_REGSEL_R6,
  48         ARMV7M_REGSEL_R7,
  49
  50         ARMV7M_REGSEL_R8,
  51         ARMV7M_REGSEL_R9,
  52         ARMV7M_REGSEL_R10,
  53         ARMV7M_REGSEL_R11,
  54
  55         ARMV7M_REGSEL_R12,
  56         ARMV7M_REGSEL_R13,
  57         ARMV7M_REGSEL_R14,
  58         ARMV7M_REGSEL_PC = 15,
  59
  60         ARMV7M_REGSEL_xPSR = 16,
  61         ARMV7M_REGSEL_MSP,
  62         ARMV7M_REGSEL_PSP,
  63
  64         ARMV8M_REGSEL_MSP_NS = 0x18,
  65         ARMV8M_REGSEL_PSP_NS,
  66         ARMV8M_REGSEL_MSP_S,
  67         ARMV8M_REGSEL_PSP_S,
  68         ARMV8M_REGSEL_MSPLIM_S,
  69         ARMV8M_REGSEL_PSPLIM_S,
  70         ARMV8M_REGSEL_MSPLIM_NS,
  71         ARMV8M_REGSEL_PSPLIM_NS,
  72
  73         ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14,
  74         ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S = 0x22,
  75         ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS = 0x23,
  76         ARMV7M_REGSEL_FPSCR = 0x21,
  77
  78         /* 32bit Floating-point registers */
  79         ARMV7M_REGSEL_S0 = 0x40,
  80         ARMV7M_REGSEL_S1,
  81         ARMV7M_REGSEL_S2,
  82         ARMV7M_REGSEL_S3,
  83         ARMV7M_REGSEL_S4,
  84         ARMV7M_REGSEL_S5,
  85         ARMV7M_REGSEL_S6,
  86         ARMV7M_REGSEL_S7,
  87         ARMV7M_REGSEL_S8,
  88         ARMV7M_REGSEL_S9,
  89         ARMV7M_REGSEL_S10,
  90         ARMV7M_REGSEL_S11,
  91         ARMV7M_REGSEL_S12,
  92         ARMV7M_REGSEL_S13,
  93         ARMV7M_REGSEL_S14,
  94         ARMV7M_REGSEL_S15,
  95         ARMV7M_REGSEL_S16,
  96         ARMV7M_REGSEL_S17,
  97         ARMV7M_REGSEL_S18,
  98         ARMV7M_REGSEL_S19,
  99         ARMV7M_REGSEL_S20,
 100         ARMV7M_REGSEL_S21,
 101         ARMV7M_REGSEL_S22,
 102         ARMV7M_REGSEL_S23,
 103         ARMV7M_REGSEL_S24,
 104         ARMV7M_REGSEL_S25,
 105         ARMV7M_REGSEL_S26,
 106         ARMV7M_REGSEL_S27,
 107         ARMV7M_REGSEL_S28,
 108         ARMV7M_REGSEL_S29,
 109         ARMV7M_REGSEL_S30,
 110         ARMV7M_REGSEL_S31,
 111 };
 112
 113 /* offsets into armv7m core register cache */
 114 enum {
 115         /* for convenience, the first set of indices match
 116          * the Cortex-M DCRSR.REGSEL selectors
 117          */
 118         ARMV7M_R0 = ARMV7M_REGSEL_R0,
 119         ARMV7M_R1 = ARMV7M_REGSEL_R1,
 120         ARMV7M_R2 = ARMV7M_REGSEL_R2,
 121         ARMV7M_R3 = ARMV7M_REGSEL_R3,
 122
 123         ARMV7M_R4 = ARMV7M_REGSEL_R4,
 124         ARMV7M_R5 = ARMV7M_REGSEL_R5,
 125         ARMV7M_R6 = ARMV7M_REGSEL_R6,
 126         ARMV7M_R7 = ARMV7M_REGSEL_R7,
 127
 128         ARMV7M_R8 = ARMV7M_REGSEL_R8,
 129         ARMV7M_R9 = ARMV7M_REGSEL_R9,
 130         ARMV7M_R10 = ARMV7M_REGSEL_R10,
 131         ARMV7M_R11 = ARMV7M_REGSEL_R11,
 132
 133         ARMV7M_R12 = ARMV7M_REGSEL_R12,
 134         ARMV7M_R13 = ARMV7M_REGSEL_R13,
 135         ARMV7M_R14 = ARMV7M_REGSEL_R14,
 136         ARMV7M_PC = ARMV7M_REGSEL_PC,
 137
 138         ARMV7M_xPSR = ARMV7M_REGSEL_xPSR,
 139         ARMV7M_MSP = ARMV7M_REGSEL_MSP,
 140         ARMV7M_PSP = ARMV7M_REGSEL_PSP,
 141
 142         /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
 143
 144         /* A block of container and contained registers follows:
 145          * THE ORDER IS IMPORTANT to the end of the block ! */
 146         /* working register for packing/unpacking special regs, hidden from gdb */
 147         ARMV7M_PMSK_BPRI_FLTMSK_CTRL,
 148
 149         /* WARNING: If you use armv7m_write_core_reg() on one of 4 following
 150          * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
 151          * cache only and are not flushed to CPU HW register.
 152          * To trigger write to CPU HW register, add
 153          *              armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
 154          */
 155         ARMV7M_PRIMASK,
 156         ARMV7M_BASEPRI,
 157         ARMV7M_FAULTMASK,
 158         ARMV7M_CONTROL,
 159         /* The end of block of container and contained registers */
 160
 161         /* ARMv8-M specific registers */
 162         ARMV8M_MSP_NS,
 163         ARMV8M_PSP_NS,
 164         ARMV8M_MSP_S,
 165         ARMV8M_PSP_S,
 166         ARMV8M_MSPLIM_S,
 167         ARMV8M_PSPLIM_S,
 168         ARMV8M_MSPLIM_NS,
 169         ARMV8M_PSPLIM_NS,
 170
 171         /* A block of container and contained registers follows:
 172          * THE ORDER IS IMPORTANT to the end of the block ! */
 173         ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S,
 174         ARMV8M_PRIMASK_S,
 175         ARMV8M_BASEPRI_S,
 176         ARMV8M_FAULTMASK_S,
 177         ARMV8M_CONTROL_S,
 178         /* The end of block of container and contained registers */
 179
 180         /* A block of container and contained registers follows:
 181          * THE ORDER IS IMPORTANT to the end of the block ! */
 182         ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS,
 183         ARMV8M_PRIMASK_NS,
 184         ARMV8M_BASEPRI_NS,
 185         ARMV8M_FAULTMASK_NS,
 186         ARMV8M_CONTROL_NS,
 187         /* The end of block of container and contained registers */
 188
 189         /* 64bit Floating-point registers */
 190         ARMV7M_D0,
 191         ARMV7M_D1,
 192         ARMV7M_D2,
 193         ARMV7M_D3,
 194         ARMV7M_D4,
 195         ARMV7M_D5,
 196         ARMV7M_D6,
 197         ARMV7M_D7,
 198         ARMV7M_D8,
 199         ARMV7M_D9,
 200         ARMV7M_D10,
 201         ARMV7M_D11,
 202         ARMV7M_D12,
 203         ARMV7M_D13,
 204         ARMV7M_D14,
 205         ARMV7M_D15,
 206
 207         /* Floating-point status register */
 208         ARMV7M_FPSCR,
 209
 210         /* for convenience add registers' block delimiters */
 211         ARMV7M_LAST_REG,
 212         ARMV7M_CORE_FIRST_REG = ARMV7M_R0,
 213         ARMV7M_CORE_LAST_REG = ARMV7M_xPSR,
 214         ARMV7M_FPU_FIRST_REG = ARMV7M_D0,
 215         ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR,
 216         ARMV8M_FIRST_REG = ARMV8M_MSP_NS,
 217         ARMV8M_LAST_REG = ARMV8M_CONTROL_NS,
 218 };
 219
 220 enum {
 221         FP_NONE = 0,
 222         FPV4_SP,
 223         FPV5_SP,
 224         FPV5_DP,
 225 };
 226
 227 #define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
 228
 229 #define ARMV7M_COMMON_MAGIC 0x2A452A45
 230
 231 struct armv7m_common {
 232         struct arm arm;
 233
 234         int common_magic;
 235         int exception_number;
 236
 237         /* AP this processor is connected to in the DAP */
 238         struct adiv5_ap *debug_ap;
 239
 240         int fp_feature;
 241         uint32_t demcr;
 242
 243         /* hla_target uses a high level adapter that does not support all functions */
 244         bool is_hla_target;
 245
 246         struct armv7m_trace_config trace_config;
 247
 248         /* Direct processor core register read and writes */
 249         int (*load_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t *value);
 250         int (*store_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t value);
 251
 252         int (*examine_debug_reason)(struct target *target);
 253         int (*post_debug_entry)(struct target *target);
 254
 255         void (*pre_restore_context)(struct target *target);
 256 };
 257
 258 static inline struct armv7m_common *
 259 target_to_armv7m(struct target *target)
 260 {
 261         return container_of(target->arch_info, struct armv7m_common, arm);
 262 }
 263
 264 static inline bool is_armv7m(const struct armv7m_common *armv7m)
 265 {
 266         return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
 267 }
 268
 269 struct armv7m_algorithm {
 270         int common_magic;
 271
 272         enum arm_mode core_mode;
 273
 274         uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */
 275 };
 276
 277 struct reg_cache *armv7m_build_reg_cache(struct target *target);
 278 void armv7m_free_reg_cache(struct target *target);
 279
 280 enum armv7m_mode armv7m_number_to_mode(int number);
 281 int armv7m_mode_to_number(enum armv7m_mode mode);
 282
 283 int armv7m_arch_state(struct target *target);
 284 int armv7m_get_gdb_reg_list(struct target *target,
 285                 struct reg **reg_list[], int *reg_list_size,
 286                 enum target_register_class reg_class);
 287
 288 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
 289
 290 int armv7m_run_algorithm(struct target *target,
 291                 int num_mem_params, struct mem_param *mem_params,
 292                 int num_reg_params, struct reg_param *reg_params,
 293                 target_addr_t entry_point, target_addr_t exit_point,
 294                 int timeout_ms, void *arch_info);
 295
 296 int armv7m_start_algorithm(struct target *target,
 297                 int num_mem_params, struct mem_param *mem_params,
 298                 int num_reg_params, struct reg_param *reg_params,
 299                 target_addr_t entry_point, target_addr_t exit_point,
 300                 void *arch_info);
 301
 302 int armv7m_wait_algorithm(struct target *target,
 303                 int num_mem_params, struct mem_param *mem_params,
 304                 int num_reg_params, struct reg_param *reg_params,
 305                 target_addr_t exit_point, int timeout_ms,
 306                 void *arch_info);
 307
 308 int armv7m_invalidate_core_regs(struct target *target);
 309
 310 int armv7m_restore_context(struct target *target);
 311
 312 int armv7m_checksum_memory(struct target *target,
 313                 target_addr_t address, uint32_t count, uint32_t *checksum);
 314 int armv7m_blank_check_memory(struct target *target,
 315                 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
 316
 317 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
 318
 319 extern const struct command_registration armv7m_command_handlers[];
 320
 321 #endif /* OPENOCD_TARGET_ARMV7M_H */