1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef ARMV7M_COMMON_H
27 #define ARMV7M_COMMON_H
29 #include "arm_adi_v5.h"
31 /* define for enabling armv7 gdb workarounds */
33 #define ARMV7_GDB_HACKS
38 ARMV7M_MODE_THREAD = 0,
39 ARMV7M_MODE_USER_THREAD = 1,
40 ARMV7M_MODE_HANDLER = 2,
44 extern char* armv7m_mode_strings[];
48 ARMV7M_REGISTER_CORE_GP,
49 ARMV7M_REGISTER_CORE_SP,
50 ARMV7M_REGISTER_MEMMAP
53 extern char* armv7m_exception_strings[];
55 extern char *armv7m_exception_string(int number);
57 /* offsets into armv7m core register cache */
65 /* FIXME the register numbers here are core-specific. Cortex-M3
66 * through r1p1 only defines registers up to PSP; see ARM DDI 0337E.
68 * It's r2p0 (see ARM DDI 0337G) which defines the register that's
69 * called SPEC20 here, with four single-byte fields with CONTROL
70 * (highest byte), FAULTMASK, BASEPRI, and PRIMASK (lowest byte).
76 #define ARMV7M_COMMON_MAGIC 0x2A452A45
78 typedef struct armv7m_common_s
81 reg_cache_t *core_cache;
82 enum armv7m_mode core_mode;
84 swjdp_common_t swjdp_info;
88 /* Direct processor core register read and writes */
89 int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
90 int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
91 /* register cache to processor synchronization */
92 int (*read_core_reg)(struct target_s *target, int num);
93 int (*write_core_reg)(struct target_s *target, int num);
95 int (*examine_debug_reason)(target_t *target);
96 void (*pre_debug_entry)(target_t *target);
97 void (*post_debug_entry)(target_t *target);
99 void (*pre_restore_context)(target_t *target);
100 void (*post_restore_context)(target_t *target);
105 typedef struct armv7m_algorithm_s
109 enum armv7m_mode core_mode;
110 } armv7m_algorithm_t;
112 typedef struct armv7m_core_reg_s
115 enum armv7m_regtype type;
116 enum armv7m_mode mode;
118 armv7m_common_t *armv7m_common;
121 extern reg_cache_t *armv7m_build_reg_cache(target_t *target);
122 extern enum armv7m_mode armv7m_number_to_mode(int number);
123 extern int armv7m_mode_to_number(enum armv7m_mode mode);
125 extern int armv7m_arch_state(struct target_s *target);
126 extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
128 extern int armv7m_register_commands(struct command_context_s *cmd_ctx);
129 extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
131 extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
133 extern int armv7m_invalidate_core_regs(target_t *target);
135 extern int armv7m_restore_context(target_t *target);
137 extern int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
138 extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank);
140 /* Thumb mode instructions
143 /* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
144 * Rd: destination register
145 * SYSm: source special register
147 #define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
149 /* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
150 * Rd: source register
151 * SYSm: destination special register
153 #define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
155 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
156 * special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
157 * Rd: source register
162 #define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
163 #define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
165 /* Breakpoint (Thumb mode) v5 onwards
166 * Im: immediate value used by debugger
168 #define ARMV7M_T_BKPT(Im) ((0xBE00 | Im) | ((0xBE00 | Im) << 16))
170 /* Store register (Thumb mode)
171 * Rd: source register
174 #define ARMV7M_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
176 /* Load register (Thumb state)
177 * Rd: destination register
180 #define ARMV7M_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
182 /* Load multiple (Thumb state)
184 * List: for each bit in list: store register
186 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
188 /* Load register with PC relative addressing
189 * Rd: register to load
191 #define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
193 /* Move hi register (Thumb mode)
194 * Rd: destination register
195 * Rm: source register
197 #define ARMV7M_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
199 /* No operation (Thumb mode)
201 #define ARMV7M_T_NOP (0x46c0 | (0x46c0 << 16))
203 /* Move immediate to register (Thumb state)
204 * Rd: destination register
205 * Im: 8-bit immediate value
207 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
209 /* Branch and Exchange
210 * Rm: register containing branch target
212 #define ARMV7M_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
214 /* Branch (Thumb state)
217 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
219 #endif /* ARMV7M_H */