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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "replacements.h"
  28
  29 #include "armv7m.h"
  30 #include "register.h"
  31 #include "target.h"
  32 #include "log.h"
  33 #include "jtag.h"
  34 #include "arm_jtag.h"
  35
  36 #include <stdlib.h>
  37 #include <string.h>
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 char* armv7m_mode_strings[] =
  44 {
  45         "Thread", "Thread (User)", "Handler",
  46 };
  47
  48 char* armv7m_exception_strings[] =
  49 {
  50         "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
  51         "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  52 };
  53
  54 char* armv7m_core_reg_list[] =
  55 {
  56         /* Registers accessed through core debug */
  57         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  58         "sp", "lr", "pc",
  59         "xPSR", "msp", "psp",
  60         /* Registers accessed through special reg 20 */
  61         "primask", "basepri", "faultmask", "control"
  62 };
  63
  64 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  65
  66 reg_t armv7m_gdb_dummy_fp_reg =
  67 {
  68         "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  69 };
  70
  71 u8 armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
  72
  73 reg_t armv7m_gdb_dummy_fps_reg =
  74 {
  75         "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
  76 };
  77
  78 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
  79 {
  80         /*  CORE_GP are accesible using the core debug registers */
  81         {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  82         {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  83         {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  84         {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  85         {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  86         {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  87         {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  88         {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  89         {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  90         {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  91         {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  92         {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  93         {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  94         {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  95         {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  96         {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  97
  98         {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
  99         {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
 100         {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
 101
 102         /*  CORE_SP are accesible using coreregister 20 */
 103         {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
 104         {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
 105         {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
 106         {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}  /* CONTROL */
 107 };
 108
 109 int armv7m_core_reg_arch_type = -1;
 110
 111 int armv7m_restore_context(target_t *target)
 112 {
 113         int i;
 114
 115         /* get pointers to arch-specific information */
 116         armv7m_common_t *armv7m = target->arch_info;
 117
 118         LOG_DEBUG(" ");
 119
 120         if (armv7m->pre_restore_context)
 121                 armv7m->pre_restore_context(target);
 122
 123         for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
 124         {
 125                 if (armv7m->core_cache->reg_list[i].dirty)
 126                 {
 127                         armv7m->write_core_reg(target, i);
 128                 }
 129         }
 130
 131         if (armv7m->post_restore_context)
 132                 armv7m->post_restore_context(target);
 133
 134         return ERROR_OK;
 135 }
 136
 137 /* Core state functions */
 138 char *armv7m_exception_string(int number)
 139 {
 140         static char enamebuf[32];
 141
 142         if ((number < 0) | (number > 511))
 143                 return "Invalid exception";
 144         if (number < 16)
 145                 return armv7m_exception_strings[number];
 146         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 147         return enamebuf;
 148 }
 149
 150 int armv7m_get_core_reg(reg_t *reg)
 151 {
 152         int retval;
 153         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 154         target_t *target = armv7m_reg->target;
 155         armv7m_common_t *armv7m_target = target->arch_info;
 156
 157         if (target->state != TARGET_HALTED)
 158         {
 159                 return ERROR_TARGET_NOT_HALTED;
 160         }
 161
 162         retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
 163
 164         return retval;
 165 }
 166
 167 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
 168 {
 169         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 170         target_t *target = armv7m_reg->target;
 171         u32 value = buf_get_u32(buf, 0, 32);
 172
 173         if (target->state != TARGET_HALTED)
 174         {
 175                 return ERROR_TARGET_NOT_HALTED;
 176         }
 177
 178         buf_set_u32(reg->value, 0, 32, value);
 179         reg->dirty = 1;
 180         reg->valid = 1;
 181
 182         return ERROR_OK;
 183 }
 184
 185 int armv7m_read_core_reg(struct target_s *target, int num)
 186 {
 187         u32 reg_value;
 188         int retval;
 189         armv7m_core_reg_t * armv7m_core_reg;
 190
 191         /* get pointers to arch-specific information */
 192         armv7m_common_t *armv7m = target->arch_info;
 193
 194         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 195                 return ERROR_INVALID_ARGUMENTS;
 196
 197         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 198         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 199         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 200         armv7m->core_cache->reg_list[num].valid = 1;
 201         armv7m->core_cache->reg_list[num].dirty = 0;
 202
 203         return ERROR_OK;
 204 }
 205
 206 int armv7m_write_core_reg(struct target_s *target, int num)
 207 {
 208         int retval;
 209         u32 reg_value;
 210         armv7m_core_reg_t *armv7m_core_reg;
 211
 212         /* get pointers to arch-specific information */
 213         armv7m_common_t *armv7m = target->arch_info;
 214
 215         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 216                 return ERROR_INVALID_ARGUMENTS;
 217
 218         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 219         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 220         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 221         if (retval != ERROR_OK)
 222         {
 223                 LOG_ERROR("JTAG failure");
 224                 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 225                 return ERROR_JTAG_DEVICE_ERROR;
 226         }
 227         LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
 228         armv7m->core_cache->reg_list[num].valid = 1;
 229         armv7m->core_cache->reg_list[num].dirty = 0;
 230
 231         return ERROR_OK;
 232 }
 233
 234 int armv7m_invalidate_core_regs(target_t *target)
 235 {
 236         /* get pointers to arch-specific information */
 237         armv7m_common_t *armv7m = target->arch_info;
 238         int i;
 239
 240         for (i = 0; i < armv7m->core_cache->num_regs; i++)
 241         {
 242                 armv7m->core_cache->reg_list[i].valid = 0;
 243                 armv7m->core_cache->reg_list[i].dirty = 0;
 244         }
 245
 246         return ERROR_OK;
 247 }
 248
 249 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
 250 {
 251         /* get pointers to arch-specific information */
 252         armv7m_common_t *armv7m = target->arch_info;
 253         int i;
 254
 255         *reg_list_size = 26;
 256         *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
 257
 258         for (i = 0; i < 16; i++)
 259         {
 260                 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 261         }
 262
 263         for (i = 16; i < 24; i++)
 264         {
 265                 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
 266         }
 267
 268         (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
 269
 270         /* ARMV7M is always in thumb mode, try to make GDB understand this
 271          * if it does not support this arch */
 272         armv7m->core_cache->reg_list[15].value[0] |= 1;
 273         (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 274         return ERROR_OK;
 275 }
 276
 277 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 278 {
 279         /* get pointers to arch-specific information */
 280         armv7m_common_t *armv7m = target->arch_info;
 281         armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
 282         enum armv7m_mode core_mode = armv7m->core_mode;
 283         int retval = ERROR_OK;
 284         u32 pc;
 285         int i;
 286         u32 context[ARMV7NUMCOREREGS];
 287
 288         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 289         {
 290                 LOG_ERROR("current target isn't an ARMV7M target");
 291                 return ERROR_TARGET_INVALID;
 292         }
 293
 294         if (target->state != TARGET_HALTED)
 295         {
 296                 LOG_WARNING("target not halted");
 297                 return ERROR_TARGET_NOT_HALTED;
 298         }
 299
 300         /* refresh core register cache */
 301         /* Not needed if core register cache is always consistent with target process state */
 302         for (i = 0; i < ARMV7NUMCOREREGS; i++)
 303         {
 304                 if (!armv7m->core_cache->reg_list[i].valid)
 305                         armv7m->read_core_reg(target, i);
 306                 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 307         }
 308
 309         for (i = 0; i < num_mem_params; i++)
 310         {
 311                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 312         }
 313
 314         for (i = 0; i < num_reg_params; i++)
 315         {
 316                 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 317                 u32 regvalue;
 318
 319                 if (!reg)
 320                 {
 321                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 322                         exit(-1);
 323                 }
 324
 325                 if (reg->size != reg_params[i].size)
 326                 {
 327                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 328                         exit(-1);
 329                 }
 330
 331                 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 332                 armv7m_set_core_reg(reg, reg_params[i].value);
 333         }
 334
 335         if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
 336         {
 337                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 338                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
 339                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
 340                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 341         }
 342
 343         /* ARMV7M always runs in Thumb state */
 344         if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
 345         {
 346                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
 347                 return ERROR_TARGET_FAILURE;
 348         }
 349
 350         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 351         sequence to write register values to the processor and the read them back */
 352         target_resume(target, 0, entry_point, 1, 1);
 353         target_poll(target);
 354
 355         while (target->state != TARGET_HALTED)
 356         {
 357                 usleep(5000);
 358                 target_poll(target);
 359                 if ((timeout_ms -= 5) <= 0)
 360                 {
 361                         LOG_ERROR("timeout waiting for algorithm to complete, trying to halt target");
 362                         target_halt(target);
 363                         timeout_ms = 1000;
 364                         while (target->state != TARGET_HALTED)
 365                         {
 366                                 usleep(10000);
 367                                 target_poll(target);
 368                                 if ((timeout_ms -= 10) <= 0)
 369                                 {
 370                                         LOG_ERROR("target didn't reenter debug state, exiting");
 371                                         exit(-1);
 372                                 }
 373                         }
 374                         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 375                         LOG_DEBUG("failed algoritm halted at 0x%x ", pc);
 376                         retval = ERROR_TARGET_TIMEOUT;
 377                 }
 378         }
 379
 380         breakpoint_remove(target, exit_point);
 381
 382         /* Read memory values to mem_params[] */
 383         for (i = 0; i < num_mem_params; i++)
 384         {
 385                 if (mem_params[i].direction != PARAM_OUT)
 386                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 387         }
 388
 389         /* Copy core register values to reg_params[] */
 390         for (i = 0; i < num_reg_params; i++)
 391         {
 392                 if (reg_params[i].direction != PARAM_OUT)
 393                 {
 394                         reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 395
 396                         if (!reg)
 397                         {
 398                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 399                                 exit(-1);
 400                         }
 401
 402                         if (reg->size != reg_params[i].size)
 403                         {
 404                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 405                                 exit(-1);
 406                         }
 407
 408                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 409                 }
 410         }
 411
 412         for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
 413         {
 414                 LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
 415                 buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
 416                 armv7m->core_cache->reg_list[i].valid = 1;
 417                 armv7m->core_cache->reg_list[i].dirty = 1;
 418         }
 419
 420         armv7m->core_mode = core_mode;
 421
 422         return retval;
 423 }
 424
 425 int armv7m_arch_state(struct target_s *target)
 426 {
 427         /* get pointers to arch-specific information */
 428         armv7m_common_t *armv7m = target->arch_info;
 429
 430         LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
 431                 target_debug_reason_strings[target->debug_reason],
 432                 armv7m_mode_strings[armv7m->core_mode],
 433                 armv7m_exception_string(armv7m->exception_number),
 434                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 435                 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
 436
 437         return ERROR_OK;
 438 }
 439
 440 reg_cache_t *armv7m_build_reg_cache(target_t *target)
 441 {
 442         /* get pointers to arch-specific information */
 443         armv7m_common_t *armv7m = target->arch_info;
 444
 445         int num_regs = ARMV7NUMCOREREGS;
 446         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 447         reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 448         reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 449         armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
 450         int i;
 451
 452         if (armv7m_core_reg_arch_type == -1)
 453                 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
 454
 455         /* Build the process context cache */
 456         cache->name = "arm v7m registers";
 457         cache->next = NULL;
 458         cache->reg_list = reg_list;
 459         cache->num_regs = num_regs;
 460         (*cache_p) = cache;
 461         armv7m->core_cache = cache;
 462
 463         for (i = 0; i < num_regs; i++)
 464         {
 465                 arch_info[i] = armv7m_core_reg_list_arch_info[i];
 466                 arch_info[i].target = target;
 467                 arch_info[i].armv7m_common = armv7m;
 468                 reg_list[i].name = armv7m_core_reg_list[i];
 469                 reg_list[i].size = 32;
 470                 reg_list[i].value = calloc(1, 4);
 471                 reg_list[i].dirty = 0;
 472                 reg_list[i].valid = 0;
 473                 reg_list[i].bitfield_desc = NULL;
 474                 reg_list[i].num_bitfields = 0;
 475                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 476                 reg_list[i].arch_info = &arch_info[i];
 477         }
 478
 479         return cache;
 480 }
 481
 482 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 483 {
 484         armv7m_build_reg_cache(target);
 485
 486         return ERROR_OK;
 487 }
 488
 489 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
 490 {
 491         /* register arch-specific functions */
 492
 493         target->arch_info = armv7m;
 494         armv7m->read_core_reg = armv7m_read_core_reg;
 495         armv7m->write_core_reg = armv7m_write_core_reg;
 496
 497         return ERROR_OK;
 498 }
 499
 500 int armv7m_register_commands(struct command_context_s *cmd_ctx)
 501 {
 502         return ERROR_OK;
 503 }
 504
 505 int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
 506 {
 507         working_area_t *crc_algorithm;
 508         armv7m_algorithm_t armv7m_info;
 509         reg_param_t reg_params[2];
 510         int retval;
 511
 512         u16 cortex_m3_crc_code[] = {
 513                 0x4602,                                 /* mov  r2, r0 */
 514                 0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
 515                 0x460B,                                 /* mov  r3, r1 */
 516                 0xF04F, 0x0400,                 /* mov  r4, #0 */
 517                 0xE013,                                 /* b    ncomp */
 518                                                                 /* nbyte: */
 519                 0x5D11,                                 /* ldrb r1, [r2, r4] */
 520                 0xF8DF, 0x7028,                 /* ldr          r7, CRC32XOR */
 521                 0xEA80, 0x6001,                 /* eor          r0, r0, r1, asl #24 */
 522
 523                 0xF04F, 0x0500,                 /* mov          r5, #0 */
 524                                                                 /* loop: */
 525                 0x2800,                                 /* cmp          r0, #0 */
 526                 0xEA4F, 0x0640,                 /* mov          r6, r0, asl #1 */
 527                 0xF105, 0x0501,                 /* add          r5, r5, #1 */
 528                 0x4630,                                 /* mov          r0, r6 */
 529                 0xBFB8,                                 /* it           lt */
 530                 0xEA86, 0x0007,                 /* eor          r0, r6, r7 */
 531                 0x2D08,                                 /* cmp          r5, #8 */
 532                 0xD1F4,                                 /* bne          loop */
 533
 534                 0xF104, 0x0401,                 /* add  r4, r4, #1 */
 535                                                                 /* ncomp: */
 536                 0x429C,                                 /* cmp  r4, r3 */
 537                 0xD1E9,                                 /* bne  nbyte */
 538                                                                 /* end: */
 539                 0xE7FE,                                 /* b    end */
 540                 0x1DB7, 0x04C1                  /* CRC32XOR:    .word 0x04C11DB7 */
 541         };
 542
 543         int i;
 544
 545         if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
 546         {
 547                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 548         }
 549
 550         /* convert flash writing code into a buffer in target endianness */
 551         for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
 552                 target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i]);
 553
 554         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 555         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 556
 557         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 558         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 559
 560         buf_set_u32(reg_params[0].value, 0, 32, address);
 561         buf_set_u32(reg_params[1].value, 0, 32, count);
 562
 563         if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
 564                 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
 565         {
 566                 LOG_ERROR("error executing cortex_m3 crc algorithm");
 567                 destroy_reg_param(&reg_params[0]);
 568                 destroy_reg_param(&reg_params[1]);
 569                 target_free_working_area(target, crc_algorithm);
 570                 return retval;
 571         }
 572
 573         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 574
 575         destroy_reg_param(&reg_params[0]);
 576         destroy_reg_param(&reg_params[1]);
 577
 578         target_free_working_area(target, crc_algorithm);
 579
 580         return ERROR_OK;
 581 }
 582
 583