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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  12  *   oyvind.harboe@zylin.com                                               *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  ***************************************************************************/
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include "replacements.h"
  34
  35 #include "armv7m.h"
  36 #include "register.h"
  37 #include "target.h"
  38 #include "log.h"
  39 #include "jtag.h"
  40 #include "arm_jtag.h"
  41
  42 #include <stdlib.h>
  43 #include <string.h>
  44
  45 #if 0
  46 #define _DEBUG_INSTRUCTION_EXECUTION_
  47 #endif
  48
  49 char* armv7m_mode_strings[] =
  50 {
  51         "Thread", "Thread (User)", "Handler",
  52 };
  53
  54 char* armv7m_exception_strings[] =
  55 {
  56         "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
  57         "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  58 };
  59
  60 char* armv7m_core_reg_list[] =
  61 {
  62         /* Registers accessed through core debug */
  63         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  64         "sp", "lr", "pc",
  65         "xPSR", "msp", "psp",
  66         /* Registers accessed through special reg 20 */
  67         "primask", "basepri", "faultmask", "control"
  68 };
  69
  70 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  71
  72 reg_t armv7m_gdb_dummy_fp_reg =
  73 {
  74         "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  75 };
  76
  77 u8 armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
  78
  79 reg_t armv7m_gdb_dummy_fps_reg =
  80 {
  81         "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
  82 };
  83
  84 #ifdef ARMV7_GDB_HACKS
  85 u8 armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  86
  87 reg_t armv7m_gdb_dummy_cpsr_reg =
  88 {
  89         "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
  90 };
  91 #endif
  92
  93 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
  94 {
  95         /*  CORE_GP are accesible using the core debug registers */
  96         {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  97         {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  98         {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  99         {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 100         {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 101         {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 102         {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 103         {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 104         {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 105         {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 106         {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 107         {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 108         {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 109         {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 110         {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 111         {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 112
 113         {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
 114         {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
 115         {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
 116
 117         /*  CORE_SP are accesible using coreregister 20 */
 118         {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
 119         {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
 120         {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
 121         {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}  /* CONTROL */
 122 };
 123
 124 int armv7m_core_reg_arch_type = -1;
 125 int armv7m_dummy_core_reg_arch_type = -1;
 126
 127 int armv7m_restore_context(target_t *target)
 128 {
 129         int i;
 130
 131         /* get pointers to arch-specific information */
 132         armv7m_common_t *armv7m = target->arch_info;
 133
 134         LOG_DEBUG(" ");
 135
 136         if (armv7m->pre_restore_context)
 137                 armv7m->pre_restore_context(target);
 138
 139         for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
 140         {
 141                 if (armv7m->core_cache->reg_list[i].dirty)
 142                 {
 143                         armv7m->write_core_reg(target, i);
 144                 }
 145         }
 146
 147         if (armv7m->post_restore_context)
 148                 armv7m->post_restore_context(target);
 149
 150         return ERROR_OK;
 151 }
 152
 153 /* Core state functions */
 154 char *armv7m_exception_string(int number)
 155 {
 156         static char enamebuf[32];
 157
 158         if ((number < 0) | (number > 511))
 159                 return "Invalid exception";
 160         if (number < 16)
 161                 return armv7m_exception_strings[number];
 162         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 163         return enamebuf;
 164 }
 165
 166 int armv7m_get_core_reg(reg_t *reg)
 167 {
 168         int retval;
 169         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 170         target_t *target = armv7m_reg->target;
 171         armv7m_common_t *armv7m_target = target->arch_info;
 172
 173         if (target->state != TARGET_HALTED)
 174         {
 175                 return ERROR_TARGET_NOT_HALTED;
 176         }
 177
 178         retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
 179
 180         return retval;
 181 }
 182
 183 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
 184 {
 185         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 186         target_t *target = armv7m_reg->target;
 187         u32 value = buf_get_u32(buf, 0, 32);
 188
 189         if (target->state != TARGET_HALTED)
 190         {
 191                 return ERROR_TARGET_NOT_HALTED;
 192         }
 193
 194         buf_set_u32(reg->value, 0, 32, value);
 195         reg->dirty = 1;
 196         reg->valid = 1;
 197
 198         return ERROR_OK;
 199 }
 200
 201 int armv7m_read_core_reg(struct target_s *target, int num)
 202 {
 203         u32 reg_value;
 204         int retval;
 205         armv7m_core_reg_t * armv7m_core_reg;
 206
 207         /* get pointers to arch-specific information */
 208         armv7m_common_t *armv7m = target->arch_info;
 209
 210         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 211                 return ERROR_INVALID_ARGUMENTS;
 212
 213         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 214         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 215         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 216         armv7m->core_cache->reg_list[num].valid = 1;
 217         armv7m->core_cache->reg_list[num].dirty = 0;
 218
 219         return ERROR_OK;
 220 }
 221
 222 int armv7m_write_core_reg(struct target_s *target, int num)
 223 {
 224         int retval;
 225         u32 reg_value;
 226         armv7m_core_reg_t *armv7m_core_reg;
 227
 228         /* get pointers to arch-specific information */
 229         armv7m_common_t *armv7m = target->arch_info;
 230
 231         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 232                 return ERROR_INVALID_ARGUMENTS;
 233
 234         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 235         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 236         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 237         if (retval != ERROR_OK)
 238         {
 239                 LOG_ERROR("JTAG failure");
 240                 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 241                 return ERROR_JTAG_DEVICE_ERROR;
 242         }
 243         LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
 244         armv7m->core_cache->reg_list[num].valid = 1;
 245         armv7m->core_cache->reg_list[num].dirty = 0;
 246
 247         return ERROR_OK;
 248 }
 249
 250 int armv7m_invalidate_core_regs(target_t *target)
 251 {
 252         /* get pointers to arch-specific information */
 253         armv7m_common_t *armv7m = target->arch_info;
 254         int i;
 255
 256         for (i = 0; i < armv7m->core_cache->num_regs; i++)
 257         {
 258                 armv7m->core_cache->reg_list[i].valid = 0;
 259                 armv7m->core_cache->reg_list[i].dirty = 0;
 260         }
 261
 262         return ERROR_OK;
 263 }
 264
 265 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
 266 {
 267         /* get pointers to arch-specific information */
 268         armv7m_common_t *armv7m = target->arch_info;
 269         int i;
 270
 271         *reg_list_size = 26;
 272         *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
 273
 274         for (i = 0; i < 16; i++)
 275         {
 276                 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 277         }
 278
 279         for (i = 16; i < 24; i++)
 280         {
 281                 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
 282         }
 283
 284         (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
 285
 286 #ifdef ARMV7_GDB_HACKS
 287         /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
 288         (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
 289
 290         /* ARMV7M is always in thumb mode, try to make GDB understand this
 291          * if it does not support this arch */
 292         armv7m->core_cache->reg_list[15].value[0] |= 1;
 293 #else
 294         (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 295 #endif
 296
 297         return ERROR_OK;
 298 }
 299
 300 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 301 {
 302         /* get pointers to arch-specific information */
 303         armv7m_common_t *armv7m = target->arch_info;
 304         armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
 305         enum armv7m_mode core_mode = armv7m->core_mode;
 306         int retval = ERROR_OK;
 307         u32 pc;
 308         int i;
 309         u32 context[ARMV7NUMCOREREGS];
 310
 311         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 312         {
 313                 LOG_ERROR("current target isn't an ARMV7M target");
 314                 return ERROR_TARGET_INVALID;
 315         }
 316
 317         if (target->state != TARGET_HALTED)
 318         {
 319                 LOG_WARNING("target not halted");
 320                 return ERROR_TARGET_NOT_HALTED;
 321         }
 322
 323         /* refresh core register cache */
 324         /* Not needed if core register cache is always consistent with target process state */
 325         for (i = 0; i < ARMV7NUMCOREREGS; i++)
 326         {
 327                 if (!armv7m->core_cache->reg_list[i].valid)
 328                         armv7m->read_core_reg(target, i);
 329                 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 330         }
 331
 332         for (i = 0; i < num_mem_params; i++)
 333         {
 334                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 335         }
 336
 337         for (i = 0; i < num_reg_params; i++)
 338         {
 339                 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 340                 u32 regvalue;
 341
 342                 if (!reg)
 343                 {
 344                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 345                         exit(-1);
 346                 }
 347
 348                 if (reg->size != reg_params[i].size)
 349                 {
 350                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 351                         exit(-1);
 352                 }
 353
 354                 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 355                 armv7m_set_core_reg(reg, reg_params[i].value);
 356         }
 357
 358         if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
 359         {
 360                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 361                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
 362                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
 363                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 364         }
 365
 366         /* ARMV7M always runs in Thumb state */
 367         if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
 368         {
 369                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
 370                 return ERROR_TARGET_FAILURE;
 371         }
 372
 373         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 374         sequence to write register values to the processor and the read them back */
 375         target_resume(target, 0, entry_point, 1, 1);
 376         target_poll(target);
 377
 378         target_wait_state(target, TARGET_HALTED, timeout_ms);
 379         if (target->state != TARGET_HALTED)
 380         {
 381                 if ((retval=target_halt(target))!=ERROR_OK)
 382                         return retval;
 383                 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
 384                 {
 385                         return retval;
 386                 }
 387                 return ERROR_TARGET_TIMEOUT;
 388         }
 389
 390
 391         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 392         if (pc != exit_point)
 393         {
 394                 LOG_DEBUG("failed algoritm halted at 0x%x ", pc);
 395                 return ERROR_TARGET_TIMEOUT;
 396         }
 397
 398         breakpoint_remove(target, exit_point);
 399
 400         /* Read memory values to mem_params[] */
 401         for (i = 0; i < num_mem_params; i++)
 402         {
 403                 if (mem_params[i].direction != PARAM_OUT)
 404                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 405         }
 406
 407         /* Copy core register values to reg_params[] */
 408         for (i = 0; i < num_reg_params; i++)
 409         {
 410                 if (reg_params[i].direction != PARAM_OUT)
 411                 {
 412                         reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 413
 414                         if (!reg)
 415                         {
 416                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 417                                 exit(-1);
 418                         }
 419
 420                         if (reg->size != reg_params[i].size)
 421                         {
 422                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 423                                 exit(-1);
 424                         }
 425
 426                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 427                 }
 428         }
 429
 430         for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
 431         {
 432                 LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
 433                 buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
 434                 armv7m->core_cache->reg_list[i].valid = 1;
 435                 armv7m->core_cache->reg_list[i].dirty = 1;
 436         }
 437
 438         armv7m->core_mode = core_mode;
 439
 440         return retval;
 441 }
 442
 443 int armv7m_arch_state(struct target_s *target)
 444 {
 445         /* get pointers to arch-specific information */
 446         armv7m_common_t *armv7m = target->arch_info;
 447
 448         LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
 449                  Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
 450                 armv7m_mode_strings[armv7m->core_mode],
 451                 armv7m_exception_string(armv7m->exception_number),
 452                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 453                 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
 454
 455         return ERROR_OK;
 456 }
 457
 458 reg_cache_t *armv7m_build_reg_cache(target_t *target)
 459 {
 460         /* get pointers to arch-specific information */
 461         armv7m_common_t *armv7m = target->arch_info;
 462
 463         int num_regs = ARMV7NUMCOREREGS;
 464         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 465         reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 466         reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 467         armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
 468         int i;
 469
 470         if (armv7m_core_reg_arch_type == -1)
 471         {
 472                 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
 473         }
 474
 475         register_init_dummy(&armv7m_gdb_dummy_fps_reg);
 476 #ifdef ARMV7_GDB_HACKS
 477         register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
 478 #endif
 479         register_init_dummy(&armv7m_gdb_dummy_fp_reg);
 480
 481         /* Build the process context cache */
 482         cache->name = "arm v7m registers";
 483         cache->next = NULL;
 484         cache->reg_list = reg_list;
 485         cache->num_regs = num_regs;
 486         (*cache_p) = cache;
 487         armv7m->core_cache = cache;
 488
 489         for (i = 0; i < num_regs; i++)
 490         {
 491                 arch_info[i] = armv7m_core_reg_list_arch_info[i];
 492                 arch_info[i].target = target;
 493                 arch_info[i].armv7m_common = armv7m;
 494                 reg_list[i].name = armv7m_core_reg_list[i];
 495                 reg_list[i].size = 32;
 496                 reg_list[i].value = calloc(1, 4);
 497                 reg_list[i].dirty = 0;
 498                 reg_list[i].valid = 0;
 499                 reg_list[i].bitfield_desc = NULL;
 500                 reg_list[i].num_bitfields = 0;
 501                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 502                 reg_list[i].arch_info = &arch_info[i];
 503         }
 504
 505         return cache;
 506 }
 507
 508 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 509 {
 510         armv7m_build_reg_cache(target);
 511
 512         return ERROR_OK;
 513 }
 514
 515 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
 516 {
 517         /* register arch-specific functions */
 518
 519         target->arch_info = armv7m;
 520         armv7m->read_core_reg = armv7m_read_core_reg;
 521         armv7m->write_core_reg = armv7m_write_core_reg;
 522
 523         return ERROR_OK;
 524 }
 525
 526 int armv7m_register_commands(struct command_context_s *cmd_ctx)
 527 {
 528         return ERROR_OK;
 529 }
 530
 531 int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
 532 {
 533         working_area_t *crc_algorithm;
 534         armv7m_algorithm_t armv7m_info;
 535         reg_param_t reg_params[2];
 536         int retval;
 537
 538         u16 cortex_m3_crc_code[] = {
 539                 0x4602,                                 /* mov  r2, r0 */
 540                 0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
 541                 0x460B,                                 /* mov  r3, r1 */
 542                 0xF04F, 0x0400,                 /* mov  r4, #0 */
 543                 0xE013,                                 /* b    ncomp */
 544                                                                 /* nbyte: */
 545                 0x5D11,                                 /* ldrb r1, [r2, r4] */
 546                 0xF8DF, 0x7028,                 /* ldr          r7, CRC32XOR */
 547                 0xEA80, 0x6001,                 /* eor          r0, r0, r1, asl #24 */
 548
 549                 0xF04F, 0x0500,                 /* mov          r5, #0 */
 550                                                                 /* loop: */
 551                 0x2800,                                 /* cmp          r0, #0 */
 552                 0xEA4F, 0x0640,                 /* mov          r6, r0, asl #1 */
 553                 0xF105, 0x0501,                 /* add          r5, r5, #1 */
 554                 0x4630,                                 /* mov          r0, r6 */
 555                 0xBFB8,                                 /* it           lt */
 556                 0xEA86, 0x0007,                 /* eor          r0, r6, r7 */
 557                 0x2D08,                                 /* cmp          r5, #8 */
 558                 0xD1F4,                                 /* bne          loop */
 559
 560                 0xF104, 0x0401,                 /* add  r4, r4, #1 */
 561                                                                 /* ncomp: */
 562                 0x429C,                                 /* cmp  r4, r3 */
 563                 0xD1E9,                                 /* bne  nbyte */
 564                                                                 /* end: */
 565                 0xE7FE,                                 /* b    end */
 566                 0x1DB7, 0x04C1                  /* CRC32XOR:    .word 0x04C11DB7 */
 567         };
 568
 569         int i;
 570
 571         if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
 572         {
 573                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 574         }
 575
 576         /* convert flash writing code into a buffer in target endianness */
 577         for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
 578                 target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i]);
 579
 580         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 581         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 582
 583         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 584         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 585
 586         buf_set_u32(reg_params[0].value, 0, 32, address);
 587         buf_set_u32(reg_params[1].value, 0, 32, count);
 588
 589         if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
 590                 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
 591         {
 592                 LOG_ERROR("error executing cortex_m3 crc algorithm");
 593                 destroy_reg_param(&reg_params[0]);
 594                 destroy_reg_param(&reg_params[1]);
 595                 target_free_working_area(target, crc_algorithm);
 596                 return retval;
 597         }
 598
 599         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 600
 601         destroy_reg_param(&reg_params[0]);
 602         destroy_reg_param(&reg_params[1]);
 603
 604         target_free_working_area(target, crc_algorithm);
 605
 606         return ERROR_OK;
 607 }
 608
 609 int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
 610 {
 611         working_area_t *erase_check_algorithm;
 612         reg_param_t reg_params[3];
 613         armv7m_algorithm_t armv7m_info;
 614         int retval;
 615         int i;
 616
 617         u16 erase_check_code[] =
 618         {
 619                                                         /* loop: */
 620                  0xF810, 0x3B01,        /* ldrb         r3, [r0], #1 */
 621                  0xEA02, 0x0203,        /* and  r2, r2, r3 */
 622                  0x3901,                        /* subs         r1, r1, #1 */
 623                  0xD1F9,                        /* bne          loop */
 624                                                         /* end: */
 625                  0xE7FE,                        /* b            end */
 626         };
 627
 628         /* make sure we have a working area */
 629         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
 630         {
 631                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 632         }
 633
 634         /* convert flash writing code into a buffer in target endianness */
 635         for (i = 0; i < (sizeof(erase_check_code)/sizeof(u16)); i++)
 636                 target_write_u16(target, erase_check_algorithm->address + i*sizeof(u16), erase_check_code[i]);
 637
 638         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 639         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 640
 641         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 642         buf_set_u32(reg_params[0].value, 0, 32, address);
 643
 644         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 645         buf_set_u32(reg_params[1].value, 0, 32, count);
 646
 647         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 648         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
 649
 650         if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
 651                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
 652         {
 653                 destroy_reg_param(&reg_params[0]);
 654                 destroy_reg_param(&reg_params[1]);
 655                 destroy_reg_param(&reg_params[2]);
 656                 target_free_working_area(target, erase_check_algorithm);
 657                 return 0;
 658         }
 659
 660         *blank = buf_get_u32(reg_params[2].value, 0, 32);
 661
 662         destroy_reg_param(&reg_params[0]);
 663         destroy_reg_param(&reg_params[1]);
 664         destroy_reg_param(&reg_params[2]);
 665
 666         target_free_working_area(target, erase_check_algorithm);
 667
 668         return ERROR_OK;
 669 }