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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2006 by Magnus Lundin                                   *
   5  *   lundin@mlu.mine.nu                                                    *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "replacements.h"
  27
  28 #include "armv7m.h"
  29 #include "register.h"
  30 #include "target.h"
  31 #include "log.h"
  32 #include "jtag.h"
  33 #include "arm_jtag.h"
  34
  35 #include <stdlib.h>
  36 #include <string.h>
  37
  38 #if 0
  39 #define _DEBUG_INSTRUCTION_EXECUTION_
  40 #endif
  41
  42 char* armv7m_mode_strings[] =
  43 {
  44         "Handler", "Thread"
  45 };
  46
  47 char* armv7m_state_strings[] =
  48 {
  49         "Thumb", "Debug"
  50 };
  51
  52 char* armv7m_exception_strings[] =
  53 {
  54         "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
  55         "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  56 };
  57
  58 char* armv7m_core_reg_list[] =
  59 {
  60 /* Registers accessed through core debug */
  61         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  62         "sp", "lr", "pc",
  63         "xPSR", "msp", "psp",
  64 /* Registers accessed through MSR instructions */
  65 //      "apsr", "iapsr", "ipsr", "epsr",
  66         "primask", "basepri", "faultmask", "control"
  67 };
  68
  69 char* armv7m_core_dbgreg_list[] =
  70 {
  71 /* Registers accessed through core debug */
  72         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  73         "sp", "lr", "pc",
  74         "xPSR", "msp", "psp",
  75 /* Registers accessed through MSR instructions */
  76 //      "dbg_apsr", "iapsr", "ipsr", "epsr",
  77         "primask", "basepri", "faultmask", "dbg_control"
  78 };
  79
  80 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  81
  82 reg_t armv7m_gdb_dummy_fp_reg =
  83 {
  84         "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  85 };
  86
  87 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
  88 {
  89         /*  CORE_GP are accesible using the core debug registers */
  90         {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  91         {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  92         {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  93         {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  94         {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  95         {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  96         {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  97         {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  98         {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  99         {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 100         {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 101         {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 102         {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 103         {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 104         {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 105         {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 106
 107         {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
 108         {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
 109         {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
 110
 111         /*  CORE_SP are accesible using MSR and MRS instructions */
 112 //      {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
 113 //      {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
 114 //      {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
 115 //      {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
 116
 117         {0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
 118         {0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
 119         {0x13, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
 120         {0x14, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}  /* CONTROL */
 121 };
 122
 123 int armv7m_core_reg_arch_type = -1;
 124
 125
 126 /* Keep different contexts for the process being debugged and debug algorithms */
 127 enum armv7m_runcontext armv7m_get_context(target_t *target)
 128 {
 129         /* get pointers to arch-specific information */
 130         armv7m_common_t *armv7m = target->arch_info;
 131
 132         if (armv7m->process_context == armv7m->core_cache)
 133                 return ARMV7M_PROCESS_CONTEXT;
 134         if (armv7m->debug_context == armv7m->core_cache)
 135                 return ARMV7M_DEBUG_CONTEXT;
 136
 137         ERROR("Invalid runcontext");
 138         exit(-1);
 139 }
 140
 141 int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
 142 {
 143         int i;
 144         /* get pointers to arch-specific information */
 145         armv7m_common_t *armv7m = target->arch_info;
 146
 147         if ((target->state != TARGET_HALTED) && (target->state != TARGET_RESET))
 148         {
 149                 WARNING("target not halted, switch context ");
 150                 return ERROR_TARGET_NOT_HALTED;
 151         }
 152
 153         if (new_ctx == armv7m_get_context(target))
 154                 return ERROR_OK;
 155
 156         switch (new_ctx)
 157         {
 158                 case ARMV7M_PROCESS_CONTEXT:
 159                          armv7m->core_cache = armv7m->process_context;
 160                          break;
 161                 case ARMV7M_DEBUG_CONTEXT:
 162                          armv7m->core_cache = armv7m->debug_context;
 163                          break;
 164                 default:
 165                         ERROR("Invalid runcontext");
 166                         exit(-1);
 167         }
 168         /* Mark registers in new context as dirty to force reload when run */
 169
 170         for (i = 0; i < armv7m->core_cache->num_regs-1; i++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
 171         {
 172                 armv7m->core_cache->reg_list[i].dirty = 1;
 173         }
 174
 175         return ERROR_OK;
 176 }
 177
 178 /* Core state functions */
 179 char enamebuf[32];
 180 char *armv7m_exception_string(int number)
 181 {
 182         if ((number < 0) | (number > 511))
 183                 return "Invalid exception";
 184         if (number < 16)
 185                 return armv7m_exception_strings[number];
 186         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 187         return enamebuf;
 188 }
 189
 190 int armv7m_get_core_reg(reg_t *reg)
 191 {
 192         int retval;
 193         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 194         target_t *target = armv7m_reg->target;
 195         armv7m_common_t *armv7m_target = target->arch_info;
 196
 197         if (target->state != TARGET_HALTED)
 198         {
 199                 return ERROR_TARGET_NOT_HALTED;
 200         }
 201
 202         retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
 203
 204         return retval;
 205 }
 206
 207 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
 208 {
 209         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 210         target_t *target = armv7m_reg->target;
 211         armv7m_common_t *armv7m_target = target->arch_info;
 212         u32 value = buf_get_u32(buf, 0, 32);
 213
 214         if (target->state != TARGET_HALTED)
 215         {
 216                 return ERROR_TARGET_NOT_HALTED;
 217         }
 218
 219         buf_set_u32(reg->value, 0, 32, value);
 220         reg->dirty = 1;
 221         reg->valid = 1;
 222
 223         return ERROR_OK;
 224 }
 225
 226 int armv7m_read_core_reg(struct target_s *target, int num)
 227 {
 228         u32 reg_value;
 229         int retval;
 230         armv7m_core_reg_t * armv7m_core_reg;
 231
 232         /* get pointers to arch-specific information */
 233         armv7m_common_t *armv7m = target->arch_info;
 234
 235         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 236                 return ERROR_INVALID_ARGUMENTS;
 237
 238         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 239         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 240         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 241         armv7m->core_cache->reg_list[num].valid=1;
 242         armv7m->core_cache->reg_list[num].dirty=0;
 243
 244         return ERROR_OK;
 245 }
 246
 247 int armv7m_write_core_reg(struct target_s *target, int num)
 248 {
 249         int retval;
 250         u32 reg_value;
 251         armv7m_core_reg_t * armv7m_core_reg;
 252
 253         /* get pointers to arch-specific information */
 254         armv7m_common_t *armv7m = target->arch_info;
 255
 256         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 257                 return ERROR_INVALID_ARGUMENTS;
 258
 259         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 260         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 261         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 262         if (retval != ERROR_OK)
 263         {
 264                 ERROR("JTAG failure");
 265                 armv7m->core_cache->reg_list[num].dirty=1;
 266                 return ERROR_JTAG_DEVICE_ERROR;
 267         }
 268         DEBUG("write core reg %i value 0x%x",num ,reg_value);
 269         armv7m->core_cache->reg_list[num].valid=1;
 270         armv7m->core_cache->reg_list[num].dirty=0;
 271
 272         return ERROR_OK;
 273 }
 274
 275 int armv7m_invalidate_core_regs(target_t *target)
 276 {
 277         /* get pointers to arch-specific information */
 278         armv7m_common_t *armv7m = target->arch_info;
 279         int i;
 280
 281         for (i = 0; i < armv7m->core_cache->num_regs; i++)
 282         {
 283                 armv7m->core_cache->reg_list[i].valid = 0;
 284                 armv7m->core_cache->reg_list[i].dirty = 0;
 285         }
 286
 287         return ERROR_OK;
 288 }
 289
 290 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
 291 {
 292         /* get pointers to arch-specific information */
 293         armv7m_common_t *armv7m = target->arch_info;
 294         int i;
 295
 296         if (target->state != TARGET_HALTED)
 297         {
 298                 return ERROR_TARGET_NOT_HALTED;
 299         }
 300
 301         *reg_list_size = 26;
 302         *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
 303
 304         /* TODOLATER correct list of registers, names ? */
 305         for (i = 0; i < *reg_list_size; i++)
 306         {
 307                 if (i < ARMV7NUMCOREREGS)
 308                         (*reg_list)[i] = &armv7m->process_context->reg_list[i];
 309                         //(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 310                 else
 311                         (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
 312         }
 313         /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */
 314         //armv7m->core_cache->reg_list[15].value[0] |= 1;
 315         armv7m->process_context->reg_list[15].value[0] |= 1;
 316         //armv7m->core_cache->reg_list[ARMV7M_xPSR].value[0] = (1<<5);
 317         //armv7m->process_context->reg_list[ARMV7M_xPSR].value[0] = (1<<5);
 318         (*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];
 319         //(*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];
 320         return ERROR_OK;
 321 }
 322
 323 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 324 {
 325         // get pointers to arch-specific information
 326         armv7m_common_t *armv7m = target->arch_info;
 327         armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
 328         enum armv7m_state core_state = armv7m->core_state;
 329         enum armv7m_mode core_mode = armv7m->core_mode;
 330         int retval = ERROR_OK;
 331         u32 pc;
 332         int exit_breakpoint_size = 0;
 333         int i;
 334
 335         armv7m->core_state = core_state;
 336         armv7m->core_mode = core_mode;
 337
 338         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 339         {
 340                 ERROR("current target isn't an ARMV7M target");
 341                 return ERROR_TARGET_INVALID;
 342         }
 343
 344         if (target->state != TARGET_HALTED)
 345         {
 346                 WARNING("target not halted");
 347                 return ERROR_TARGET_NOT_HALTED;
 348         }
 349
 350         /* refresh core register cache */
 351         /* Not needed if core register cache is always consistent with target process state */
 352         armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
 353
 354         for (i = 0; i < num_mem_params; i++)
 355         {
 356                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 357         }
 358
 359         for (i = 0; i < num_reg_params; i++)
 360         {
 361                 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 362                 //reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
 363                 //armv7m_core_reg_t * armv7m_core_reg = reg->arch_info;
 364                 u32 regvalue;
 365
 366                 if (!reg)
 367                 {
 368                         ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 369                         exit(-1);
 370                 }
 371
 372                 if (reg->size != reg_params[i].size)
 373                 {
 374                         ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 375                         exit(-1);
 376                 }
 377
 378                 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 379                 //armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, regvalue);
 380                 armv7m_set_core_reg(reg, reg_params[i].value);
 381         }
 382
 383         /* ARMV7M always runs in Thumb state */
 384         exit_breakpoint_size = 2;
 385         if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_SOFT)) != ERROR_OK)
 386         {
 387                 ERROR("can't add breakpoint to finish algorithm execution");
 388                 return ERROR_TARGET_FAILURE;
 389         }
 390
 391         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 392         sequence to write register values to the processor and the read them back */
 393         target->type->resume(target, 0, entry_point, 1, 1);
 394         target->type->poll(target);
 395
 396         while (target->state != TARGET_HALTED)
 397         {
 398                 usleep(5000);
 399                 target->type->poll(target);
 400                 if ((timeout_ms -= 5) <= 0)
 401                 {
 402                         ERROR("timeout waiting for algorithm to complete, trying to halt target");
 403                         target->type->halt(target);
 404                         timeout_ms = 1000;
 405                         while (target->state != TARGET_HALTED)
 406                         {
 407                                 usleep(10000);
 408                                 target->type->poll(target);
 409                                 if ((timeout_ms -= 10) <= 0)
 410                                 {
 411                                         ERROR("target didn't reenter debug state, exiting");
 412                                         exit(-1);
 413                                 }
 414                         }
 415                         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 416                         DEBUG("failed algoritm halted at 0x%x ", pc);
 417                         retval = ERROR_TARGET_TIMEOUT;
 418                 }
 419         }
 420
 421         breakpoint_remove(target, exit_point);
 422
 423         /* Read memory values to mem_params[] */
 424         for (i = 0; i < num_mem_params; i++)
 425         {
 426                 if (mem_params[i].direction != PARAM_OUT)
 427                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 428         }
 429
 430         /* Copy core register values to reg_params[] */
 431         for (i = 0; i < num_reg_params; i++)
 432         {
 433                 if (reg_params[i].direction != PARAM_OUT)
 434                 {
 435                         //reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 436                         reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
 437                         u32 regvalue;
 438
 439                         if (!reg)
 440                         {
 441                                 ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 442                                 exit(-1);
 443                         }
 444
 445                         if (reg->size != reg_params[i].size)
 446                         {
 447                                 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 448                                 exit(-1);
 449                         }
 450
 451                         armv7m_core_reg_t *armv7m_core_reg = reg->arch_info;
 452                         //armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &regvalue);
 453                         //buf_set_u32(reg_params[i].value, 0, 32, regvalue);
 454                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 455                 }
 456         }
 457
 458         /* Mark all core registers !! except control !! as valid but dirty */
 459         /* This will be done by armv7m_use_context in resume function */
 460         //for (i = 0; i < armv7m->core_cache->num_regs-1; i++)
 461         //{
 462         //      armv7m->core_cache->reg_list[i].dirty = 1;
 463         //}
 464
 465         // ????armv7m->core_state = core_state;
 466         // ????armv7m->core_mode = core_mode;
 467
 468         return retval;
 469 }
 470
 471 int armv7m_arch_state(struct target_s *target, char *buf, int buf_size)
 472 {
 473         /* get pointers to arch-specific information */
 474         armv7m_common_t *armv7m = target->arch_info;
 475
 476         snprintf(buf, buf_size,
 477                  "target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
 478                  armv7m_state_strings[armv7m->core_state],
 479                  target_debug_reason_strings[target->debug_reason],
 480                  armv7m_mode_strings[armv7m->core_mode],
 481                  armv7m_exception_string(armv7m->exception_number),
 482                  buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 483                  buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
 484
 485         return ERROR_OK;
 486 }
 487
 488 reg_cache_t *armv7m_build_reg_cache(target_t *target)
 489 {
 490         /* get pointers to arch-specific information */
 491         armv7m_common_t *armv7m = target->arch_info;
 492         arm_jtag_t *jtag_info = &armv7m->jtag_info;
 493
 494         int num_regs = ARMV7NUMCOREREGS;
 495         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 496         reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 497         reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 498         armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
 499         int i;
 500
 501         if (armv7m_core_reg_arch_type == -1)
 502                 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
 503
 504         /* Build the process context cache */
 505         cache->name = "arm v7m registers";
 506         cache->next = NULL;
 507         cache->reg_list = reg_list;
 508         cache->num_regs = num_regs;
 509         (*cache_p) = cache;
 510         armv7m->core_cache = cache;
 511         armv7m->process_context = cache;
 512
 513         for (i = 0; i < num_regs; i++)
 514         {
 515                 arch_info[i] = armv7m_core_reg_list_arch_info[i];
 516                 arch_info[i].target = target;
 517                 arch_info[i].armv7m_common = armv7m;
 518                 reg_list[i].name = armv7m_core_reg_list[i];
 519                 reg_list[i].size = 32;
 520                 reg_list[i].value = calloc(1, 4);
 521                 reg_list[i].dirty = 0;
 522                 reg_list[i].valid = 0;
 523                 reg_list[i].bitfield_desc = NULL;
 524                 reg_list[i].num_bitfields = 0;
 525                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 526                 reg_list[i].arch_info = &arch_info[i];
 527         }
 528
 529         /* Build the debug context cache*/
 530         cache = malloc(sizeof(reg_cache_t));
 531         reg_list = malloc(sizeof(reg_t) * num_regs);
 532
 533         cache->name = "arm v7m debug registers";
 534         cache->next = NULL;
 535         cache->reg_list = reg_list;
 536         cache->num_regs = num_regs;
 537         armv7m->debug_context = cache;
 538         armv7m->process_context->next = cache;
 539
 540         for (i = 0; i < num_regs; i++)
 541         {
 542                 reg_list[i].name = armv7m_core_dbgreg_list[i];
 543                 reg_list[i].size = 32;
 544                 reg_list[i].value = calloc(1, 4);
 545                 reg_list[i].dirty = 0;
 546                 reg_list[i].valid = 0;
 547                 reg_list[i].bitfield_desc = NULL;
 548                 reg_list[i].num_bitfields = 0;
 549                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 550                 reg_list[i].arch_info = &arch_info[i];
 551         }
 552
 553     return cache;
 554 }
 555
 556 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 557 {
 558         armv7m_build_reg_cache(target);
 559
 560         return ERROR_OK;
 561 }
 562
 563 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
 564 {
 565         /* register arch-specific functions */
 566
 567         target->arch_info = armv7m;
 568         armv7m->core_state = ARMV7M_STATE_THUMB;
 569         armv7m->read_core_reg = armv7m_read_core_reg;
 570         armv7m->write_core_reg = armv7m_write_core_reg;
 571
 572         return ERROR_OK;
 573 }
 574
 575 int armv7m_register_commands(struct command_context_s *cmd_ctx)
 576 {
 577         int retval;
 578
 579         return ERROR_OK;
 580 }