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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "replacements.h"
  31
  32 #include "armv7m.h"
  33 #include "register.h"
  34 #include "target.h"
  35 #include "log.h"
  36 #include "jtag.h"
  37 #include "arm_jtag.h"
  38
  39 #include <stdlib.h>
  40 #include <string.h>
  41
  42 #if 0
  43 #define _DEBUG_INSTRUCTION_EXECUTION_
  44 #endif
  45
  46 char* armv7m_mode_strings[] =
  47 {
  48         "Thread", "Thread (User)", "Handler",
  49 };
  50
  51 char* armv7m_exception_strings[] =
  52 {
  53         "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
  54         "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  55 };
  56
  57 char* armv7m_core_reg_list[] =
  58 {
  59         /* Registers accessed through core debug */
  60         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  61         "sp", "lr", "pc",
  62         "xPSR", "msp", "psp",
  63         /* Registers accessed through special reg 20 */
  64         "primask", "basepri", "faultmask", "control"
  65 };
  66
  67 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  68
  69 reg_t armv7m_gdb_dummy_fp_reg =
  70 {
  71         "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  72 };
  73
  74 u8 armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
  75
  76 reg_t armv7m_gdb_dummy_fps_reg =
  77 {
  78         "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
  79 };
  80
  81 #ifdef ARMV7_GDB_HACKS
  82 u8 armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  83
  84 reg_t armv7m_gdb_dummy_cpsr_reg =
  85 {
  86         "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
  87 };
  88 #endif
  89
  90 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
  91 {
  92         /*  CORE_GP are accesible using the core debug registers */
  93         {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  94         {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  95         {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  96         {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  97         {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  98         {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  99         {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 100         {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 101         {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 102         {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 103         {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 104         {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 105         {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 106         {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 107         {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 108         {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 109
 110         {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
 111         {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
 112         {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
 113
 114         /*  CORE_SP are accesible using coreregister 20 */
 115         {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
 116         {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
 117         {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
 118         {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}  /* CONTROL */
 119 };
 120
 121 int armv7m_core_reg_arch_type = -1;
 122
 123 int armv7m_restore_context(target_t *target)
 124 {
 125         int i;
 126
 127         /* get pointers to arch-specific information */
 128         armv7m_common_t *armv7m = target->arch_info;
 129
 130         LOG_DEBUG(" ");
 131
 132         if (armv7m->pre_restore_context)
 133                 armv7m->pre_restore_context(target);
 134
 135         for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
 136         {
 137                 if (armv7m->core_cache->reg_list[i].dirty)
 138                 {
 139                         armv7m->write_core_reg(target, i);
 140                 }
 141         }
 142
 143         if (armv7m->post_restore_context)
 144                 armv7m->post_restore_context(target);
 145
 146         return ERROR_OK;
 147 }
 148
 149 /* Core state functions */
 150 char *armv7m_exception_string(int number)
 151 {
 152         static char enamebuf[32];
 153
 154         if ((number < 0) | (number > 511))
 155                 return "Invalid exception";
 156         if (number < 16)
 157                 return armv7m_exception_strings[number];
 158         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 159         return enamebuf;
 160 }
 161
 162 int armv7m_get_core_reg(reg_t *reg)
 163 {
 164         int retval;
 165         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 166         target_t *target = armv7m_reg->target;
 167         armv7m_common_t *armv7m_target = target->arch_info;
 168
 169         if (target->state != TARGET_HALTED)
 170         {
 171                 return ERROR_TARGET_NOT_HALTED;
 172         }
 173
 174         retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
 175
 176         return retval;
 177 }
 178
 179 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
 180 {
 181         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 182         target_t *target = armv7m_reg->target;
 183         u32 value = buf_get_u32(buf, 0, 32);
 184
 185         if (target->state != TARGET_HALTED)
 186         {
 187                 return ERROR_TARGET_NOT_HALTED;
 188         }
 189
 190         buf_set_u32(reg->value, 0, 32, value);
 191         reg->dirty = 1;
 192         reg->valid = 1;
 193
 194         return ERROR_OK;
 195 }
 196
 197 int armv7m_read_core_reg(struct target_s *target, int num)
 198 {
 199         u32 reg_value;
 200         int retval;
 201         armv7m_core_reg_t * armv7m_core_reg;
 202
 203         /* get pointers to arch-specific information */
 204         armv7m_common_t *armv7m = target->arch_info;
 205
 206         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 207                 return ERROR_INVALID_ARGUMENTS;
 208
 209         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 210         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 211         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 212         armv7m->core_cache->reg_list[num].valid = 1;
 213         armv7m->core_cache->reg_list[num].dirty = 0;
 214
 215         return ERROR_OK;
 216 }
 217
 218 int armv7m_write_core_reg(struct target_s *target, int num)
 219 {
 220         int retval;
 221         u32 reg_value;
 222         armv7m_core_reg_t *armv7m_core_reg;
 223
 224         /* get pointers to arch-specific information */
 225         armv7m_common_t *armv7m = target->arch_info;
 226
 227         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 228                 return ERROR_INVALID_ARGUMENTS;
 229
 230         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 231         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 232         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 233         if (retval != ERROR_OK)
 234         {
 235                 LOG_ERROR("JTAG failure");
 236                 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 237                 return ERROR_JTAG_DEVICE_ERROR;
 238         }
 239         LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
 240         armv7m->core_cache->reg_list[num].valid = 1;
 241         armv7m->core_cache->reg_list[num].dirty = 0;
 242
 243         return ERROR_OK;
 244 }
 245
 246 int armv7m_invalidate_core_regs(target_t *target)
 247 {
 248         /* get pointers to arch-specific information */
 249         armv7m_common_t *armv7m = target->arch_info;
 250         int i;
 251
 252         for (i = 0; i < armv7m->core_cache->num_regs; i++)
 253         {
 254                 armv7m->core_cache->reg_list[i].valid = 0;
 255                 armv7m->core_cache->reg_list[i].dirty = 0;
 256         }
 257
 258         return ERROR_OK;
 259 }
 260
 261 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
 262 {
 263         /* get pointers to arch-specific information */
 264         armv7m_common_t *armv7m = target->arch_info;
 265         int i;
 266
 267         *reg_list_size = 26;
 268         *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
 269
 270         for (i = 0; i < 16; i++)
 271         {
 272                 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 273         }
 274
 275         for (i = 16; i < 24; i++)
 276         {
 277                 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
 278         }
 279
 280         (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
 281
 282 #ifdef ARMV7_GDB_HACKS
 283         /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
 284         (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
 285
 286         /* ARMV7M is always in thumb mode, try to make GDB understand this
 287          * if it does not support this arch */
 288         armv7m->core_cache->reg_list[15].value[0] |= 1;
 289 #else
 290         (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 291 #endif
 292
 293         return ERROR_OK;
 294 }
 295
 296 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 297 {
 298         /* get pointers to arch-specific information */
 299         armv7m_common_t *armv7m = target->arch_info;
 300         armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
 301         enum armv7m_mode core_mode = armv7m->core_mode;
 302         int retval = ERROR_OK;
 303         u32 pc;
 304         int i;
 305         u32 context[ARMV7NUMCOREREGS];
 306
 307         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 308         {
 309                 LOG_ERROR("current target isn't an ARMV7M target");
 310                 return ERROR_TARGET_INVALID;
 311         }
 312
 313         if (target->state != TARGET_HALTED)
 314         {
 315                 LOG_WARNING("target not halted");
 316                 return ERROR_TARGET_NOT_HALTED;
 317         }
 318
 319         /* refresh core register cache */
 320         /* Not needed if core register cache is always consistent with target process state */
 321         for (i = 0; i < ARMV7NUMCOREREGS; i++)
 322         {
 323                 if (!armv7m->core_cache->reg_list[i].valid)
 324                         armv7m->read_core_reg(target, i);
 325                 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 326         }
 327
 328         for (i = 0; i < num_mem_params; i++)
 329         {
 330                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 331         }
 332
 333         for (i = 0; i < num_reg_params; i++)
 334         {
 335                 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 336                 u32 regvalue;
 337
 338                 if (!reg)
 339                 {
 340                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 341                         exit(-1);
 342                 }
 343
 344                 if (reg->size != reg_params[i].size)
 345                 {
 346                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 347                         exit(-1);
 348                 }
 349
 350                 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 351                 armv7m_set_core_reg(reg, reg_params[i].value);
 352         }
 353
 354         if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
 355         {
 356                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 357                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
 358                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
 359                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 360         }
 361
 362         /* ARMV7M always runs in Thumb state */
 363         if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
 364         {
 365                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
 366                 return ERROR_TARGET_FAILURE;
 367         }
 368
 369         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 370         sequence to write register values to the processor and the read them back */
 371         target_resume(target, 0, entry_point, 1, 1);
 372         target_poll(target);
 373
 374         target_wait_state(target, TARGET_HALTED, timeout_ms);
 375         if (target->state != TARGET_HALTED)
 376         {
 377                 if ((retval=target_halt(target))!=ERROR_OK)
 378                         return retval;
 379                 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
 380                 {
 381                         return retval;
 382                 }
 383                 return ERROR_TARGET_TIMEOUT;
 384         }
 385
 386
 387         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 388         if (pc != exit_point)
 389         {
 390                 LOG_DEBUG("failed algoritm halted at 0x%x ", pc);
 391                 return ERROR_TARGET_TIMEOUT;
 392         }
 393
 394         breakpoint_remove(target, exit_point);
 395
 396         /* Read memory values to mem_params[] */
 397         for (i = 0; i < num_mem_params; i++)
 398         {
 399                 if (mem_params[i].direction != PARAM_OUT)
 400                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 401         }
 402
 403         /* Copy core register values to reg_params[] */
 404         for (i = 0; i < num_reg_params; i++)
 405         {
 406                 if (reg_params[i].direction != PARAM_OUT)
 407                 {
 408                         reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 409
 410                         if (!reg)
 411                         {
 412                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 413                                 exit(-1);
 414                         }
 415
 416                         if (reg->size != reg_params[i].size)
 417                         {
 418                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 419                                 exit(-1);
 420                         }
 421
 422                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 423                 }
 424         }
 425
 426         for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
 427         {
 428                 LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
 429                 buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
 430                 armv7m->core_cache->reg_list[i].valid = 1;
 431                 armv7m->core_cache->reg_list[i].dirty = 1;
 432         }
 433
 434         armv7m->core_mode = core_mode;
 435
 436         return retval;
 437 }
 438
 439 int armv7m_arch_state(struct target_s *target)
 440 {
 441         /* get pointers to arch-specific information */
 442         armv7m_common_t *armv7m = target->arch_info;
 443
 444         LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
 445                  Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
 446                 armv7m_mode_strings[armv7m->core_mode],
 447                 armv7m_exception_string(armv7m->exception_number),
 448                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 449                 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
 450
 451         return ERROR_OK;
 452 }
 453
 454 reg_cache_t *armv7m_build_reg_cache(target_t *target)
 455 {
 456         /* get pointers to arch-specific information */
 457         armv7m_common_t *armv7m = target->arch_info;
 458
 459         int num_regs = ARMV7NUMCOREREGS;
 460         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 461         reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 462         reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 463         armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
 464         int i;
 465
 466         if (armv7m_core_reg_arch_type == -1)
 467                 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
 468
 469         /* Build the process context cache */
 470         cache->name = "arm v7m registers";
 471         cache->next = NULL;
 472         cache->reg_list = reg_list;
 473         cache->num_regs = num_regs;
 474         (*cache_p) = cache;
 475         armv7m->core_cache = cache;
 476
 477         for (i = 0; i < num_regs; i++)
 478         {
 479                 arch_info[i] = armv7m_core_reg_list_arch_info[i];
 480                 arch_info[i].target = target;
 481                 arch_info[i].armv7m_common = armv7m;
 482                 reg_list[i].name = armv7m_core_reg_list[i];
 483                 reg_list[i].size = 32;
 484                 reg_list[i].value = calloc(1, 4);
 485                 reg_list[i].dirty = 0;
 486                 reg_list[i].valid = 0;
 487                 reg_list[i].bitfield_desc = NULL;
 488                 reg_list[i].num_bitfields = 0;
 489                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 490                 reg_list[i].arch_info = &arch_info[i];
 491         }
 492
 493         return cache;
 494 }
 495
 496 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 497 {
 498         armv7m_build_reg_cache(target);
 499
 500         return ERROR_OK;
 501 }
 502
 503 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
 504 {
 505         /* register arch-specific functions */
 506
 507         target->arch_info = armv7m;
 508         armv7m->read_core_reg = armv7m_read_core_reg;
 509         armv7m->write_core_reg = armv7m_write_core_reg;
 510
 511         return ERROR_OK;
 512 }
 513
 514 int armv7m_register_commands(struct command_context_s *cmd_ctx)
 515 {
 516         return ERROR_OK;
 517 }
 518
 519 int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
 520 {
 521         working_area_t *crc_algorithm;
 522         armv7m_algorithm_t armv7m_info;
 523         reg_param_t reg_params[2];
 524         int retval;
 525
 526         u16 cortex_m3_crc_code[] = {
 527                 0x4602,                                 /* mov  r2, r0 */
 528                 0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
 529                 0x460B,                                 /* mov  r3, r1 */
 530                 0xF04F, 0x0400,                 /* mov  r4, #0 */
 531                 0xE013,                                 /* b    ncomp */
 532                                                                 /* nbyte: */
 533                 0x5D11,                                 /* ldrb r1, [r2, r4] */
 534                 0xF8DF, 0x7028,                 /* ldr          r7, CRC32XOR */
 535                 0xEA80, 0x6001,                 /* eor          r0, r0, r1, asl #24 */
 536
 537                 0xF04F, 0x0500,                 /* mov          r5, #0 */
 538                                                                 /* loop: */
 539                 0x2800,                                 /* cmp          r0, #0 */
 540                 0xEA4F, 0x0640,                 /* mov          r6, r0, asl #1 */
 541                 0xF105, 0x0501,                 /* add          r5, r5, #1 */
 542                 0x4630,                                 /* mov          r0, r6 */
 543                 0xBFB8,                                 /* it           lt */
 544                 0xEA86, 0x0007,                 /* eor          r0, r6, r7 */
 545                 0x2D08,                                 /* cmp          r5, #8 */
 546                 0xD1F4,                                 /* bne          loop */
 547
 548                 0xF104, 0x0401,                 /* add  r4, r4, #1 */
 549                                                                 /* ncomp: */
 550                 0x429C,                                 /* cmp  r4, r3 */
 551                 0xD1E9,                                 /* bne  nbyte */
 552                                                                 /* end: */
 553                 0xE7FE,                                 /* b    end */
 554                 0x1DB7, 0x04C1                  /* CRC32XOR:    .word 0x04C11DB7 */
 555         };
 556
 557         int i;
 558
 559         if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
 560         {
 561                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 562         }
 563
 564         /* convert flash writing code into a buffer in target endianness */
 565         for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
 566                 target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i]);
 567
 568         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 569         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 570
 571         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 572         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 573
 574         buf_set_u32(reg_params[0].value, 0, 32, address);
 575         buf_set_u32(reg_params[1].value, 0, 32, count);
 576
 577         if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
 578                 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
 579         {
 580                 LOG_ERROR("error executing cortex_m3 crc algorithm");
 581                 destroy_reg_param(&reg_params[0]);
 582                 destroy_reg_param(&reg_params[1]);
 583                 target_free_working_area(target, crc_algorithm);
 584                 return retval;
 585         }
 586
 587         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 588
 589         destroy_reg_param(&reg_params[0]);
 590         destroy_reg_param(&reg_params[1]);
 591
 592         target_free_working_area(target, crc_algorithm);
 593
 594         return ERROR_OK;
 595 }
 596
 597 int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
 598 {
 599         working_area_t *erase_check_algorithm;
 600         reg_param_t reg_params[3];
 601         armv7m_algorithm_t armv7m_info;
 602         int retval;
 603         int i;
 604
 605         u16 erase_check_code[] =
 606         {
 607                                                         /* loop: */
 608                  0xF810, 0x3B01,        /* ldrb         r3, [r0], #1 */
 609                  0xEA02, 0x0203,        /* and  r2, r2, r3 */
 610                  0x3901,                        /* subs         r1, r1, #1 */
 611                  0xD1F9,                        /* bne          loop */
 612                                                         /* end: */
 613                  0xE7FE,                        /* b            end */
 614         };
 615
 616         /* make sure we have a working area */
 617         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
 618         {
 619                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 620         }
 621
 622         /* convert flash writing code into a buffer in target endianness */
 623         for (i = 0; i < (sizeof(erase_check_code)/sizeof(u16)); i++)
 624                 target_write_u16(target, erase_check_algorithm->address + i*sizeof(u16), erase_check_code[i]);
 625
 626         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 627         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 628
 629         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 630         buf_set_u32(reg_params[0].value, 0, 32, address);
 631
 632         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 633         buf_set_u32(reg_params[1].value, 0, 32, count);
 634
 635         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 636         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
 637
 638         if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
 639                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
 640         {
 641                 destroy_reg_param(&reg_params[0]);
 642                 destroy_reg_param(&reg_params[1]);
 643                 destroy_reg_param(&reg_params[2]);
 644                 target_free_working_area(target, erase_check_algorithm);
 645                 return 0;
 646         }
 647
 648         *blank = buf_get_u32(reg_params[2].value, 0, 32);
 649
 650         destroy_reg_param(&reg_params[0]);
 651         destroy_reg_param(&reg_params[1]);
 652         destroy_reg_param(&reg_params[2]);
 653
 654         target_free_working_area(target, erase_check_algorithm);
 655
 656         return ERROR_OK;
 657 }