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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  12  *   oyvind.harboe@zylin.com                                               *
  13  *                                                                         *
  14  *   Copyright (C) 2018 by Liviu Ionescu                                   *
  15  *   <ilg@livius.net>                                                      *
  16  *                                                                         *
  17  *   This program is free software; you can redistribute it and/or modify  *
  18  *   it under the terms of the GNU General Public License as published by  *
  19  *   the Free Software Foundation; either version 2 of the License, or     *
  20  *   (at your option) any later version.                                   *
  21  *                                                                         *
  22  *   This program is distributed in the hope that it will be useful,       *
  23  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  24  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  25  *   GNU General Public License for more details.                          *
  26  *                                                                         *
  27  *   You should have received a copy of the GNU General Public License     *
  28  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  29  *                                                                         *
  30  *   ARMv7-M Architecture, Application Level Reference Manual              *
  31  *              ARM DDI 0405C (September 2008)                             *
  32  *                                                                         *
  33  ***************************************************************************/
  34
  35 #ifdef HAVE_CONFIG_H
  36 #include "config.h"
  37 #endif
  38
  39 #include "breakpoints.h"
  40 #include "armv7m.h"
  41 #include "algorithm.h"
  42 #include "register.h"
  43 #include "semihosting_common.h"
  44
  45 #if 0
  46 #define _DEBUG_INSTRUCTION_EXECUTION_
  47 #endif
  48
  49 static const char * const armv7m_exception_strings[] = {
  50         "", "Reset", "NMI", "HardFault",
  51         "MemManage", "BusFault", "UsageFault", "SecureFault",
  52         "RESERVED", "RESERVED", "RESERVED", "SVCall",
  53         "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  54 };
  55
  56 /* PSP is used in some thread modes */
  57 const int armv7m_psp_reg_map[ARMV7M_NUM_CORE_REGS] = {
  58         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
  59         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
  60         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
  61         ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
  62         ARMV7M_xPSR,
  63 };
  64
  65 /* MSP is used in handler and some thread modes */
  66 const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
  67         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
  68         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
  69         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
  70         ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
  71         ARMV7M_xPSR,
  72 };
  73
  74 /*
  75  * These registers are not memory-mapped.  The ARMv7-M profile includes
  76  * memory mapped registers too, such as for the NVIC (interrupt controller)
  77  * and SysTick (timer) modules; those can mostly be treated as peripherals.
  78  *
  79  * The ARMv6-M profile is almost identical in this respect, except that it
  80  * doesn't include basepri or faultmask registers.
  81  */
  82 static const struct {
  83         unsigned id;
  84         const char *name;
  85         unsigned bits;
  86         enum reg_type type;
  87         const char *group;
  88         const char *feature;
  89 } armv7m_regs[] = {
  90         { ARMV7M_R0, "r0", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
  91         { ARMV7M_R1, "r1", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
  92         { ARMV7M_R2, "r2", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
  93         { ARMV7M_R3, "r3", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
  94         { ARMV7M_R4, "r4", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
  95         { ARMV7M_R5, "r5", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
  96         { ARMV7M_R6, "r6", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
  97         { ARMV7M_R7, "r7", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
  98         { ARMV7M_R8, "r8", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
  99         { ARMV7M_R9, "r9", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
 100         { ARMV7M_R10, "r10", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
 101         { ARMV7M_R11, "r11", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
 102         { ARMV7M_R12, "r12", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
 103         { ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile" },
 104         { ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
 105         { ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile" },
 106         { ARMV7M_xPSR, "xPSR", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
 107
 108         { ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
 109         { ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
 110
 111         { ARMV7M_PRIMASK, "primask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
 112         { ARMV7M_BASEPRI, "basepri", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
 113         { ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
 114         { ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
 115
 116         { ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 117         { ARMV7M_D1, "d1", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 118         { ARMV7M_D2, "d2", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 119         { ARMV7M_D3, "d3", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 120         { ARMV7M_D4, "d4", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 121         { ARMV7M_D5, "d5", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 122         { ARMV7M_D6, "d6", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 123         { ARMV7M_D7, "d7", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 124         { ARMV7M_D8, "d8", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 125         { ARMV7M_D9, "d9", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 126         { ARMV7M_D10, "d10", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 127         { ARMV7M_D11, "d11", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 128         { ARMV7M_D12, "d12", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 129         { ARMV7M_D13, "d13", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 130         { ARMV7M_D14, "d14", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 131         { ARMV7M_D15, "d15", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
 132
 133         { ARMV7M_FPSCR, "fpscr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp" },
 134 };
 135
 136 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
 137
 138 /**
 139  * Restores target context using the cache of core registers set up
 140  * by armv7m_build_reg_cache(), calling optional core-specific hooks.
 141  */
 142 int armv7m_restore_context(struct target *target)
 143 {
 144         int i;
 145         struct armv7m_common *armv7m = target_to_armv7m(target);
 146         struct reg_cache *cache = armv7m->arm.core_cache;
 147
 148         LOG_DEBUG(" ");
 149
 150         if (armv7m->pre_restore_context)
 151                 armv7m->pre_restore_context(target);
 152
 153         for (i = cache->num_regs - 1; i >= 0; i--) {
 154                 if (cache->reg_list[i].dirty) {
 155                         armv7m->arm.write_core_reg(target, &cache->reg_list[i], i,
 156                                                    ARM_MODE_ANY, cache->reg_list[i].value);
 157                 }
 158         }
 159
 160         return ERROR_OK;
 161 }
 162
 163 /* Core state functions */
 164
 165 /**
 166  * Maps ISR number (from xPSR) to name.
 167  * Note that while names and meanings for the first sixteen are standardized
 168  * (with zero not a true exception), external interrupts are only numbered.
 169  * They are assigned by vendors, which generally assign different numbers to
 170  * peripherals (such as UART0 or a USB peripheral controller).
 171  */
 172 const char *armv7m_exception_string(int number)
 173 {
 174         static char enamebuf[32];
 175
 176         if ((number < 0) | (number > 511))
 177                 return "Invalid exception";
 178         if (number < 16)
 179                 return armv7m_exception_strings[number];
 180         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 181         return enamebuf;
 182 }
 183
 184 static int armv7m_get_core_reg(struct reg *reg)
 185 {
 186         int retval;
 187         struct arm_reg *armv7m_reg = reg->arch_info;
 188         struct target *target = armv7m_reg->target;
 189         struct arm *arm = target_to_arm(target);
 190
 191         if (target->state != TARGET_HALTED)
 192                 return ERROR_TARGET_NOT_HALTED;
 193
 194         retval = arm->read_core_reg(target, reg, reg->number, arm->core_mode);
 195
 196         return retval;
 197 }
 198
 199 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
 200 {
 201         struct arm_reg *armv7m_reg = reg->arch_info;
 202         struct target *target = armv7m_reg->target;
 203
 204         if (target->state != TARGET_HALTED)
 205                 return ERROR_TARGET_NOT_HALTED;
 206
 207         buf_cpy(buf, reg->value, reg->size);
 208         reg->dirty = true;
 209         reg->valid = true;
 210
 211         return ERROR_OK;
 212 }
 213
 214 static int armv7m_read_core_reg(struct target *target, struct reg *r,
 215         int num, enum arm_mode mode)
 216 {
 217         uint32_t reg_value;
 218         int retval;
 219         struct arm_reg *armv7m_core_reg;
 220         struct armv7m_common *armv7m = target_to_armv7m(target);
 221
 222         assert(num < (int)armv7m->arm.core_cache->num_regs);
 223
 224         armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
 225
 226         if ((armv7m_core_reg->num >= ARMV7M_D0) && (armv7m_core_reg->num <= ARMV7M_D15)) {
 227                 /* map D0..D15 to S0..S31 */
 228                 size_t regidx = ARMV7M_S0 + 2 * (armv7m_core_reg->num - ARMV7M_D0);
 229                 retval = armv7m->load_core_reg_u32(target, regidx, &reg_value);
 230                 if (retval != ERROR_OK)
 231                         return retval;
 232                 buf_set_u32(armv7m->arm.core_cache->reg_list[num].value,
 233                             0, 32, reg_value);
 234                 retval = armv7m->load_core_reg_u32(target, regidx + 1, &reg_value);
 235                 if (retval != ERROR_OK)
 236                         return retval;
 237                 buf_set_u32(armv7m->arm.core_cache->reg_list[num].value + 4,
 238                             0, 32, reg_value);
 239         } else {
 240                 retval = armv7m->load_core_reg_u32(target,
 241                                                    armv7m_core_reg->num, &reg_value);
 242                 if (retval != ERROR_OK)
 243                         return retval;
 244                 buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
 245         }
 246
 247         armv7m->arm.core_cache->reg_list[num].valid = true;
 248         armv7m->arm.core_cache->reg_list[num].dirty = false;
 249
 250         return retval;
 251 }
 252
 253 static int armv7m_write_core_reg(struct target *target, struct reg *r,
 254         int num, enum arm_mode mode, uint8_t *value)
 255 {
 256         int retval;
 257         struct arm_reg *armv7m_core_reg;
 258         struct armv7m_common *armv7m = target_to_armv7m(target);
 259
 260         assert(num < (int)armv7m->arm.core_cache->num_regs);
 261
 262         armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
 263
 264         if ((armv7m_core_reg->num >= ARMV7M_D0) && (armv7m_core_reg->num <= ARMV7M_D15)) {
 265                 /* map D0..D15 to S0..S31 */
 266                 size_t regidx = ARMV7M_S0 + 2 * (armv7m_core_reg->num - ARMV7M_D0);
 267
 268                 uint32_t t = buf_get_u32(value, 0, 32);
 269                 retval = armv7m->store_core_reg_u32(target, regidx, t);
 270                 if (retval != ERROR_OK)
 271                         goto out_error;
 272
 273                 t = buf_get_u32(value + 4, 0, 32);
 274                 retval = armv7m->store_core_reg_u32(target, regidx + 1, t);
 275                 if (retval != ERROR_OK)
 276                         goto out_error;
 277         } else {
 278                 uint32_t t = buf_get_u32(value, 0, 32);
 279
 280                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, t);
 281                 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->num, t);
 282                 if (retval != ERROR_OK)
 283                         goto out_error;
 284         }
 285
 286         armv7m->arm.core_cache->reg_list[num].valid = true;
 287         armv7m->arm.core_cache->reg_list[num].dirty = false;
 288
 289         return ERROR_OK;
 290
 291 out_error:
 292         LOG_ERROR("Error setting register");
 293         armv7m->arm.core_cache->reg_list[num].dirty = armv7m->arm.core_cache->reg_list[num].valid;
 294         return ERROR_JTAG_DEVICE_ERROR;
 295 }
 296
 297 /**
 298  * Returns generic ARM userspace registers to GDB.
 299  */
 300 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 301                 int *reg_list_size, enum target_register_class reg_class)
 302 {
 303         struct armv7m_common *armv7m = target_to_armv7m(target);
 304         int i, size;
 305
 306         if (reg_class == REG_CLASS_ALL)
 307                 size = armv7m->arm.core_cache->num_regs;
 308         else
 309                 size = ARMV7M_NUM_CORE_REGS;
 310
 311         *reg_list = malloc(sizeof(struct reg *) * size);
 312         if (*reg_list == NULL)
 313                 return ERROR_FAIL;
 314
 315         for (i = 0; i < size; i++)
 316                 (*reg_list)[i] = &armv7m->arm.core_cache->reg_list[i];
 317
 318         *reg_list_size = size;
 319
 320         return ERROR_OK;
 321 }
 322
 323 /** Runs a Thumb algorithm in the target. */
 324 int armv7m_run_algorithm(struct target *target,
 325         int num_mem_params, struct mem_param *mem_params,
 326         int num_reg_params, struct reg_param *reg_params,
 327         target_addr_t entry_point, target_addr_t exit_point,
 328         int timeout_ms, void *arch_info)
 329 {
 330         int retval;
 331
 332         retval = armv7m_start_algorithm(target,
 333                         num_mem_params, mem_params,
 334                         num_reg_params, reg_params,
 335                         entry_point, exit_point,
 336                         arch_info);
 337
 338         if (retval == ERROR_OK)
 339                 retval = armv7m_wait_algorithm(target,
 340                                 num_mem_params, mem_params,
 341                                 num_reg_params, reg_params,
 342                                 exit_point, timeout_ms,
 343                                 arch_info);
 344
 345         return retval;
 346 }
 347
 348 /** Starts a Thumb algorithm in the target. */
 349 int armv7m_start_algorithm(struct target *target,
 350         int num_mem_params, struct mem_param *mem_params,
 351         int num_reg_params, struct reg_param *reg_params,
 352         target_addr_t entry_point, target_addr_t exit_point,
 353         void *arch_info)
 354 {
 355         struct armv7m_common *armv7m = target_to_armv7m(target);
 356         struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
 357         enum arm_mode core_mode = armv7m->arm.core_mode;
 358         int retval = ERROR_OK;
 359
 360         /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
 361          * at the exit point */
 362
 363         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
 364                 LOG_ERROR("current target isn't an ARMV7M target");
 365                 return ERROR_TARGET_INVALID;
 366         }
 367
 368         if (target->state != TARGET_HALTED) {
 369                 LOG_WARNING("target not halted");
 370                 return ERROR_TARGET_NOT_HALTED;
 371         }
 372
 373         /* refresh core register cache
 374          * Not needed if core register cache is always consistent with target process state */
 375         for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
 376
 377                 armv7m_algorithm_info->context[i] = buf_get_u32(
 378                                 armv7m->arm.core_cache->reg_list[i].value,
 379                                 0,
 380                                 32);
 381         }
 382
 383         for (int i = 0; i < num_mem_params; i++) {
 384                 if (mem_params[i].direction == PARAM_IN)
 385                         continue;
 386                 retval = target_write_buffer(target, mem_params[i].address,
 387                                 mem_params[i].size,
 388                                 mem_params[i].value);
 389                 if (retval != ERROR_OK)
 390                         return retval;
 391         }
 392
 393         for (int i = 0; i < num_reg_params; i++) {
 394                 if (reg_params[i].direction == PARAM_IN)
 395                         continue;
 396
 397                 struct reg *reg =
 398                         register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, 0);
 399 /*              uint32_t regvalue; */
 400
 401                 if (!reg) {
 402                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 403                         return ERROR_COMMAND_SYNTAX_ERROR;
 404                 }
 405
 406                 if (reg->size != reg_params[i].size) {
 407                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
 408                                 reg_params[i].reg_name);
 409                         return ERROR_COMMAND_SYNTAX_ERROR;
 410                 }
 411
 412 /*              regvalue = buf_get_u32(reg_params[i].value, 0, 32); */
 413                 armv7m_set_core_reg(reg, reg_params[i].value);
 414         }
 415
 416         {
 417                 /*
 418                  * Ensure xPSR.T is set to avoid trying to run things in arm
 419                  * (non-thumb) mode, which armv7m does not support.
 420                  *
 421                  * We do this by setting the entirety of xPSR, which should
 422                  * remove all the unknowns about xPSR state.
 423                  *
 424                  * Because xPSR.T is populated on reset from the vector table,
 425                  * it might be 0 if the vector table has "bad" data in it.
 426                  */
 427                 struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
 428                 buf_set_u32(reg->value, 0, 32, 0x01000000);
 429                 reg->valid = true;
 430                 reg->dirty = true;
 431         }
 432
 433         if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY &&
 434                         armv7m_algorithm_info->core_mode != core_mode) {
 435
 436                 /* we cannot set ARM_MODE_HANDLER, so use ARM_MODE_THREAD instead */
 437                 if (armv7m_algorithm_info->core_mode == ARM_MODE_HANDLER) {
 438                         armv7m_algorithm_info->core_mode = ARM_MODE_THREAD;
 439                         LOG_INFO("ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead");
 440                 }
 441
 442                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 443                 buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
 444                         0, 1, armv7m_algorithm_info->core_mode);
 445                 armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
 446                 armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
 447         }
 448
 449         /* save previous core mode */
 450         armv7m_algorithm_info->core_mode = core_mode;
 451
 452         retval = target_resume(target, 0, entry_point, 1, 1);
 453
 454         return retval;
 455 }
 456
 457 /** Waits for an algorithm in the target. */
 458 int armv7m_wait_algorithm(struct target *target,
 459         int num_mem_params, struct mem_param *mem_params,
 460         int num_reg_params, struct reg_param *reg_params,
 461         target_addr_t exit_point, int timeout_ms,
 462         void *arch_info)
 463 {
 464         struct armv7m_common *armv7m = target_to_armv7m(target);
 465         struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
 466         int retval = ERROR_OK;
 467
 468         /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
 469          * at the exit point */
 470
 471         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
 472                 LOG_ERROR("current target isn't an ARMV7M target");
 473                 return ERROR_TARGET_INVALID;
 474         }
 475
 476         retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
 477         /* If the target fails to halt due to the breakpoint, force a halt */
 478         if (retval != ERROR_OK || target->state != TARGET_HALTED) {
 479                 retval = target_halt(target);
 480                 if (retval != ERROR_OK)
 481                         return retval;
 482                 retval = target_wait_state(target, TARGET_HALTED, 500);
 483                 if (retval != ERROR_OK)
 484                         return retval;
 485                 return ERROR_TARGET_TIMEOUT;
 486         }
 487
 488         if (exit_point) {
 489                 /* PC value has been cached in cortex_m_debug_entry() */
 490                 uint32_t pc = buf_get_u32(armv7m->arm.pc->value, 0, 32);
 491                 if (pc != exit_point) {
 492                         LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
 493                                           pc, exit_point);
 494                         return ERROR_TARGET_ALGO_EXIT;
 495                 }
 496         }
 497
 498         /* Read memory values to mem_params[] */
 499         for (int i = 0; i < num_mem_params; i++) {
 500                 if (mem_params[i].direction != PARAM_OUT) {
 501                         retval = target_read_buffer(target, mem_params[i].address,
 502                                         mem_params[i].size,
 503                                         mem_params[i].value);
 504                         if (retval != ERROR_OK)
 505                                 return retval;
 506                 }
 507         }
 508
 509         /* Copy core register values to reg_params[] */
 510         for (int i = 0; i < num_reg_params; i++) {
 511                 if (reg_params[i].direction != PARAM_OUT) {
 512                         struct reg *reg = register_get_by_name(armv7m->arm.core_cache,
 513                                         reg_params[i].reg_name,
 514                                         0);
 515
 516                         if (!reg) {
 517                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 518                                 return ERROR_COMMAND_SYNTAX_ERROR;
 519                         }
 520
 521                         if (reg->size != reg_params[i].size) {
 522                                 LOG_ERROR(
 523                                         "BUG: register '%s' size doesn't match reg_params[i].size",
 524                                         reg_params[i].reg_name);
 525                                 return ERROR_COMMAND_SYNTAX_ERROR;
 526                         }
 527
 528                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 529                 }
 530         }
 531
 532         for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) {
 533                 uint32_t regvalue;
 534                 regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32);
 535                 if (regvalue != armv7m_algorithm_info->context[i]) {
 536                         LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
 537                                         armv7m->arm.core_cache->reg_list[i].name,
 538                                 armv7m_algorithm_info->context[i]);
 539                         buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
 540                                 0, 32, armv7m_algorithm_info->context[i]);
 541                         armv7m->arm.core_cache->reg_list[i].valid = true;
 542                         armv7m->arm.core_cache->reg_list[i].dirty = true;
 543                 }
 544         }
 545
 546         /* restore previous core mode */
 547         if (armv7m_algorithm_info->core_mode != armv7m->arm.core_mode) {
 548                 LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 549                 buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
 550                         0, 1, armv7m_algorithm_info->core_mode);
 551                 armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
 552                 armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
 553         }
 554
 555         armv7m->arm.core_mode = armv7m_algorithm_info->core_mode;
 556
 557         return retval;
 558 }
 559
 560 /** Logs summary of ARMv7-M state for a halted target. */
 561 int armv7m_arch_state(struct target *target)
 562 {
 563         struct armv7m_common *armv7m = target_to_armv7m(target);
 564         struct arm *arm = &armv7m->arm;
 565         uint32_t ctrl, sp;
 566
 567         /* avoid filling log waiting for fileio reply */
 568         if (target->semihosting && target->semihosting->hit_fileio)
 569                 return ERROR_OK;
 570
 571         ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
 572         sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 573
 574         LOG_USER("target halted due to %s, current mode: %s %s\n"
 575                 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s",
 576                 debug_reason_name(target),
 577                 arm_mode_name(arm->core_mode),
 578                 armv7m_exception_string(armv7m->exception_number),
 579                 buf_get_u32(arm->cpsr->value, 0, 32),
 580                 buf_get_u32(arm->pc->value, 0, 32),
 581                 (ctrl & 0x02) ? 'p' : 'm',
 582                 sp,
 583                 (target->semihosting && target->semihosting->is_active) ? ", semihosting" : "",
 584                 (target->semihosting && target->semihosting->is_fileio) ? " fileio" : "");
 585
 586         return ERROR_OK;
 587 }
 588
 589 static const struct reg_arch_type armv7m_reg_type = {
 590         .get = armv7m_get_core_reg,
 591         .set = armv7m_set_core_reg,
 592 };
 593
 594 /** Builds cache of architecturally defined registers.  */
 595 struct reg_cache *armv7m_build_reg_cache(struct target *target)
 596 {
 597         struct armv7m_common *armv7m = target_to_armv7m(target);
 598         struct arm *arm = &armv7m->arm;
 599         int num_regs = ARMV7M_NUM_REGS;
 600         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 601         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 602         struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
 603         struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
 604         struct reg_feature *feature;
 605         int i;
 606
 607         /* Build the process context cache */
 608         cache->name = "arm v7m registers";
 609         cache->next = NULL;
 610         cache->reg_list = reg_list;
 611         cache->num_regs = num_regs;
 612         (*cache_p) = cache;
 613
 614         for (i = 0; i < num_regs; i++) {
 615                 arch_info[i].num = armv7m_regs[i].id;
 616                 arch_info[i].target = target;
 617                 arch_info[i].arm = arm;
 618
 619                 reg_list[i].name = armv7m_regs[i].name;
 620                 reg_list[i].size = armv7m_regs[i].bits;
 621                 size_t storage_size = DIV_ROUND_UP(armv7m_regs[i].bits, 8);
 622                 if (storage_size < 4)
 623                         storage_size = 4;
 624                 reg_list[i].value = calloc(1, storage_size);
 625                 reg_list[i].dirty = false;
 626                 reg_list[i].valid = false;
 627                 reg_list[i].type = &armv7m_reg_type;
 628                 reg_list[i].arch_info = &arch_info[i];
 629
 630                 reg_list[i].group = armv7m_regs[i].group;
 631                 reg_list[i].number = i;
 632                 reg_list[i].exist = true;
 633                 reg_list[i].caller_save = true; /* gdb defaults to true */
 634
 635                 feature = calloc(1, sizeof(struct reg_feature));
 636                 if (feature) {
 637                         feature->name = armv7m_regs[i].feature;
 638                         reg_list[i].feature = feature;
 639                 } else
 640                         LOG_ERROR("unable to allocate feature list");
 641
 642                 reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
 643                 if (reg_list[i].reg_data_type)
 644                         reg_list[i].reg_data_type->type = armv7m_regs[i].type;
 645                 else
 646                         LOG_ERROR("unable to allocate reg type list");
 647         }
 648
 649         arm->cpsr = reg_list + ARMV7M_xPSR;
 650         arm->pc = reg_list + ARMV7M_PC;
 651         arm->core_cache = cache;
 652
 653         return cache;
 654 }
 655
 656 void armv7m_free_reg_cache(struct target *target)
 657 {
 658         struct armv7m_common *armv7m = target_to_armv7m(target);
 659         struct arm *arm = &armv7m->arm;
 660         struct reg_cache *cache;
 661         struct reg *reg;
 662         unsigned int i;
 663
 664         cache = arm->core_cache;
 665
 666         if (!cache)
 667                 return;
 668
 669         for (i = 0; i < cache->num_regs; i++) {
 670                 reg = &cache->reg_list[i];
 671
 672                 free(reg->feature);
 673                 free(reg->reg_data_type);
 674                 free(reg->value);
 675         }
 676
 677         free(cache->reg_list[0].arch_info);
 678         free(cache->reg_list);
 679         free(cache);
 680
 681         arm->core_cache = NULL;
 682 }
 683
 684 static int armv7m_setup_semihosting(struct target *target, int enable)
 685 {
 686         /* nothing todo for armv7m */
 687         return ERROR_OK;
 688 }
 689
 690 /** Sets up target as a generic ARMv7-M core */
 691 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
 692 {
 693         struct arm *arm = &armv7m->arm;
 694
 695         armv7m->common_magic = ARMV7M_COMMON_MAGIC;
 696         armv7m->fp_feature = FP_NONE;
 697         armv7m->trace_config.trace_bus_id = 1;
 698         /* Enable stimulus port #0 by default */
 699         armv7m->trace_config.itm_ter[0] = 1;
 700
 701         arm->core_type = ARM_CORE_TYPE_M_PROFILE;
 702         arm->arch_info = armv7m;
 703         arm->setup_semihosting = armv7m_setup_semihosting;
 704
 705         arm->read_core_reg = armv7m_read_core_reg;
 706         arm->write_core_reg = armv7m_write_core_reg;
 707
 708         return arm_init_arch_info(target, arm);
 709 }
 710
 711 /** Generates a CRC32 checksum of a memory region. */
 712 int armv7m_checksum_memory(struct target *target,
 713         target_addr_t address, uint32_t count, uint32_t *checksum)
 714 {
 715         struct working_area *crc_algorithm;
 716         struct armv7m_algorithm armv7m_info;
 717         struct reg_param reg_params[2];
 718         int retval;
 719
 720         static const uint8_t cortex_m_crc_code[] = {
 721 #include "../../contrib/loaders/checksum/armv7m_crc.inc"
 722         };
 723
 724         retval = target_alloc_working_area(target, sizeof(cortex_m_crc_code), &crc_algorithm);
 725         if (retval != ERROR_OK)
 726                 return retval;
 727
 728         retval = target_write_buffer(target, crc_algorithm->address,
 729                         sizeof(cortex_m_crc_code), (uint8_t *)cortex_m_crc_code);
 730         if (retval != ERROR_OK)
 731                 goto cleanup;
 732
 733         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 734         armv7m_info.core_mode = ARM_MODE_THREAD;
 735
 736         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 737         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 738
 739         buf_set_u32(reg_params[0].value, 0, 32, address);
 740         buf_set_u32(reg_params[1].value, 0, 32, count);
 741
 742         int timeout = 20000 * (1 + (count / (1024 * 1024)));
 743
 744         retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
 745                         crc_algorithm->address + (sizeof(cortex_m_crc_code) - 6),
 746                         timeout, &armv7m_info);
 747
 748         if (retval == ERROR_OK)
 749                 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 750         else
 751                 LOG_ERROR("error executing cortex_m crc algorithm");
 752
 753         destroy_reg_param(&reg_params[0]);
 754         destroy_reg_param(&reg_params[1]);
 755
 756 cleanup:
 757         target_free_working_area(target, crc_algorithm);
 758
 759         return retval;
 760 }
 761
 762 /** Checks an array of memory regions whether they are erased. */
 763 int armv7m_blank_check_memory(struct target *target,
 764         struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
 765 {
 766         struct working_area *erase_check_algorithm;
 767         struct working_area *erase_check_params;
 768         struct reg_param reg_params[2];
 769         struct armv7m_algorithm armv7m_info;
 770         int retval;
 771
 772         static bool timed_out;
 773
 774         static const uint8_t erase_check_code[] = {
 775 #include "../../contrib/loaders/erase_check/armv7m_erase_check.inc"
 776         };
 777
 778         const uint32_t code_size = sizeof(erase_check_code);
 779
 780         /* make sure we have a working area */
 781         if (target_alloc_working_area(target, code_size,
 782                 &erase_check_algorithm) != ERROR_OK)
 783                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 784
 785         retval = target_write_buffer(target, erase_check_algorithm->address,
 786                         code_size, erase_check_code);
 787         if (retval != ERROR_OK)
 788                 goto cleanup1;
 789
 790         /* prepare blocks array for algo */
 791         struct algo_block {
 792                 union {
 793                         uint32_t size;
 794                         uint32_t result;
 795                 };
 796                 uint32_t address;
 797         };
 798
 799         uint32_t avail = target_get_working_area_avail(target);
 800         int blocks_to_check = avail / sizeof(struct algo_block) - 1;
 801         if (num_blocks < blocks_to_check)
 802                 blocks_to_check = num_blocks;
 803
 804         struct algo_block *params = malloc((blocks_to_check+1)*sizeof(struct algo_block));
 805         if (params == NULL) {
 806                 retval = ERROR_FAIL;
 807                 goto cleanup1;
 808         }
 809
 810         int i;
 811         uint32_t total_size = 0;
 812         for (i = 0; i < blocks_to_check; i++) {
 813                 total_size += blocks[i].size;
 814                 target_buffer_set_u32(target, (uint8_t *)&(params[i].size),
 815                                                 blocks[i].size / sizeof(uint32_t));
 816                 target_buffer_set_u32(target, (uint8_t *)&(params[i].address),
 817                                                 blocks[i].address);
 818         }
 819         target_buffer_set_u32(target, (uint8_t *)&(params[blocks_to_check].size), 0);
 820
 821         uint32_t param_size = (blocks_to_check + 1) * sizeof(struct algo_block);
 822         if (target_alloc_working_area(target, param_size,
 823                         &erase_check_params) != ERROR_OK) {
 824                 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 825                 goto cleanup2;
 826         }
 827
 828         retval = target_write_buffer(target, erase_check_params->address,
 829                                 param_size, (uint8_t *)params);
 830         if (retval != ERROR_OK)
 831                 goto cleanup3;
 832
 833         uint32_t erased_word = erased_value | (erased_value << 8)
 834                                | (erased_value << 16) | (erased_value << 24);
 835
 836         LOG_DEBUG("Starting erase check of %d blocks, parameters@"
 837                  TARGET_ADDR_FMT, blocks_to_check, erase_check_params->address);
 838
 839         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 840         armv7m_info.core_mode = ARM_MODE_THREAD;
 841
 842         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 843         buf_set_u32(reg_params[0].value, 0, 32, erase_check_params->address);
 844
 845         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 846         buf_set_u32(reg_params[1].value, 0, 32, erased_word);
 847
 848         /* assume CPU clk at least 1 MHz */
 849         int timeout = (timed_out ? 30000 : 2000) + total_size * 3 / 1000;
 850
 851         retval = target_run_algorithm(target,
 852                                 0, NULL,
 853                                 ARRAY_SIZE(reg_params), reg_params,
 854                                 erase_check_algorithm->address,
 855                                 erase_check_algorithm->address + (code_size - 2),
 856                                 timeout,
 857                                 &armv7m_info);
 858
 859         timed_out = retval == ERROR_TARGET_TIMEOUT;
 860         if (retval != ERROR_OK && !timed_out)
 861                 goto cleanup4;
 862
 863         retval = target_read_buffer(target, erase_check_params->address,
 864                                 param_size, (uint8_t *)params);
 865         if (retval != ERROR_OK)
 866                 goto cleanup4;
 867
 868         for (i = 0; i < blocks_to_check; i++) {
 869                 uint32_t result = target_buffer_get_u32(target,
 870                                         (uint8_t *)&(params[i].result));
 871                 if (result != 0 && result != 1)
 872                         break;
 873
 874                 blocks[i].result = result;
 875         }
 876         if (i && timed_out)
 877                 LOG_INFO("Slow CPU clock: %d blocks checked, %d remain. Continuing...", i, num_blocks-i);
 878
 879         retval = i;             /* return number of blocks really checked */
 880
 881 cleanup4:
 882         destroy_reg_param(&reg_params[0]);
 883         destroy_reg_param(&reg_params[1]);
 884
 885 cleanup3:
 886         target_free_working_area(target, erase_check_params);
 887 cleanup2:
 888         free(params);
 889 cleanup1:
 890         target_free_working_area(target, erase_check_algorithm);
 891
 892         return retval;
 893 }
 894
 895 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
 896 {
 897         struct armv7m_common *armv7m = target_to_armv7m(target);
 898         struct reg *r = armv7m->arm.pc;
 899         bool result = false;
 900
 901
 902         /* if we halted last time due to a bkpt instruction
 903          * then we have to manually step over it, otherwise
 904          * the core will break again */
 905
 906         if (target->debug_reason == DBG_REASON_BREAKPOINT) {
 907                 uint16_t op;
 908                 uint32_t pc = buf_get_u32(r->value, 0, 32);
 909
 910                 pc &= ~1;
 911                 if (target_read_u16(target, pc, &op) == ERROR_OK) {
 912                         if ((op & 0xFF00) == 0xBE00) {
 913                                 pc = buf_get_u32(r->value, 0, 32) + 2;
 914                                 buf_set_u32(r->value, 0, 32, pc);
 915                                 r->dirty = true;
 916                                 r->valid = true;
 917                                 result = true;
 918                                 LOG_DEBUG("Skipping over BKPT instruction");
 919                         }
 920                 }
 921         }
 922
 923         if (inst_found)
 924                 *inst_found = result;
 925
 926         return ERROR_OK;
 927 }
 928
 929 const struct command_registration armv7m_command_handlers[] = {
 930         {
 931                 .chain = arm_command_handlers,
 932         },
 933         COMMAND_REGISTRATION_DONE
 934 };