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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  12  *   oyvind.harboe@zylin.com                                               *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  *                                                                         *
  29  *      ARMv7-M Architecture, Application Level Reference Manual           *
  30  *              ARM DDI 0405C (September 2008)                             *
  31  *                                                                         *
  32  ***************************************************************************/
  33 #ifdef HAVE_CONFIG_H
  34 #include "config.h"
  35 #endif
  36
  37 #include "armv7m.h"
  38
  39 #define ARRAY_SIZE(x)   ((int)(sizeof(x)/sizeof((x)[0])))
  40
  41
  42 #if 0
  43 #define _DEBUG_INSTRUCTION_EXECUTION_
  44 #endif
  45
  46 char* armv7m_mode_strings[] =
  47 {
  48         "Thread", "Thread (User)", "Handler",
  49 };
  50
  51 static char *armv7m_exception_strings[] =
  52 {
  53         "", "Reset", "NMI", "HardFault",
  54         "MemManage", "BusFault", "UsageFault", "RESERVED",
  55         "RESERVED", "RESERVED", "RESERVED", "SVCall",
  56         "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  57 };
  58
  59 uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  60
  61 reg_t armv7m_gdb_dummy_fp_reg =
  62 {
  63         "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  64 };
  65
  66 uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
  67
  68 reg_t armv7m_gdb_dummy_fps_reg =
  69 {
  70         "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
  71 };
  72
  73 #ifdef ARMV7_GDB_HACKS
  74 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  75
  76 reg_t armv7m_gdb_dummy_cpsr_reg =
  77 {
  78         "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
  79 };
  80 #endif
  81
  82 /*
  83  * These registers are not memory-mapped.  The ARMv7-M profile includes
  84  * memory mapped registers too, such as for the NVIC (interrupt controller)
  85  * and SysTick (timer) modules; those can mostly be treated as peripherals.
  86  */
  87 static const struct {
  88         unsigned id;
  89         char *name;
  90 } armv7m_regs[] = {
  91         { ARMV7M_R0, "r0" },
  92         { ARMV7M_R1, "r1" },
  93         { ARMV7M_R2, "r2" },
  94         { ARMV7M_R3, "r3" },
  95
  96         { ARMV7M_R4, "r4" },
  97         { ARMV7M_R5, "r5" },
  98         { ARMV7M_R6, "r6" },
  99         { ARMV7M_R7, "r7" },
 100
 101         { ARMV7M_R8, "r8" },
 102         { ARMV7M_R9, "r9" },
 103         { ARMV7M_R10, "r10" },
 104         { ARMV7M_R11, "r11" },
 105
 106         { ARMV7M_R12, "r12" },
 107         { ARMV7M_R13, "sp" },
 108         { ARMV7M_R14, "lr" },
 109         { ARMV7M_PC, "pc" },
 110
 111         { ARMV7M_xPSR, "xPSR" },
 112         { ARMV7M_MSP, "msp" },
 113         { ARMV7M_PSP, "psp" },
 114
 115         { ARMV7M_PRIMASK, "primask" },
 116         { ARMV7M_BASEPRI, "basepri" },
 117         { ARMV7M_FAULTMASK, "faultmask" },
 118         { ARMV7M_CONTROL, "control" },
 119 };
 120
 121 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
 122
 123 int armv7m_core_reg_arch_type = -1;
 124 int armv7m_dummy_core_reg_arch_type = -1;
 125
 126 int armv7m_restore_context(target_t *target)
 127 {
 128         int i;
 129
 130         /* get pointers to arch-specific information */
 131         armv7m_common_t *armv7m = target->arch_info;
 132
 133         LOG_DEBUG(" ");
 134
 135         if (armv7m->pre_restore_context)
 136                 armv7m->pre_restore_context(target);
 137
 138         for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
 139         {
 140                 if (armv7m->core_cache->reg_list[i].dirty)
 141                 {
 142                         armv7m->write_core_reg(target, i);
 143                 }
 144         }
 145
 146         if (armv7m->post_restore_context)
 147                 armv7m->post_restore_context(target);
 148
 149         return ERROR_OK;
 150 }
 151
 152 /* Core state functions */
 153 char *armv7m_exception_string(int number)
 154 {
 155         static char enamebuf[32];
 156
 157         if ((number < 0) | (number > 511))
 158                 return "Invalid exception";
 159         if (number < 16)
 160                 return armv7m_exception_strings[number];
 161         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 162         return enamebuf;
 163 }
 164
 165 int armv7m_get_core_reg(reg_t *reg)
 166 {
 167         int retval;
 168         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 169         target_t *target = armv7m_reg->target;
 170         armv7m_common_t *armv7m_target = target->arch_info;
 171
 172         if (target->state != TARGET_HALTED)
 173         {
 174                 return ERROR_TARGET_NOT_HALTED;
 175         }
 176
 177         retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
 178
 179         return retval;
 180 }
 181
 182 int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
 183 {
 184         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 185         target_t *target = armv7m_reg->target;
 186         uint32_t value = buf_get_u32(buf, 0, 32);
 187
 188         if (target->state != TARGET_HALTED)
 189         {
 190                 return ERROR_TARGET_NOT_HALTED;
 191         }
 192
 193         buf_set_u32(reg->value, 0, 32, value);
 194         reg->dirty = 1;
 195         reg->valid = 1;
 196
 197         return ERROR_OK;
 198 }
 199
 200 int armv7m_read_core_reg(struct target_s *target, int num)
 201 {
 202         uint32_t reg_value;
 203         int retval;
 204         armv7m_core_reg_t * armv7m_core_reg;
 205
 206         /* get pointers to arch-specific information */
 207         armv7m_common_t *armv7m = target->arch_info;
 208
 209         if ((num < 0) || (num >= ARMV7M_NUM_REGS))
 210                 return ERROR_INVALID_ARGUMENTS;
 211
 212         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 213         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 214         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 215         armv7m->core_cache->reg_list[num].valid = 1;
 216         armv7m->core_cache->reg_list[num].dirty = 0;
 217
 218         return retval;
 219 }
 220
 221 int armv7m_write_core_reg(struct target_s *target, int num)
 222 {
 223         int retval;
 224         uint32_t reg_value;
 225         armv7m_core_reg_t *armv7m_core_reg;
 226
 227         /* get pointers to arch-specific information */
 228         armv7m_common_t *armv7m = target->arch_info;
 229
 230         if ((num < 0) || (num >= ARMV7M_NUM_REGS))
 231                 return ERROR_INVALID_ARGUMENTS;
 232
 233         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 234         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 235         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 236         if (retval != ERROR_OK)
 237         {
 238                 LOG_ERROR("JTAG failure");
 239                 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 240                 return ERROR_JTAG_DEVICE_ERROR;
 241         }
 242         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 243         armv7m->core_cache->reg_list[num].valid = 1;
 244         armv7m->core_cache->reg_list[num].dirty = 0;
 245
 246         return ERROR_OK;
 247 }
 248
 249 int armv7m_invalidate_core_regs(target_t *target)
 250 {
 251         /* get pointers to arch-specific information */
 252         armv7m_common_t *armv7m = target->arch_info;
 253         int i;
 254
 255         for (i = 0; i < armv7m->core_cache->num_regs; i++)
 256         {
 257                 armv7m->core_cache->reg_list[i].valid = 0;
 258                 armv7m->core_cache->reg_list[i].dirty = 0;
 259         }
 260
 261         return ERROR_OK;
 262 }
 263
 264 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
 265 {
 266         /* get pointers to arch-specific information */
 267         armv7m_common_t *armv7m = target->arch_info;
 268         int i;
 269
 270         *reg_list_size = 26;
 271         *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
 272
 273         /*
 274          * GDB register packet format for ARM:
 275          *  - the first 16 registers are r0..r15
 276          *  - (obsolete) 8 FPA registers
 277          *  - (obsolete) FPA status
 278          *  - CPSR
 279          */
 280         for (i = 0; i < 16; i++)
 281         {
 282                 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 283         }
 284
 285         for (i = 16; i < 24; i++)
 286         {
 287                 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
 288         }
 289
 290         (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
 291
 292 #ifdef ARMV7_GDB_HACKS
 293         /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
 294         (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
 295
 296         /* ARMV7M is always in thumb mode, try to make GDB understand this
 297          * if it does not support this arch */
 298         *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
 299 #else
 300         (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 301 #endif
 302
 303         return ERROR_OK;
 304 }
 305
 306 /* run to exit point. return error if exit point was not reached. */
 307 static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, armv7m_common_t *armv7m)
 308 {
 309         uint32_t pc;
 310         int retval;
 311         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 312          * sequence to write register values to the processor and the read them back */
 313         if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
 314         {
 315                 return retval;
 316         }
 317
 318         retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
 319         /* If the target fails to halt due to the breakpoint, force a halt */
 320         if (retval != ERROR_OK || target->state != TARGET_HALTED)
 321         {
 322                 if ((retval = target_halt(target)) != ERROR_OK)
 323                         return retval;
 324                 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
 325                 {
 326                         return retval;
 327                 }
 328                 return ERROR_TARGET_TIMEOUT;
 329         }
 330
 331         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 332         if (pc != exit_point)
 333         {
 334                 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
 335                 return ERROR_TARGET_TIMEOUT;
 336         }
 337
 338         return ERROR_OK;
 339 }
 340
 341 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
 342 {
 343         /* get pointers to arch-specific information */
 344         armv7m_common_t *armv7m = target->arch_info;
 345         armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
 346         enum armv7m_mode core_mode = armv7m->core_mode;
 347         int retval = ERROR_OK;
 348         int i;
 349         uint32_t context[ARMV7M_NUM_REGS];
 350
 351         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 352         {
 353                 LOG_ERROR("current target isn't an ARMV7M target");
 354                 return ERROR_TARGET_INVALID;
 355         }
 356
 357         if (target->state != TARGET_HALTED)
 358         {
 359                 LOG_WARNING("target not halted");
 360                 return ERROR_TARGET_NOT_HALTED;
 361         }
 362
 363         /* refresh core register cache */
 364         /* Not needed if core register cache is always consistent with target process state */
 365         for (i = 0; i < ARMV7M_NUM_REGS; i++)
 366         {
 367                 if (!armv7m->core_cache->reg_list[i].valid)
 368                         armv7m->read_core_reg(target, i);
 369                 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 370         }
 371
 372         for (i = 0; i < num_mem_params; i++)
 373         {
 374                 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 375                         return retval;
 376         }
 377
 378         for (i = 0; i < num_reg_params; i++)
 379         {
 380                 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 381 //              uint32_t regvalue;
 382
 383                 if (!reg)
 384                 {
 385                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 386                         exit(-1);
 387                 }
 388
 389                 if (reg->size != reg_params[i].size)
 390                 {
 391                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 392                         exit(-1);
 393                 }
 394
 395 //              regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 396                 armv7m_set_core_reg(reg, reg_params[i].value);
 397         }
 398
 399         if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
 400         {
 401                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 402                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
 403                                 0, 1, armv7m_algorithm_info->core_mode);
 404                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
 405                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 406         }
 407
 408         /* ARMV7M always runs in Thumb state */
 409         if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
 410         {
 411                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
 412                 return ERROR_TARGET_FAILURE;
 413         }
 414
 415         retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
 416
 417         breakpoint_remove(target, exit_point);
 418
 419         if (retval != ERROR_OK)
 420         {
 421                 return retval;
 422         }
 423
 424         /* Read memory values to mem_params[] */
 425         for (i = 0; i < num_mem_params; i++)
 426         {
 427                 if (mem_params[i].direction != PARAM_OUT)
 428                         if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 429                         {
 430                                 return retval;
 431                         }
 432         }
 433
 434         /* Copy core register values to reg_params[] */
 435         for (i = 0; i < num_reg_params; i++)
 436         {
 437                 if (reg_params[i].direction != PARAM_OUT)
 438                 {
 439                         reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 440
 441                         if (!reg)
 442                         {
 443                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 444                                 exit(-1);
 445                         }
 446
 447                         if (reg->size != reg_params[i].size)
 448                         {
 449                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 450                                 exit(-1);
 451                         }
 452
 453                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 454                 }
 455         }
 456
 457         for (i = ARMV7M_NUM_REGS; i >= 0; i--)
 458         {
 459                 uint32_t regvalue;
 460                 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 461                 if (regvalue != context[i])
 462                 {
 463                         LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
 464                                 armv7m->core_cache->reg_list[i].name, context[i]);
 465                         buf_set_u32(armv7m->core_cache->reg_list[i].value,
 466                                         0, 32, context[i]);
 467                         armv7m->core_cache->reg_list[i].valid = 1;
 468                         armv7m->core_cache->reg_list[i].dirty = 1;
 469                 }
 470         }
 471
 472         armv7m->core_mode = core_mode;
 473
 474         return retval;
 475 }
 476
 477 int armv7m_arch_state(struct target_s *target)
 478 {
 479         /* get pointers to arch-specific information */
 480         armv7m_common_t *armv7m = target->arch_info;
 481
 482         LOG_USER("target halted due to %s, current mode: %s %s\n"
 483                 "xPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32,
 484                  Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
 485                 armv7m_mode_strings[armv7m->core_mode],
 486                 armv7m_exception_string(armv7m->exception_number),
 487                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 488                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32));
 489
 490         return ERROR_OK;
 491 }
 492
 493 reg_cache_t *armv7m_build_reg_cache(target_t *target)
 494 {
 495         /* get pointers to arch-specific information */
 496         armv7m_common_t *armv7m = target->arch_info;
 497
 498         int num_regs = ARMV7M_NUM_REGS;
 499         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 500         reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 501         reg_t *reg_list = calloc(num_regs, sizeof(reg_t));
 502         armv7m_core_reg_t *arch_info = calloc(num_regs, sizeof(armv7m_core_reg_t));
 503         int i;
 504
 505         if (armv7m_core_reg_arch_type == -1)
 506         {
 507                 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
 508         }
 509
 510         register_init_dummy(&armv7m_gdb_dummy_fps_reg);
 511 #ifdef ARMV7_GDB_HACKS
 512         register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
 513 #endif
 514         register_init_dummy(&armv7m_gdb_dummy_fp_reg);
 515
 516         /* Build the process context cache */
 517         cache->name = "arm v7m registers";
 518         cache->next = NULL;
 519         cache->reg_list = reg_list;
 520         cache->num_regs = num_regs;
 521         (*cache_p) = cache;
 522         armv7m->core_cache = cache;
 523
 524         for (i = 0; i < num_regs; i++)
 525         {
 526                 arch_info[i].num = armv7m_regs[i].id;
 527                 arch_info[i].target = target;
 528                 arch_info[i].armv7m_common = armv7m;
 529                 reg_list[i].name = armv7m_regs[i].name;
 530                 reg_list[i].size = 32;
 531                 reg_list[i].value = calloc(1, 4);
 532                 reg_list[i].dirty = 0;
 533                 reg_list[i].valid = 0;
 534                 reg_list[i].bitfield_desc = NULL;
 535                 reg_list[i].num_bitfields = 0;
 536                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 537                 reg_list[i].arch_info = &arch_info[i];
 538         }
 539
 540         return cache;
 541 }
 542
 543 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 544 {
 545         armv7m_build_reg_cache(target);
 546
 547         return ERROR_OK;
 548 }
 549
 550 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
 551 {
 552         /* register arch-specific functions */
 553
 554         target->arch_info = armv7m;
 555         armv7m->read_core_reg = armv7m_read_core_reg;
 556         armv7m->write_core_reg = armv7m_write_core_reg;
 557
 558         return ERROR_OK;
 559 }
 560
 561 int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
 562 {
 563         working_area_t *crc_algorithm;
 564         armv7m_algorithm_t armv7m_info;
 565         reg_param_t reg_params[2];
 566         int retval;
 567
 568         uint16_t cortex_m3_crc_code[] = {
 569                 0x4602,                                 /* mov  r2, r0 */
 570                 0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
 571                 0x460B,                                 /* mov  r3, r1 */
 572                 0xF04F, 0x0400,                 /* mov  r4, #0 */
 573                 0xE013,                                 /* b    ncomp */
 574                                                                 /* nbyte: */
 575                 0x5D11,                                 /* ldrb r1, [r2, r4] */
 576                 0xF8DF, 0x7028,                 /* ldr          r7, CRC32XOR */
 577                 0xEA80, 0x6001,                 /* eor          r0, r0, r1, asl #24 */
 578
 579                 0xF04F, 0x0500,                 /* mov          r5, #0 */
 580                                                                 /* loop: */
 581                 0x2800,                                 /* cmp          r0, #0 */
 582                 0xEA4F, 0x0640,                 /* mov          r6, r0, asl #1 */
 583                 0xF105, 0x0501,                 /* add          r5, r5, #1 */
 584                 0x4630,                                 /* mov          r0, r6 */
 585                 0xBFB8,                                 /* it           lt */
 586                 0xEA86, 0x0007,                 /* eor          r0, r6, r7 */
 587                 0x2D08,                                 /* cmp          r5, #8 */
 588                 0xD1F4,                                 /* bne          loop */
 589
 590                 0xF104, 0x0401,                 /* add  r4, r4, #1 */
 591                                                                 /* ncomp: */
 592                 0x429C,                                 /* cmp  r4, r3 */
 593                 0xD1E9,                                 /* bne  nbyte */
 594                                                                 /* end: */
 595                 0xE7FE,                                 /* b    end */
 596                 0x1DB7, 0x04C1                  /* CRC32XOR:    .word 0x04C11DB7 */
 597         };
 598
 599         uint32_t i;
 600
 601         if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
 602         {
 603                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 604         }
 605
 606         /* convert flash writing code into a buffer in target endianness */
 607         for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
 608                 if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
 609                 {
 610                         return retval;
 611                 }
 612
 613         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 614         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 615
 616         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 617         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 618
 619         buf_set_u32(reg_params[0].value, 0, 32, address);
 620         buf_set_u32(reg_params[1].value, 0, 32, count);
 621
 622         if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
 623                 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
 624         {
 625                 LOG_ERROR("error executing cortex_m3 crc algorithm");
 626                 destroy_reg_param(&reg_params[0]);
 627                 destroy_reg_param(&reg_params[1]);
 628                 target_free_working_area(target, crc_algorithm);
 629                 return retval;
 630         }
 631
 632         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 633
 634         destroy_reg_param(&reg_params[0]);
 635         destroy_reg_param(&reg_params[1]);
 636
 637         target_free_working_area(target, crc_algorithm);
 638
 639         return ERROR_OK;
 640 }
 641
 642 int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
 643 {
 644         working_area_t *erase_check_algorithm;
 645         reg_param_t reg_params[3];
 646         armv7m_algorithm_t armv7m_info;
 647         int retval;
 648         uint32_t i;
 649
 650         uint16_t erase_check_code[] =
 651         {
 652                                                         /* loop: */
 653                 0xF810, 0x3B01,         /* ldrb         r3, [r0], #1 */
 654                 0xEA02, 0x0203,         /* and  r2, r2, r3 */
 655                 0x3901,                         /* subs         r1, r1, #1 */
 656                 0xD1F9,                         /* bne          loop */
 657                                                         /* end: */
 658                 0xE7FE,                         /* b            end */
 659         };
 660
 661         /* make sure we have a working area */
 662         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
 663         {
 664                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 665         }
 666
 667         /* convert flash writing code into a buffer in target endianness */
 668         for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
 669                 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
 670
 671         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 672         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 673
 674         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 675         buf_set_u32(reg_params[0].value, 0, 32, address);
 676
 677         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 678         buf_set_u32(reg_params[1].value, 0, 32, count);
 679
 680         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 681         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
 682
 683         if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 684                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
 685         {
 686                 destroy_reg_param(&reg_params[0]);
 687                 destroy_reg_param(&reg_params[1]);
 688                 destroy_reg_param(&reg_params[2]);
 689                 target_free_working_area(target, erase_check_algorithm);
 690                 return 0;
 691         }
 692
 693         *blank = buf_get_u32(reg_params[2].value, 0, 32);
 694
 695         destroy_reg_param(&reg_params[0]);
 696         destroy_reg_param(&reg_params[1]);
 697         destroy_reg_param(&reg_params[2]);
 698
 699         target_free_working_area(target, erase_check_algorithm);
 700
 701         return ERROR_OK;
 702 }
 703
 704 /*
 705  * Return the debug ap baseaddress in hexadecimal;
 706  * no extra output to simplify script processing
 707  */
 708 static int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx,
 709                 char *cmd, char **args, int argc)
 710 {
 711         target_t *target = get_current_target(cmd_ctx);
 712         armv7m_common_t *armv7m = target->arch_info;
 713         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 714         uint32_t apsel, apselsave, baseaddr;
 715         int retval;
 716
 717         apsel = swjdp->apsel;
 718         apselsave = swjdp->apsel;
 719         if (argc > 0)
 720         {
 721                 apsel = strtoul(args[0], NULL, 0);
 722         }
 723         if (apselsave != apsel)
 724         {
 725                 dap_ap_select(swjdp, apsel);
 726         }
 727
 728         dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
 729         retval = swjdp_transaction_endcheck(swjdp);
 730         command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr);
 731
 732         if (apselsave != apsel)
 733         {
 734                 dap_ap_select(swjdp, apselsave);
 735         }
 736
 737         return retval;
 738 }
 739
 740
 741 /*
 742  * Return the debug ap id in hexadecimal;
 743  * no extra output to simplify script processing
 744  */
 745 extern int handle_dap_apid_command(struct command_context_s *cmd_ctx,
 746                 char *cmd, char **args, int argc)
 747 {
 748         target_t *target = get_current_target(cmd_ctx);
 749         armv7m_common_t *armv7m = target->arch_info;
 750         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 751
 752         return dap_apid_command(cmd_ctx, swjdp, args, argc);
 753 }
 754
 755 static int handle_dap_apsel_command(struct command_context_s *cmd_ctx,
 756                 char *cmd, char **args, int argc)
 757 {
 758         target_t *target = get_current_target(cmd_ctx);
 759         armv7m_common_t *armv7m = target->arch_info;
 760         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 761
 762         return dap_apsel_command(cmd_ctx, swjdp, args, argc);
 763 }
 764
 765 static int handle_dap_memaccess_command(struct command_context_s *cmd_ctx,
 766                 char *cmd, char **args, int argc)
 767 {
 768         target_t *target = get_current_target(cmd_ctx);
 769         armv7m_common_t *armv7m = target->arch_info;
 770         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 771
 772         return dap_memaccess_command(cmd_ctx, swjdp, args, argc);
 773 }
 774
 775
 776 static int handle_dap_info_command(struct command_context_s *cmd_ctx,
 777                 char *cmd, char **args, int argc)
 778 {
 779         target_t *target = get_current_target(cmd_ctx);
 780         armv7m_common_t *armv7m = target->arch_info;
 781         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 782         uint32_t apsel;
 783
 784         apsel =  swjdp->apsel;
 785         if (argc > 0)
 786                 apsel = strtoul(args[0], NULL, 0);
 787
 788         return dap_info_command(cmd_ctx, swjdp, apsel);
 789 }
 790
 791 int armv7m_register_commands(struct command_context_s *cmd_ctx)
 792 {
 793         command_t *arm_adi_v5_dap_cmd;
 794
 795         arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
 796                         NULL, COMMAND_ANY,
 797                         "cortex dap specific commands");
 798
 799         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info",
 800                         handle_dap_info_command, COMMAND_EXEC,
 801                         "Displays dap info for ap [num],"
 802                         "default currently selected AP");
 803         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel",
 804                         handle_dap_apsel_command, COMMAND_EXEC,
 805                         "Select a different AP [num] (default 0)");
 806         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid",
 807                         handle_dap_apid_command, COMMAND_EXEC,
 808                         "Displays id reg from AP [num], "
 809                         "default currently selected AP");
 810         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr",
 811                         handle_dap_baseaddr_command, COMMAND_EXEC,
 812                         "Displays debug base address from AP [num],"
 813                         "default currently selected AP");
 814         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess",
 815                         handle_dap_memaccess_command, COMMAND_EXEC,
 816                         "set/get number of extra tck for mem-ap "
 817                         "memory bus access [0-255]");
 818
 819         return ERROR_OK;
 820 }