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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2006 by Magnus Lundin                                   *
   5  *   lundin@mlu.mine.nu                                                    *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "replacements.h"
  27
  28 #include "armv7m.h"
  29 #include "register.h"
  30 #include "target.h"
  31 #include "log.h"
  32 #include "jtag.h"
  33 #include "arm_jtag.h"
  34
  35 #include <stdlib.h>
  36 #include <string.h>
  37
  38 #if 0
  39 #define _DEBUG_INSTRUCTION_EXECUTION_
  40 #endif
  41
  42 char* armv7m_mode_strings[] =
  43 {
  44         "Handler", "Thread"
  45 };
  46
  47 char* armv7m_state_strings[] =
  48 {
  49         "Thumb", "Debug"
  50 };
  51
  52 char* armv7m_exception_strings[] =
  53 {
  54         "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
  55         "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  56 };
  57
  58 char* armv7m_core_reg_list[] =
  59 {
  60 /* Registers accessed through core debug */
  61         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  62         "sp", "lr", "pc",
  63         "xPSR", "msp", "psp",
  64 /* Registers accessed through MSR instructions */
  65 //      "apsr", "iapsr", "ipsr", "epsr",
  66         "primask", "basepri", "faultmask", "control"
  67 };
  68
  69 char* armv7m_core_dbgreg_list[] =
  70 {
  71 /* Registers accessed through core debug */
  72         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  73         "sp", "lr", "pc",
  74         "xPSR", "msp", "psp",
  75 /* Registers accessed through MSR instructions */
  76 //      "dbg_apsr", "iapsr", "ipsr", "epsr",
  77         "primask", "basepri", "faultmask", "dbg_control"
  78 };
  79
  80 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  81
  82 reg_t armv7m_gdb_dummy_fp_reg =
  83 {
  84         "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  85 };
  86
  87 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
  88 {
  89         /*  CORE_GP are accesible using the core debug registers */
  90         {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  91         {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  92         {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  93         {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  94         {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  95         {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  96         {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  97         {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  98         {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  99         {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 100         {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 101         {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 102         {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 103         {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 104         {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 105         {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 106
 107         {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
 108         {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
 109         {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
 110
 111         /*  CORE_SP are accesible using MSR and MRS instructions */
 112 //      {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
 113 //      {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
 114 //      {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
 115 //      {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
 116
 117         {0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
 118         {0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
 119         {0x13, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
 120         {0x14, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}  /* CONTROL */
 121 };
 122
 123 int armv7m_core_reg_arch_type = -1;
 124
 125
 126 /* Keep different contexts for the process being debugged and debug algorithms */
 127 enum armv7m_runcontext armv7m_get_context(target_t *target)
 128 {
 129         /* get pointers to arch-specific information */
 130         armv7m_common_t *armv7m = target->arch_info;
 131
 132         if (armv7m->process_context == armv7m->core_cache) return ARMV7M_PROCESS_CONTEXT;
 133         if (armv7m->debug_context == armv7m->core_cache) return ARMV7M_DEBUG_CONTEXT;
 134
 135         ERROR("Invalid runcontext");
 136         exit(-1);
 137 }
 138
 139 int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
 140 {
 141         int i;
 142         /* get pointers to arch-specific information */
 143         armv7m_common_t *armv7m = target->arch_info;
 144
 145         if ((target->state != TARGET_HALTED) && (target->state != TARGET_RESET))
 146         {
 147                 WARNING("target not halted, switch context ");
 148                 return ERROR_TARGET_NOT_HALTED;
 149         }
 150
 151         if (new_ctx == armv7m_get_context(target))
 152                 return ERROR_OK;
 153
 154         switch (new_ctx)
 155         {
 156                 case ARMV7M_PROCESS_CONTEXT:
 157                          armv7m->core_cache = armv7m->process_context;
 158                          break;
 159                 case ARMV7M_DEBUG_CONTEXT:
 160                          armv7m->core_cache = armv7m->debug_context;
 161                          break;
 162                 default:
 163                         ERROR("Invalid runcontext");
 164                         exit(-1);
 165         }
 166         /* Mark registers in new context as dirty to force reload when run */
 167
 168         for (i = 0; i < armv7m->core_cache->num_regs-1; i++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
 169         {
 170                 armv7m->core_cache->reg_list[i].dirty = 1;
 171         }
 172
 173         return ERROR_OK;
 174 }
 175
 176 /* Core state functions */
 177 char enamebuf[32];
 178 char *armv7m_exception_string(int number)
 179 {
 180         if ((number<0)|(number>511)) return "Invalid exception";
 181         if (number<16) return armv7m_exception_strings[number];
 182         sprintf(enamebuf,"External Interrupt(%i)",number-16);
 183         return enamebuf;
 184 }
 185
 186 int armv7m_get_core_reg(reg_t *reg)
 187 {
 188         int retval;
 189         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 190         target_t *target = armv7m_reg->target;
 191         armv7m_common_t *armv7m_target = target->arch_info;
 192
 193         if (target->state != TARGET_HALTED)
 194         {
 195                 return ERROR_TARGET_NOT_HALTED;
 196         }
 197
 198         retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
 199
 200         return retval;
 201 }
 202
 203 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
 204 {
 205         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 206         target_t *target = armv7m_reg->target;
 207         armv7m_common_t *armv7m_target = target->arch_info;
 208         u32 value = buf_get_u32(buf, 0, 32);
 209
 210         if (target->state != TARGET_HALTED)
 211         {
 212                 return ERROR_TARGET_NOT_HALTED;
 213         }
 214
 215         buf_set_u32(reg->value, 0, 32, value);
 216         reg->dirty = 1;
 217         reg->valid = 1;
 218
 219         return ERROR_OK;
 220 }
 221
 222 int armv7m_read_core_reg(struct target_s *target, int num)
 223 {
 224         u32 reg_value;
 225         int retval;
 226         armv7m_core_reg_t * armv7m_core_reg;
 227
 228         /* get pointers to arch-specific information */
 229         armv7m_common_t *armv7m = target->arch_info;
 230
 231         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 232                 return ERROR_INVALID_ARGUMENTS;
 233
 234         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 235         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 236         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 237         armv7m->core_cache->reg_list[num].valid=1;
 238         armv7m->core_cache->reg_list[num].dirty=0;
 239
 240         return ERROR_OK;
 241 }
 242
 243 int armv7m_write_core_reg(struct target_s *target, int num)
 244 {
 245         int retval;
 246         u32 reg_value;
 247         armv7m_core_reg_t * armv7m_core_reg;
 248
 249         /* get pointers to arch-specific information */
 250         armv7m_common_t *armv7m = target->arch_info;
 251
 252         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 253                 return ERROR_INVALID_ARGUMENTS;
 254
 255
 256         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 257         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 258         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 259         if (retval != ERROR_OK)
 260         {
 261                         ERROR("JTAG failure");
 262                         armv7m->core_cache->reg_list[num].dirty=1;
 263                         return ERROR_JTAG_DEVICE_ERROR;
 264         }
 265         DEBUG("write core reg %i value 0x%x",num ,reg_value);
 266         armv7m->core_cache->reg_list[num].valid=1;
 267         armv7m->core_cache->reg_list[num].dirty=0;
 268
 269         return ERROR_OK;
 270
 271 }
 272
 273
 274
 275 int armv7m_invalidate_core_regs(target_t *target)
 276 {
 277         /* get pointers to arch-specific information */
 278         armv7m_common_t *armv7m = target->arch_info;
 279         int i;
 280
 281         for (i = 0; i < armv7m->core_cache->num_regs; i++)
 282         {
 283                 armv7m->core_cache->reg_list[i].valid = 0;
 284                 armv7m->core_cache->reg_list[i].dirty = 0;
 285         }
 286
 287         return ERROR_OK;
 288 }
 289
 290
 291 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
 292 {
 293         /* get pointers to arch-specific information */
 294         armv7m_common_t *armv7m = target->arch_info;
 295         int i;
 296
 297
 298         if (target->state != TARGET_HALTED)
 299         {
 300                 return ERROR_TARGET_NOT_HALTED;
 301         }
 302
 303         *reg_list_size = 26;
 304         *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
 305
 306         /* TODOLATER correct list of registers, names ? */
 307         for (i = 0; i < *reg_list_size; i++)
 308         {
 309                 if (i<ARMV7NUMCOREREGS)
 310                         (*reg_list)[i] = &armv7m->process_context->reg_list[i];
 311                         //(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 312                 else
 313                         (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
 314         }
 315         /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */
 316         //armv7m->core_cache->reg_list[15].value[0] |= 1;
 317         armv7m->process_context->reg_list[15].value[0] |= 1;
 318         //armv7m->core_cache->reg_list[ARMV7M_xPSR].value[0] = (1<<5);
 319         //armv7m->process_context->reg_list[ARMV7M_xPSR].value[0] = (1<<5);
 320         (*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];
 321         //(*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];
 322         return ERROR_OK;
 323 }
 324
 325 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 326 {
 327         // get pointers to arch-specific information
 328         armv7m_common_t *armv7m = target->arch_info;
 329         armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
 330         enum armv7m_state core_state = armv7m->core_state;
 331         enum armv7m_mode core_mode = armv7m->core_mode;
 332         int retval = ERROR_OK;
 333         u32 pc;
 334         int exit_breakpoint_size = 0;
 335         int i;
 336
 337         armv7m->core_state = core_state;
 338         armv7m->core_mode = core_mode;
 339
 340         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 341         {
 342                 ERROR("current target isn't an ARMV7M target");
 343                 return ERROR_TARGET_INVALID;
 344         }
 345
 346         if (target->state != TARGET_HALTED)
 347         {
 348                 WARNING("target not halted");
 349                 return ERROR_TARGET_NOT_HALTED;
 350         }
 351
 352         /* refresh core register cache */
 353         /* Not needed if core register cache is always consistent with target process state */
 354         armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
 355
 356         for (i = 0; i < num_mem_params; i++)
 357         {
 358                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 359         }
 360
 361         for (i = 0; i < num_reg_params; i++)
 362         {
 363                 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 364                 //reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
 365                 //armv7m_core_reg_t * armv7m_core_reg = reg->arch_info;
 366                 u32 regvalue;
 367
 368                 if (!reg)
 369                 {
 370                         ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 371                         exit(-1);
 372                 }
 373
 374                 if (reg->size != reg_params[i].size)
 375                 {
 376                         ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 377                         exit(-1);
 378                 }
 379
 380                 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 381                 //armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, regvalue);
 382                 armv7m_set_core_reg(reg, reg_params[i].value);
 383         }
 384
 385         /* ARMV7M always runs in Tumb state */
 386         exit_breakpoint_size = 2;
 387         if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_SOFT)) != ERROR_OK)
 388         {
 389                 ERROR("can't add breakpoint to finish algorithm execution");
 390                 return ERROR_TARGET_FAILURE;
 391         }
 392
 393         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 394         sequence to write register values to the processor and the read them back */
 395         target->type->resume(target, 0, entry_point, 1, 1);
 396         target->type->poll(target);
 397
 398         while (target->state != TARGET_HALTED)
 399         {
 400                 usleep(5000);
 401                 target->type->poll(target);
 402                 if ((timeout_ms -= 5) <= 0)
 403                 {
 404                         ERROR("timeout waiting for algorithm to complete, trying to halt target");
 405                         target->type->halt(target);
 406                         timeout_ms = 1000;
 407                         while (target->state != TARGET_HALTED)
 408                         {
 409                                 usleep(10000);
 410                                 target->type->poll(target);
 411                                 if ((timeout_ms -= 10) <= 0)
 412                                 {
 413                                         ERROR("target didn't reenter debug state, exiting");
 414                                         exit(-1);
 415                                 }
 416                         }
 417                         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 418                         DEBUG("failed algoritm halted at 0x%x ",pc);
 419                         retval = ERROR_TARGET_TIMEOUT;
 420                 }
 421         }
 422
 423         breakpoint_remove(target, exit_point);
 424
 425         /* Read memory values to mem_params[] */
 426         for (i = 0; i < num_mem_params; i++)
 427         {
 428                 if (mem_params[i].direction != PARAM_OUT)
 429                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 430         }
 431
 432         /* Copy core register values to reg_params[] */
 433         for (i = 0; i < num_reg_params; i++)
 434         {
 435                 if (reg_params[i].direction != PARAM_OUT)
 436                 {
 437                         //reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 438                         reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
 439                         u32 regvalue;
 440
 441                         if (!reg)
 442                         {
 443                                 ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 444                                 exit(-1);
 445                         }
 446
 447                         if (reg->size != reg_params[i].size)
 448                         {
 449                                 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 450                                 exit(-1);
 451                         }
 452
 453                         armv7m_core_reg_t * armv7m_core_reg = reg->arch_info;
 454                         //armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &regvalue);
 455                         //buf_set_u32(reg_params[i].value, 0, 32, regvalue);
 456                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 457                 }
 458         }
 459
 460         /* Mark all core registers !! except control !! as valid but dirty */
 461         /* This will be done by armv7m_use_context in resume function */
 462         //for (i = 0; i < armv7m->core_cache->num_regs-1; i++)
 463         //{
 464         //      armv7m->core_cache->reg_list[i].dirty = 1;
 465         //}
 466
 467
 468         // ????armv7m->core_state = core_state;
 469         // ????armv7m->core_mode = core_mode;
 470
 471
 472         return retval;
 473 }
 474
 475 int armv7m_arch_state(struct target_s *target, char *buf, int buf_size)
 476 {
 477         /* get pointers to arch-specific information */
 478         armv7m_common_t *armv7m = target->arch_info;
 479
 480         snprintf(buf, buf_size,
 481                          "target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
 482                          armv7m_state_strings[armv7m->core_state],
 483                          target_debug_reason_strings[target->debug_reason],
 484                          armv7m_mode_strings[armv7m->core_mode],
 485                          armv7m_exception_string(armv7m->exception_number),
 486                          buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 487                          buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
 488
 489         return ERROR_OK;
 490 }
 491
 492 reg_cache_t *armv7m_build_reg_cache(target_t *target)
 493 {
 494
 495         /* get pointers to arch-specific information */
 496         armv7m_common_t *armv7m = target->arch_info;
 497         arm_jtag_t *jtag_info = &armv7m->jtag_info;
 498
 499         int num_regs = ARMV7NUMCOREREGS;
 500         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 501         reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 502         reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 503         armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
 504         int i;
 505
 506         if (armv7m_core_reg_arch_type == -1)
 507                 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
 508
 509         /* Build the process context cache */
 510         cache->name = "arm v7m registers";
 511         cache->next = NULL;
 512         cache->reg_list = reg_list;
 513         cache->num_regs = num_regs;
 514         (*cache_p) = cache;
 515         armv7m->core_cache = cache;
 516         armv7m->process_context = cache;
 517
 518         for (i = 0; i < num_regs; i++)
 519         {
 520                 arch_info[i] = armv7m_core_reg_list_arch_info[i];
 521                 arch_info[i].target = target;
 522                 arch_info[i].armv7m_common = armv7m;
 523                 reg_list[i].name = armv7m_core_reg_list[i];
 524                 reg_list[i].size = 32;
 525                 reg_list[i].value = calloc(1, 4);
 526                 reg_list[i].dirty = 0;
 527                 reg_list[i].valid = 0;
 528                 reg_list[i].bitfield_desc = NULL;
 529                 reg_list[i].num_bitfields = 0;
 530                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 531                 reg_list[i].arch_info = &arch_info[i];
 532         }
 533
 534         /* Build the debug context cache*/
 535         cache = malloc(sizeof(reg_cache_t));
 536         reg_list = malloc(sizeof(reg_t) * num_regs);
 537
 538         cache->name = "arm v7m debug registers";
 539         cache->next = NULL;
 540         cache->reg_list = reg_list;
 541         cache->num_regs = num_regs;
 542         armv7m->debug_context = cache;
 543         armv7m->process_context->next = cache;
 544
 545         for (i = 0; i < num_regs; i++)
 546         {
 547                 reg_list[i].name = armv7m_core_dbgreg_list[i];
 548                 reg_list[i].size = 32;
 549                 reg_list[i].value = calloc(1, 4);
 550                 reg_list[i].dirty = 0;
 551                 reg_list[i].valid = 0;
 552                 reg_list[i].bitfield_desc = NULL;
 553                 reg_list[i].num_bitfields = 0;
 554                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 555                 reg_list[i].arch_info = &arch_info[i];
 556         }
 557
 558     return cache;
 559 }
 560
 561 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 562 {
 563
 564         armv7m_build_reg_cache(target);
 565
 566         return ERROR_OK;
 567
 568 }
 569
 570 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
 571 {
 572
 573         /* register arch-specific functions */
 574
 575         target->arch_info = armv7m;
 576         armv7m->core_state = ARMV7M_STATE_THUMB;
 577         armv7m->read_core_reg = armv7m_read_core_reg;
 578         armv7m->write_core_reg = armv7m_write_core_reg;
 579
 580         return ERROR_OK;
 581 }
 582
 583
 584 int armv7m_register_commands(struct command_context_s *cmd_ctx)
 585 {
 586         int retval;
 587
 588         return ERROR_OK;
 589
 590 }