git.gag.com Git - fw/openocd/blob - src/target/armv7m.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  12  *   oyvind.harboe@zylin.com                                               *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  ***************************************************************************/
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include "armv7m.h"
  34
  35
  36 #if 0
  37 #define _DEBUG_INSTRUCTION_EXECUTION_
  38 #endif
  39
  40 char* armv7m_mode_strings[] =
  41 {
  42         "Thread", "Thread (User)", "Handler",
  43 };
  44
  45 char* armv7m_exception_strings[] =
  46 {
  47         "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
  48         "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  49 };
  50
  51 char* armv7m_core_reg_list[] =
  52 {
  53         /* Registers accessed through core debug */
  54         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
  55         "sp", "lr", "pc",
  56         "xPSR", "msp", "psp",
  57         /* Registers accessed through special reg 20 */
  58         "primask", "basepri", "faultmask", "control"
  59 };
  60
  61 uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  62
  63 reg_t armv7m_gdb_dummy_fp_reg =
  64 {
  65         "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  66 };
  67
  68 uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
  69
  70 reg_t armv7m_gdb_dummy_fps_reg =
  71 {
  72         "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
  73 };
  74
  75 #ifdef ARMV7_GDB_HACKS
  76 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  77
  78 reg_t armv7m_gdb_dummy_cpsr_reg =
  79 {
  80         "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
  81 };
  82 #endif
  83
  84 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
  85 {
  86         /*  CORE_GP are accesible using the core debug registers */
  87         {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  88         {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  89         {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  90         {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  91         {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  92         {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  93         {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  94         {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  95         {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  96         {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  97         {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  98         {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
  99         {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 100         {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 101         {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 102         {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
 103
 104         {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
 105         {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
 106         {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
 107
 108         /*  CORE_SP are accesible using coreregister 20 */
 109         {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
 110         {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
 111         {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
 112         {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}  /* CONTROL */
 113 };
 114
 115 int armv7m_core_reg_arch_type = -1;
 116 int armv7m_dummy_core_reg_arch_type = -1;
 117
 118 int armv7m_restore_context(target_t *target)
 119 {
 120         int i;
 121
 122         /* get pointers to arch-specific information */
 123         armv7m_common_t *armv7m = target->arch_info;
 124
 125         LOG_DEBUG(" ");
 126
 127         if (armv7m->pre_restore_context)
 128                 armv7m->pre_restore_context(target);
 129
 130         for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
 131         {
 132                 if (armv7m->core_cache->reg_list[i].dirty)
 133                 {
 134                         armv7m->write_core_reg(target, i);
 135                 }
 136         }
 137
 138         if (armv7m->post_restore_context)
 139                 armv7m->post_restore_context(target);
 140
 141         return ERROR_OK;
 142 }
 143
 144 /* Core state functions */
 145 char *armv7m_exception_string(int number)
 146 {
 147         static char enamebuf[32];
 148
 149         if ((number < 0) | (number > 511))
 150                 return "Invalid exception";
 151         if (number < 16)
 152                 return armv7m_exception_strings[number];
 153         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 154         return enamebuf;
 155 }
 156
 157 int armv7m_get_core_reg(reg_t *reg)
 158 {
 159         int retval;
 160         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 161         target_t *target = armv7m_reg->target;
 162         armv7m_common_t *armv7m_target = target->arch_info;
 163
 164         if (target->state != TARGET_HALTED)
 165         {
 166                 return ERROR_TARGET_NOT_HALTED;
 167         }
 168
 169         retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
 170
 171         return retval;
 172 }
 173
 174 int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
 175 {
 176         armv7m_core_reg_t *armv7m_reg = reg->arch_info;
 177         target_t *target = armv7m_reg->target;
 178         uint32_t value = buf_get_u32(buf, 0, 32);
 179
 180         if (target->state != TARGET_HALTED)
 181         {
 182                 return ERROR_TARGET_NOT_HALTED;
 183         }
 184
 185         buf_set_u32(reg->value, 0, 32, value);
 186         reg->dirty = 1;
 187         reg->valid = 1;
 188
 189         return ERROR_OK;
 190 }
 191
 192 int armv7m_read_core_reg(struct target_s *target, int num)
 193 {
 194         uint32_t reg_value;
 195         int retval;
 196         armv7m_core_reg_t * armv7m_core_reg;
 197
 198         /* get pointers to arch-specific information */
 199         armv7m_common_t *armv7m = target->arch_info;
 200
 201         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 202                 return ERROR_INVALID_ARGUMENTS;
 203
 204         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 205         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 206         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 207         armv7m->core_cache->reg_list[num].valid = 1;
 208         armv7m->core_cache->reg_list[num].dirty = 0;
 209
 210         return retval;
 211 }
 212
 213 int armv7m_write_core_reg(struct target_s *target, int num)
 214 {
 215         int retval;
 216         uint32_t reg_value;
 217         armv7m_core_reg_t *armv7m_core_reg;
 218
 219         /* get pointers to arch-specific information */
 220         armv7m_common_t *armv7m = target->arch_info;
 221
 222         if ((num < 0) || (num >= ARMV7NUMCOREREGS))
 223                 return ERROR_INVALID_ARGUMENTS;
 224
 225         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 226         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 227         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 228         if (retval != ERROR_OK)
 229         {
 230                 LOG_ERROR("JTAG failure");
 231                 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 232                 return ERROR_JTAG_DEVICE_ERROR;
 233         }
 234         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 235         armv7m->core_cache->reg_list[num].valid = 1;
 236         armv7m->core_cache->reg_list[num].dirty = 0;
 237
 238         return ERROR_OK;
 239 }
 240
 241 int armv7m_invalidate_core_regs(target_t *target)
 242 {
 243         /* get pointers to arch-specific information */
 244         armv7m_common_t *armv7m = target->arch_info;
 245         int i;
 246
 247         for (i = 0; i < armv7m->core_cache->num_regs; i++)
 248         {
 249                 armv7m->core_cache->reg_list[i].valid = 0;
 250                 armv7m->core_cache->reg_list[i].dirty = 0;
 251         }
 252
 253         return ERROR_OK;
 254 }
 255
 256 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
 257 {
 258         /* get pointers to arch-specific information */
 259         armv7m_common_t *armv7m = target->arch_info;
 260         int i;
 261
 262         *reg_list_size = 26;
 263         *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
 264
 265         for (i = 0; i < 16; i++)
 266         {
 267                 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 268         }
 269
 270         for (i = 16; i < 24; i++)
 271         {
 272                 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
 273         }
 274
 275         (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
 276
 277 #ifdef ARMV7_GDB_HACKS
 278         /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
 279         (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
 280
 281         /* ARMV7M is always in thumb mode, try to make GDB understand this
 282          * if it does not support this arch */
 283         *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
 284 #else
 285         (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 286 #endif
 287
 288         return ERROR_OK;
 289 }
 290
 291 /* run to exit point. return error if exit point was not reached. */
 292 static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, armv7m_common_t *armv7m)
 293 {
 294         uint32_t pc;
 295         int retval;
 296         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 297          * sequence to write register values to the processor and the read them back */
 298         if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
 299         {
 300                 return retval;
 301         }
 302
 303         retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
 304         /* If the target fails to halt due to the breakpoint, force a halt */
 305         if (retval != ERROR_OK || target->state != TARGET_HALTED)
 306         {
 307                 if ((retval=target_halt(target))!=ERROR_OK)
 308                         return retval;
 309                 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
 310                 {
 311                         return retval;
 312                 }
 313                 return ERROR_TARGET_TIMEOUT;
 314         }
 315
 316         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 317         if (pc != exit_point)
 318         {
 319                 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
 320                 return ERROR_TARGET_TIMEOUT;
 321         }
 322
 323         return ERROR_OK;
 324 }
 325
 326 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
 327 {
 328         /* get pointers to arch-specific information */
 329         armv7m_common_t *armv7m = target->arch_info;
 330         armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
 331         enum armv7m_mode core_mode = armv7m->core_mode;
 332         int retval = ERROR_OK;
 333         int i;
 334         uint32_t context[ARMV7NUMCOREREGS];
 335
 336         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 337         {
 338                 LOG_ERROR("current target isn't an ARMV7M target");
 339                 return ERROR_TARGET_INVALID;
 340         }
 341
 342         if (target->state != TARGET_HALTED)
 343         {
 344                 LOG_WARNING("target not halted");
 345                 return ERROR_TARGET_NOT_HALTED;
 346         }
 347
 348         /* refresh core register cache */
 349         /* Not needed if core register cache is always consistent with target process state */
 350         for (i = 0; i < ARMV7NUMCOREREGS; i++)
 351         {
 352                 if (!armv7m->core_cache->reg_list[i].valid)
 353                         armv7m->read_core_reg(target, i);
 354                 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 355         }
 356
 357         for (i = 0; i < num_mem_params; i++)
 358         {
 359                 if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value))!=ERROR_OK)
 360                         return retval;
 361         }
 362
 363         for (i = 0; i < num_reg_params; i++)
 364         {
 365                 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 366 //              uint32_t regvalue;
 367
 368                 if (!reg)
 369                 {
 370                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 371                         exit(-1);
 372                 }
 373
 374                 if (reg->size != reg_params[i].size)
 375                 {
 376                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 377                         exit(-1);
 378                 }
 379
 380 //              regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 381                 armv7m_set_core_reg(reg, reg_params[i].value);
 382         }
 383
 384         if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
 385         {
 386                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 387                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
 388                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
 389                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 390         }
 391
 392         /* ARMV7M always runs in Thumb state */
 393         if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
 394         {
 395                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
 396                 return ERROR_TARGET_FAILURE;
 397         }
 398
 399         retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
 400
 401         breakpoint_remove(target, exit_point);
 402
 403         if (retval != ERROR_OK)
 404         {
 405                 return retval;
 406         }
 407
 408         /* Read memory values to mem_params[] */
 409         for (i = 0; i < num_mem_params; i++)
 410         {
 411                 if (mem_params[i].direction != PARAM_OUT)
 412                         if((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 413                         {
 414                                 return retval;
 415                         }
 416         }
 417
 418         /* Copy core register values to reg_params[] */
 419         for (i = 0; i < num_reg_params; i++)
 420         {
 421                 if (reg_params[i].direction != PARAM_OUT)
 422                 {
 423                         reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 424
 425                         if (!reg)
 426                         {
 427                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 428                                 exit(-1);
 429                         }
 430
 431                         if (reg->size != reg_params[i].size)
 432                         {
 433                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 434                                 exit(-1);
 435                         }
 436
 437                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 438                 }
 439         }
 440
 441         for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
 442         {
 443                 uint32_t regvalue;
 444                 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 445                 if (regvalue != context[i])
 446                 {
 447                         LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", armv7m->core_cache->reg_list[i].name, context[i]);
 448                         buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
 449                         armv7m->core_cache->reg_list[i].valid = 1;
 450                         armv7m->core_cache->reg_list[i].dirty = 1;
 451                 }
 452         }
 453
 454         armv7m->core_mode = core_mode;
 455
 456         return retval;
 457 }
 458
 459 int armv7m_arch_state(struct target_s *target)
 460 {
 461         /* get pointers to arch-specific information */
 462         armv7m_common_t *armv7m = target->arch_info;
 463
 464         LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
 465                  Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
 466                 armv7m_mode_strings[armv7m->core_mode],
 467                 armv7m_exception_string(armv7m->exception_number),
 468                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 469                 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
 470
 471         return ERROR_OK;
 472 }
 473
 474 reg_cache_t *armv7m_build_reg_cache(target_t *target)
 475 {
 476         /* get pointers to arch-specific information */
 477         armv7m_common_t *armv7m = target->arch_info;
 478
 479         int num_regs = ARMV7NUMCOREREGS;
 480         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 481         reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 482         reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 483         armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
 484         int i;
 485
 486         if (armv7m_core_reg_arch_type == -1)
 487         {
 488                 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
 489         }
 490
 491         register_init_dummy(&armv7m_gdb_dummy_fps_reg);
 492 #ifdef ARMV7_GDB_HACKS
 493         register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
 494 #endif
 495         register_init_dummy(&armv7m_gdb_dummy_fp_reg);
 496
 497         /* Build the process context cache */
 498         cache->name = "arm v7m registers";
 499         cache->next = NULL;
 500         cache->reg_list = reg_list;
 501         cache->num_regs = num_regs;
 502         (*cache_p) = cache;
 503         armv7m->core_cache = cache;
 504
 505         for (i = 0; i < num_regs; i++)
 506         {
 507                 arch_info[i] = armv7m_core_reg_list_arch_info[i];
 508                 arch_info[i].target = target;
 509                 arch_info[i].armv7m_common = armv7m;
 510                 reg_list[i].name = armv7m_core_reg_list[i];
 511                 reg_list[i].size = 32;
 512                 reg_list[i].value = calloc(1, 4);
 513                 reg_list[i].dirty = 0;
 514                 reg_list[i].valid = 0;
 515                 reg_list[i].bitfield_desc = NULL;
 516                 reg_list[i].num_bitfields = 0;
 517                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 518                 reg_list[i].arch_info = &arch_info[i];
 519         }
 520
 521         return cache;
 522 }
 523
 524 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 525 {
 526         armv7m_build_reg_cache(target);
 527
 528         return ERROR_OK;
 529 }
 530
 531 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
 532 {
 533         /* register arch-specific functions */
 534
 535         target->arch_info = armv7m;
 536         armv7m->read_core_reg = armv7m_read_core_reg;
 537         armv7m->write_core_reg = armv7m_write_core_reg;
 538
 539         return ERROR_OK;
 540 }
 541
 542 int armv7m_register_commands(struct command_context_s *cmd_ctx)
 543 {
 544         command_t *arm_adi_v5_dap_cmd;
 545
 546         arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands");
 547         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "Displays dap info for ap [num], default currently selected AP");
 548         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "Select a different AP [num] (default 0)");
 549         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", handle_dap_apid_command, COMMAND_EXEC, "Displays id reg from AP [num], default currently selected AP");
 550         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr", handle_dap_baseaddr_command, COMMAND_EXEC, "Displays debug base address from AP [num], default currently selected AP");
 551         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess", handle_dap_memaccess_command, COMMAND_EXEC, "set/get number of extra tck for mem-ap memory bus access [0-255]");
 552
 553         return ERROR_OK;
 554 }
 555
 556 int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
 557 {
 558         working_area_t *crc_algorithm;
 559         armv7m_algorithm_t armv7m_info;
 560         reg_param_t reg_params[2];
 561         int retval;
 562
 563         uint16_t cortex_m3_crc_code[] = {
 564                 0x4602,                                 /* mov  r2, r0 */
 565                 0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
 566                 0x460B,                                 /* mov  r3, r1 */
 567                 0xF04F, 0x0400,                 /* mov  r4, #0 */
 568                 0xE013,                                 /* b    ncomp */
 569                                                                 /* nbyte: */
 570                 0x5D11,                                 /* ldrb r1, [r2, r4] */
 571                 0xF8DF, 0x7028,                 /* ldr          r7, CRC32XOR */
 572                 0xEA80, 0x6001,                 /* eor          r0, r0, r1, asl #24 */
 573
 574                 0xF04F, 0x0500,                 /* mov          r5, #0 */
 575                                                                 /* loop: */
 576                 0x2800,                                 /* cmp          r0, #0 */
 577                 0xEA4F, 0x0640,                 /* mov          r6, r0, asl #1 */
 578                 0xF105, 0x0501,                 /* add          r5, r5, #1 */
 579                 0x4630,                                 /* mov          r0, r6 */
 580                 0xBFB8,                                 /* it           lt */
 581                 0xEA86, 0x0007,                 /* eor          r0, r6, r7 */
 582                 0x2D08,                                 /* cmp          r5, #8 */
 583                 0xD1F4,                                 /* bne          loop */
 584
 585                 0xF104, 0x0401,                 /* add  r4, r4, #1 */
 586                                                                 /* ncomp: */
 587                 0x429C,                                 /* cmp  r4, r3 */
 588                 0xD1E9,                                 /* bne  nbyte */
 589                                                                 /* end: */
 590                 0xE7FE,                                 /* b    end */
 591                 0x1DB7, 0x04C1                  /* CRC32XOR:    .word 0x04C11DB7 */
 592         };
 593
 594         uint32_t i;
 595
 596         if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
 597         {
 598                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 599         }
 600
 601         /* convert flash writing code into a buffer in target endianness */
 602         for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
 603                 if((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
 604                 {
 605                         return retval;
 606                 }
 607
 608         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 609         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 610
 611         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 612         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 613
 614         buf_set_u32(reg_params[0].value, 0, 32, address);
 615         buf_set_u32(reg_params[1].value, 0, 32, count);
 616
 617         if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
 618                 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
 619         {
 620                 LOG_ERROR("error executing cortex_m3 crc algorithm");
 621                 destroy_reg_param(&reg_params[0]);
 622                 destroy_reg_param(&reg_params[1]);
 623                 target_free_working_area(target, crc_algorithm);
 624                 return retval;
 625         }
 626
 627         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 628
 629         destroy_reg_param(&reg_params[0]);
 630         destroy_reg_param(&reg_params[1]);
 631
 632         target_free_working_area(target, crc_algorithm);
 633
 634         return ERROR_OK;
 635 }
 636
 637 int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
 638 {
 639         working_area_t *erase_check_algorithm;
 640         reg_param_t reg_params[3];
 641         armv7m_algorithm_t armv7m_info;
 642         int retval;
 643         uint32_t i;
 644
 645         uint16_t erase_check_code[] =
 646         {
 647                                                         /* loop: */
 648                 0xF810, 0x3B01,         /* ldrb         r3, [r0], #1 */
 649                 0xEA02, 0x0203,         /* and  r2, r2, r3 */
 650                 0x3901,                         /* subs         r1, r1, #1 */
 651                 0xD1F9,                         /* bne          loop */
 652                                                         /* end: */
 653                 0xE7FE,                         /* b            end */
 654         };
 655
 656         /* make sure we have a working area */
 657         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
 658         {
 659                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 660         }
 661
 662         /* convert flash writing code into a buffer in target endianness */
 663         for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
 664                 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
 665
 666         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 667         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 668
 669         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 670         buf_set_u32(reg_params[0].value, 0, 32, address);
 671
 672         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 673         buf_set_u32(reg_params[1].value, 0, 32, count);
 674
 675         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 676         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
 677
 678         if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 679                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
 680         {
 681                 destroy_reg_param(&reg_params[0]);
 682                 destroy_reg_param(&reg_params[1]);
 683                 destroy_reg_param(&reg_params[2]);
 684                 target_free_working_area(target, erase_check_algorithm);
 685                 return 0;
 686         }
 687
 688         *blank = buf_get_u32(reg_params[2].value, 0, 32);
 689
 690         destroy_reg_param(&reg_params[0]);
 691         destroy_reg_param(&reg_params[1]);
 692         destroy_reg_param(&reg_params[2]);
 693
 694         target_free_working_area(target, erase_check_algorithm);
 695
 696         return ERROR_OK;
 697 }
 698
 699 /********************************************************************************************************************
 700 * Return the debug ap baseaddress in hexadecimal, no extra output to simplify script processing
 701 *********************************************************************************************************************/
 702 int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 703 {
 704         target_t *target = get_current_target(cmd_ctx);
 705         armv7m_common_t *armv7m = target->arch_info;
 706         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 707         uint32_t apsel, apselsave, baseaddr;
 708         int retval;
 709
 710         apsel = swjdp->apsel;
 711         apselsave = swjdp->apsel;
 712         if (argc > 0)
 713         {
 714                 apsel = strtoul(args[0], NULL, 0);
 715         }
 716         if (apselsave != apsel)
 717         {
 718                 dap_ap_select(swjdp, apsel);
 719         }
 720
 721         dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
 722         retval = swjdp_transaction_endcheck(swjdp);
 723         command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr);
 724
 725         if (apselsave != apsel)
 726         {
 727                 dap_ap_select(swjdp, apselsave);
 728         }
 729
 730         return retval;
 731 }
 732
 733
 734 /********************************************************************************************************************
 735 * Return the debug ap id in hexadecimal, no extra output to simplify script processing
 736 *********************************************************************************************************************/
 737 extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 738 {
 739         target_t *target = get_current_target(cmd_ctx);
 740         armv7m_common_t *armv7m = target->arch_info;
 741         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 742         uint32_t apsel, apselsave, apid;
 743         int retval;
 744
 745         apsel = swjdp->apsel;
 746         apselsave = swjdp->apsel;
 747         if (argc > 0)
 748         {
 749                 apsel = strtoul(args[0], NULL, 0);
 750         }
 751
 752         if (apselsave != apsel)
 753         {
 754                 dap_ap_select(swjdp, apsel);
 755         }
 756
 757         dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
 758         retval = swjdp_transaction_endcheck(swjdp);
 759         command_print(cmd_ctx, "0x%8.8" PRIx32 "", apid);
 760         if (apselsave != apsel)
 761         {
 762                 dap_ap_select(swjdp, apselsave);
 763         }
 764
 765         return retval;
 766 }
 767
 768 int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 769 {
 770         target_t *target = get_current_target(cmd_ctx);
 771         armv7m_common_t *armv7m = target->arch_info;
 772         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 773         uint32_t apsel, apid;
 774         int retval;
 775
 776         apsel = 0;
 777         if (argc > 0)
 778         {
 779                 apsel = strtoul(args[0], NULL, 0);
 780         }
 781
 782         dap_ap_select(swjdp, apsel);
 783         dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
 784         retval = swjdp_transaction_endcheck(swjdp);
 785         command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8" PRIx32 "", (int)apsel, apid);
 786
 787         return retval;
 788 }
 789
 790 int handle_dap_memaccess_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 791 {
 792         target_t *target = get_current_target(cmd_ctx);
 793         armv7m_common_t *armv7m = target->arch_info;
 794         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 795         uint32_t memaccess_tck;
 796
 797         memaccess_tck = swjdp->memaccess_tck;
 798         if (argc > 0)
 799         {
 800                 memaccess_tck = strtoul(args[0], NULL, 0);
 801         }
 802
 803         swjdp->memaccess_tck = memaccess_tck;
 804         command_print(cmd_ctx, "memory bus access delay set to %i tck", (int)(swjdp->memaccess_tck));
 805
 806         return ERROR_OK;
 807 }
 808
 809 int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 810 {
 811         target_t *target = get_current_target(cmd_ctx);
 812         armv7m_common_t *armv7m = target->arch_info;
 813         swjdp_common_t *swjdp = &armv7m->swjdp_info;
 814         int retval;
 815         uint32_t apsel;
 816
 817         apsel =  swjdp->apsel;
 818         if (argc > 0)
 819         {
 820                 apsel = strtoul(args[0], NULL, 0);
 821         }
 822
 823         retval = dap_info_command(cmd_ctx, swjdp, apsel);
 824
 825         return retval;
 826 }
 827