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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  12  *   oyvind.harboe@zylin.com                                               *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  *                                                                         *
  29  *      ARMv7-M Architecture, Application Level Reference Manual               *
  30  *              ARM DDI 0405C (September 2008)                             *
  31  *                                                                         *
  32  ***************************************************************************/
  33 #ifdef HAVE_CONFIG_H
  34 #include "config.h"
  35 #endif
  36
  37 #include "breakpoints.h"
  38 #include "armv7m.h"
  39 #include "algorithm.h"
  40 #include "register.h"
  41
  42
  43 #if 0
  44 #define _DEBUG_INSTRUCTION_EXECUTION_
  45 #endif
  46
  47 /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
  48 char *armv7m_mode_strings[] =
  49 {
  50         "Thread", "Thread (User)", "Handler",
  51 };
  52
  53 static char *armv7m_exception_strings[] =
  54 {
  55         "", "Reset", "NMI", "HardFault",
  56         "MemManage", "BusFault", "UsageFault", "RESERVED",
  57         "RESERVED", "RESERVED", "RESERVED", "SVCall",
  58         "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  59 };
  60
  61 #ifdef ARMV7_GDB_HACKS
  62 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  63
  64 struct reg armv7m_gdb_dummy_cpsr_reg =
  65 {
  66         .name = "GDB dummy cpsr register",
  67         .value = armv7m_gdb_dummy_cpsr_value,
  68         .dirty = 0,
  69         .valid = 1,
  70         .size = 32,
  71         .arch_info = NULL,
  72 };
  73 #endif
  74
  75 /*
  76  * These registers are not memory-mapped.  The ARMv7-M profile includes
  77  * memory mapped registers too, such as for the NVIC (interrupt controller)
  78  * and SysTick (timer) modules; those can mostly be treated as peripherals.
  79  *
  80  * The ARMv6-M profile is almost identical in this respect, except that it
  81  * doesn't include basepri or faultmask registers.
  82  */
  83 static const struct {
  84         unsigned id;
  85         char *name;
  86         unsigned bits;
  87 } armv7m_regs[] = {
  88         { ARMV7M_R0, "r0", 32 },
  89         { ARMV7M_R1, "r1", 32 },
  90         { ARMV7M_R2, "r2", 32 },
  91         { ARMV7M_R3, "r3", 32 },
  92
  93         { ARMV7M_R4, "r4", 32 },
  94         { ARMV7M_R5, "r5", 32 },
  95         { ARMV7M_R6, "r6", 32 },
  96         { ARMV7M_R7, "r7", 32 },
  97
  98         { ARMV7M_R8, "r8", 32 },
  99         { ARMV7M_R9, "r9", 32 },
 100         { ARMV7M_R10, "r10", 32 },
 101         { ARMV7M_R11, "r11", 32 },
 102
 103         { ARMV7M_R12, "r12", 32 },
 104         { ARMV7M_R13, "sp", 32 },
 105         { ARMV7M_R14, "lr", 32 },
 106         { ARMV7M_PC, "pc", 32 },
 107
 108         { ARMV7M_xPSR, "xPSR", 32 },
 109         { ARMV7M_MSP, "msp", 32 },
 110         { ARMV7M_PSP, "psp", 32 },
 111
 112         { ARMV7M_PRIMASK, "primask", 1 },
 113         { ARMV7M_BASEPRI, "basepri", 8 },
 114         { ARMV7M_FAULTMASK, "faultmask", 1 },
 115         { ARMV7M_CONTROL, "control", 2 },
 116 };
 117
 118 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
 119
 120 /**
 121  * Restores target context using the cache of core registers set up
 122  * by armv7m_build_reg_cache(), calling optional core-specific hooks.
 123  */
 124 int armv7m_restore_context(struct target *target)
 125 {
 126         int i;
 127         struct armv7m_common *armv7m = target_to_armv7m(target);
 128
 129         LOG_DEBUG(" ");
 130
 131         if (armv7m->pre_restore_context)
 132                 armv7m->pre_restore_context(target);
 133
 134         for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
 135         {
 136                 if (armv7m->core_cache->reg_list[i].dirty)
 137                 {
 138                         armv7m->write_core_reg(target, i);
 139                 }
 140         }
 141
 142         if (armv7m->post_restore_context)
 143                 armv7m->post_restore_context(target);
 144
 145         return ERROR_OK;
 146 }
 147
 148 /* Core state functions */
 149
 150 /**
 151  * Maps ISR number (from xPSR) to name.
 152  * Note that while names and meanings for the first sixteen are standardized
 153  * (with zero not a true exception), external interrupts are only numbered.
 154  * They are assigned by vendors, which generally assign different numbers to
 155  * peripherals (such as UART0 or a USB peripheral controller).
 156  */
 157 char *armv7m_exception_string(int number)
 158 {
 159         static char enamebuf[32];
 160
 161         if ((number < 0) | (number > 511))
 162                 return "Invalid exception";
 163         if (number < 16)
 164                 return armv7m_exception_strings[number];
 165         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 166         return enamebuf;
 167 }
 168
 169 static int armv7m_get_core_reg(struct reg *reg)
 170 {
 171         int retval;
 172         struct armv7m_core_reg *armv7m_reg = reg->arch_info;
 173         struct target *target = armv7m_reg->target;
 174         struct armv7m_common *armv7m = target_to_armv7m(target);
 175
 176         if (target->state != TARGET_HALTED)
 177         {
 178                 return ERROR_TARGET_NOT_HALTED;
 179         }
 180
 181         retval = armv7m->read_core_reg(target, armv7m_reg->num);
 182
 183         return retval;
 184 }
 185
 186 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
 187 {
 188         struct armv7m_core_reg *armv7m_reg = reg->arch_info;
 189         struct target *target = armv7m_reg->target;
 190         uint32_t value = buf_get_u32(buf, 0, 32);
 191
 192         if (target->state != TARGET_HALTED)
 193         {
 194                 return ERROR_TARGET_NOT_HALTED;
 195         }
 196
 197         buf_set_u32(reg->value, 0, 32, value);
 198         reg->dirty = 1;
 199         reg->valid = 1;
 200
 201         return ERROR_OK;
 202 }
 203
 204 static int armv7m_read_core_reg(struct target *target, unsigned num)
 205 {
 206         uint32_t reg_value;
 207         int retval;
 208         struct armv7m_core_reg * armv7m_core_reg;
 209         struct armv7m_common *armv7m = target_to_armv7m(target);
 210
 211         if (num >= ARMV7M_NUM_REGS)
 212                 return ERROR_INVALID_ARGUMENTS;
 213
 214         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 215         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 216         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 217         armv7m->core_cache->reg_list[num].valid = 1;
 218         armv7m->core_cache->reg_list[num].dirty = 0;
 219
 220         return retval;
 221 }
 222
 223 static int armv7m_write_core_reg(struct target *target, unsigned num)
 224 {
 225         int retval;
 226         uint32_t reg_value;
 227         struct armv7m_core_reg *armv7m_core_reg;
 228         struct armv7m_common *armv7m = target_to_armv7m(target);
 229
 230         if (num >= ARMV7M_NUM_REGS)
 231                 return ERROR_INVALID_ARGUMENTS;
 232
 233         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 234         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 235         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 236         if (retval != ERROR_OK)
 237         {
 238                 LOG_ERROR("JTAG failure");
 239                 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 240                 return ERROR_JTAG_DEVICE_ERROR;
 241         }
 242         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 243         armv7m->core_cache->reg_list[num].valid = 1;
 244         armv7m->core_cache->reg_list[num].dirty = 0;
 245
 246         return ERROR_OK;
 247 }
 248
 249 /**
 250  * Returns generic ARM userspace registers to GDB.
 251  * GDB doesn't quite understand that most ARMs don't have floating point
 252  * hardware, so this also fakes a set of long-obsolete FPA registers that
 253  * are not used in EABI based software stacks.
 254  */
 255 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
 256 {
 257         struct armv7m_common *armv7m = target_to_armv7m(target);
 258         int i;
 259
 260         *reg_list_size = 26;
 261         *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 262
 263         /*
 264          * GDB register packet format for ARM:
 265          *  - the first 16 registers are r0..r15
 266          *  - (obsolete) 8 FPA registers
 267          *  - (obsolete) FPA status
 268          *  - CPSR
 269          */
 270         for (i = 0; i < 16; i++)
 271         {
 272                 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 273         }
 274
 275         for (i = 16; i < 24; i++)
 276                 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
 277         (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
 278
 279 #ifdef ARMV7_GDB_HACKS
 280         /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
 281         (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
 282
 283         /* ARMV7M is always in thumb mode, try to make GDB understand this
 284          * if it does not support this arch */
 285         *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
 286 #else
 287         (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 288 #endif
 289
 290         return ERROR_OK;
 291 }
 292
 293 /* run to exit point. return error if exit point was not reached. */
 294 static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m)
 295 {
 296         uint32_t pc;
 297         int retval;
 298         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 299          * sequence to write register values to the processor and the read them back */
 300         if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
 301         {
 302                 return retval;
 303         }
 304
 305         retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
 306         /* If the target fails to halt due to the breakpoint, force a halt */
 307         if (retval != ERROR_OK || target->state != TARGET_HALTED)
 308         {
 309                 if ((retval = target_halt(target)) != ERROR_OK)
 310                         return retval;
 311                 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
 312                 {
 313                         return retval;
 314                 }
 315                 return ERROR_TARGET_TIMEOUT;
 316         }
 317
 318         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 319         if (pc != exit_point)
 320         {
 321                 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
 322                 return ERROR_TARGET_TIMEOUT;
 323         }
 324
 325         return ERROR_OK;
 326 }
 327
 328 /** Runs a Thumb algorithm in the target. */
 329 int armv7m_run_algorithm(struct target *target,
 330         int num_mem_params, struct mem_param *mem_params,
 331         int num_reg_params, struct reg_param *reg_params,
 332         uint32_t entry_point, uint32_t exit_point,
 333         int timeout_ms, void *arch_info)
 334 {
 335         struct armv7m_common *armv7m = target_to_armv7m(target);
 336         struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
 337         enum armv7m_mode core_mode = armv7m->core_mode;
 338         int retval = ERROR_OK;
 339         uint32_t context[ARMV7M_NUM_REGS];
 340
 341         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 342         {
 343                 LOG_ERROR("current target isn't an ARMV7M target");
 344                 return ERROR_TARGET_INVALID;
 345         }
 346
 347         if (target->state != TARGET_HALTED)
 348         {
 349                 LOG_WARNING("target not halted");
 350                 return ERROR_TARGET_NOT_HALTED;
 351         }
 352
 353         /* refresh core register cache */
 354         /* Not needed if core register cache is always consistent with target process state */
 355         for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++)
 356         {
 357                 if (!armv7m->core_cache->reg_list[i].valid)
 358                         armv7m->read_core_reg(target, i);
 359                 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 360         }
 361
 362         for (int i = 0; i < num_mem_params; i++)
 363         {
 364                 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 365                         return retval;
 366         }
 367
 368         for (int i = 0; i < num_reg_params; i++)
 369         {
 370                 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 371 //              uint32_t regvalue;
 372
 373                 if (!reg)
 374                 {
 375                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 376                         return ERROR_INVALID_ARGUMENTS;
 377                 }
 378
 379                 if (reg->size != reg_params[i].size)
 380                 {
 381                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 382                         return ERROR_INVALID_ARGUMENTS;
 383                 }
 384
 385 //              regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 386                 armv7m_set_core_reg(reg, reg_params[i].value);
 387         }
 388
 389         if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
 390         {
 391                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 392                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
 393                                 0, 1, armv7m_algorithm_info->core_mode);
 394                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
 395                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 396         }
 397
 398         /* REVISIT speed things up (3% or so in one case) by requiring
 399          * algorithms to include a BKPT instruction at each exit point.
 400          * This eliminates overheads of adding/removing a breakpoint.
 401          */
 402
 403         /* ARMV7M always runs in Thumb state */
 404         if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
 405         {
 406                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
 407                 return ERROR_TARGET_FAILURE;
 408         }
 409
 410         retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
 411
 412         breakpoint_remove(target, exit_point);
 413
 414         if (retval != ERROR_OK)
 415         {
 416                 return retval;
 417         }
 418
 419         /* Read memory values to mem_params[] */
 420         for (int i = 0; i < num_mem_params; i++)
 421         {
 422                 if (mem_params[i].direction != PARAM_OUT)
 423                         if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 424                         {
 425                                 return retval;
 426                         }
 427         }
 428
 429         /* Copy core register values to reg_params[] */
 430         for (int i = 0; i < num_reg_params; i++)
 431         {
 432                 if (reg_params[i].direction != PARAM_OUT)
 433                 {
 434                         struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 435
 436                         if (!reg)
 437                         {
 438                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 439                                 return ERROR_INVALID_ARGUMENTS;
 440                         }
 441
 442                         if (reg->size != reg_params[i].size)
 443                         {
 444                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 445                                 return ERROR_INVALID_ARGUMENTS;
 446                         }
 447
 448                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 449                 }
 450         }
 451
 452         for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
 453         {
 454                 uint32_t regvalue;
 455                 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 456                 if (regvalue != context[i])
 457                 {
 458                         LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
 459                                 armv7m->core_cache->reg_list[i].name, context[i]);
 460                         buf_set_u32(armv7m->core_cache->reg_list[i].value,
 461                                         0, 32, context[i]);
 462                         armv7m->core_cache->reg_list[i].valid = 1;
 463                         armv7m->core_cache->reg_list[i].dirty = 1;
 464                 }
 465         }
 466
 467         armv7m->core_mode = core_mode;
 468
 469         return retval;
 470 }
 471
 472 /** Logs summary of ARMv7-M state for a halted target. */
 473 int armv7m_arch_state(struct target *target)
 474 {
 475         struct armv7m_common *armv7m = target_to_armv7m(target);
 476         uint32_t ctrl, sp;
 477
 478         ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
 479         sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 480
 481         LOG_USER("target halted due to %s, current mode: %s %s\n"
 482                 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
 483                 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
 484                                 target->debug_reason)->name,
 485                 armv7m_mode_strings[armv7m->core_mode],
 486                 armv7m_exception_string(armv7m->exception_number),
 487                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 488                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32),
 489                 (ctrl & 0x02) ? 'p' : 'm',
 490                 sp);
 491
 492         return ERROR_OK;
 493 }
 494 static const struct reg_arch_type armv7m_reg_type = {
 495         .get = armv7m_get_core_reg,
 496         .set = armv7m_set_core_reg,
 497 };
 498
 499 /** Builds cache of architecturally defined registers.  */
 500 struct reg_cache *armv7m_build_reg_cache(struct target *target)
 501 {
 502         struct armv7m_common *armv7m = target_to_armv7m(target);
 503         int num_regs = ARMV7M_NUM_REGS;
 504         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 505         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 506         struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
 507         struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
 508         int i;
 509
 510 #ifdef ARMV7_GDB_HACKS
 511         register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
 512 #endif
 513
 514         /* Build the process context cache */
 515         cache->name = "arm v7m registers";
 516         cache->next = NULL;
 517         cache->reg_list = reg_list;
 518         cache->num_regs = num_regs;
 519         (*cache_p) = cache;
 520         armv7m->core_cache = cache;
 521
 522         for (i = 0; i < num_regs; i++)
 523         {
 524                 arch_info[i].num = armv7m_regs[i].id;
 525                 arch_info[i].target = target;
 526                 arch_info[i].armv7m_common = armv7m;
 527                 reg_list[i].name = armv7m_regs[i].name;
 528                 reg_list[i].size = armv7m_regs[i].bits;
 529                 reg_list[i].value = calloc(1, 4);
 530                 reg_list[i].dirty = 0;
 531                 reg_list[i].valid = 0;
 532                 reg_list[i].type = &armv7m_reg_type;
 533                 reg_list[i].arch_info = &arch_info[i];
 534         }
 535
 536         return cache;
 537 }
 538
 539 /** Sets up target as a generic ARMv7-M core */
 540 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
 541 {
 542         /* register arch-specific functions */
 543
 544         target->arch_info = armv7m;
 545         armv7m->read_core_reg = armv7m_read_core_reg;
 546         armv7m->write_core_reg = armv7m_write_core_reg;
 547
 548         return ERROR_OK;
 549 }
 550
 551 /** Generates a CRC32 checksum of a memory region. */
 552 int armv7m_checksum_memory(struct target *target,
 553                 uint32_t address, uint32_t count, uint32_t* checksum)
 554 {
 555         struct working_area *crc_algorithm;
 556         struct armv7m_algorithm armv7m_info;
 557         struct reg_param reg_params[2];
 558         int retval;
 559
 560         static const uint16_t cortex_m3_crc_code[] = {
 561                 0x4602,                                 /* mov  r2, r0 */
 562                 0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
 563                 0x460B,                                 /* mov  r3, r1 */
 564                 0xF04F, 0x0400,                 /* mov  r4, #0 */
 565                 0xE013,                                 /* b    ncomp */
 566                                                                 /* nbyte: */
 567                 0x5D11,                                 /* ldrb r1, [r2, r4] */
 568                 0xF8DF, 0x7028,                 /* ldr          r7, CRC32XOR */
 569                 0xEA80, 0x6001,                 /* eor          r0, r0, r1, asl #24 */
 570
 571                 0xF04F, 0x0500,                 /* mov          r5, #0 */
 572                                                                 /* loop: */
 573                 0x2800,                                 /* cmp          r0, #0 */
 574                 0xEA4F, 0x0640,                 /* mov          r6, r0, asl #1 */
 575                 0xF105, 0x0501,                 /* add          r5, r5, #1 */
 576                 0x4630,                                 /* mov          r0, r6 */
 577                 0xBFB8,                                 /* it           lt */
 578                 0xEA86, 0x0007,                 /* eor          r0, r6, r7 */
 579                 0x2D08,                                 /* cmp          r5, #8 */
 580                 0xD1F4,                                 /* bne          loop */
 581
 582                 0xF104, 0x0401,                 /* add  r4, r4, #1 */
 583                                                                 /* ncomp: */
 584                 0x429C,                                 /* cmp  r4, r3 */
 585                 0xD1E9,                                 /* bne  nbyte */
 586                                                                 /* end: */
 587                 0xE7FE,                                 /* b    end */
 588                 0x1DB7, 0x04C1                  /* CRC32XOR:    .word 0x04C11DB7 */
 589         };
 590
 591         uint32_t i;
 592
 593         if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
 594         {
 595                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 596         }
 597
 598         /* convert flash writing code into a buffer in target endianness */
 599         for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
 600                 if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
 601                 {
 602                         return retval;
 603                 }
 604
 605         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 606         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 607
 608         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 609         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 610
 611         buf_set_u32(reg_params[0].value, 0, 32, address);
 612         buf_set_u32(reg_params[1].value, 0, 32, count);
 613
 614         if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
 615                 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
 616         {
 617                 LOG_ERROR("error executing cortex_m3 crc algorithm");
 618                 destroy_reg_param(&reg_params[0]);
 619                 destroy_reg_param(&reg_params[1]);
 620                 target_free_working_area(target, crc_algorithm);
 621                 return retval;
 622         }
 623
 624         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 625
 626         destroy_reg_param(&reg_params[0]);
 627         destroy_reg_param(&reg_params[1]);
 628
 629         target_free_working_area(target, crc_algorithm);
 630
 631         return ERROR_OK;
 632 }
 633
 634 /** Checks whether a memory region is zeroed. */
 635 int armv7m_blank_check_memory(struct target *target,
 636                 uint32_t address, uint32_t count, uint32_t* blank)
 637 {
 638         struct working_area *erase_check_algorithm;
 639         struct reg_param reg_params[3];
 640         struct armv7m_algorithm armv7m_info;
 641         int retval;
 642         uint32_t i;
 643
 644         static const uint16_t erase_check_code[] =
 645         {
 646                 /* loop: */
 647                 0xF810, 0x3B01,         /* ldrb r3, [r0], #1 */
 648                 0xEA02, 0x0203,         /* and  r2, r2, r3 */
 649                 0x3901,                         /* subs r1, r1, #1 */
 650                 0xD1F9,                         /* bne  loop */
 651                 /* end: */
 652                 0xE7FE,                         /* b    end */
 653         };
 654
 655         /* make sure we have a working area */
 656         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
 657         {
 658                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 659         }
 660
 661         /* convert flash writing code into a buffer in target endianness */
 662         for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
 663                 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
 664
 665         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 666         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 667
 668         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 669         buf_set_u32(reg_params[0].value, 0, 32, address);
 670
 671         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 672         buf_set_u32(reg_params[1].value, 0, 32, count);
 673
 674         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 675         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
 676
 677         if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 678                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
 679         {
 680                 destroy_reg_param(&reg_params[0]);
 681                 destroy_reg_param(&reg_params[1]);
 682                 destroy_reg_param(&reg_params[2]);
 683                 target_free_working_area(target, erase_check_algorithm);
 684                 return 0;
 685         }
 686
 687         *blank = buf_get_u32(reg_params[2].value, 0, 32);
 688
 689         destroy_reg_param(&reg_params[0]);
 690         destroy_reg_param(&reg_params[1]);
 691         destroy_reg_param(&reg_params[2]);
 692
 693         target_free_working_area(target, erase_check_algorithm);
 694
 695         return ERROR_OK;
 696 }
 697
 698 /*--------------------------------------------------------------------------*/
 699
 700 /*
 701  * Only stuff below this line should need to verify that its target
 702  * is an ARMv7-M node.
 703  *
 704  * FIXME yet none of it _does_ verify target types yet!
 705  */
 706
 707
 708 /*
 709  * Return the debug ap baseaddress in hexadecimal;
 710  * no extra output to simplify script processing
 711  */
 712 COMMAND_HANDLER(handle_dap_baseaddr_command)
 713 {
 714         struct target *target = get_current_target(CMD_CTX);
 715         struct armv7m_common *armv7m = target_to_armv7m(target);
 716         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 717         uint32_t apsel, apselsave, baseaddr;
 718         int retval;
 719
 720         apselsave = swjdp->apsel;
 721         switch (CMD_ARGC) {
 722         case 0:
 723                 apsel = swjdp->apsel;
 724                 break;
 725         case 1:
 726                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
 727                 break;
 728         default:
 729                 return ERROR_COMMAND_SYNTAX_ERROR;
 730         }
 731
 732         if (apselsave != apsel)
 733                 dap_ap_select(swjdp, apsel);
 734
 735         dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
 736         retval = swjdp_transaction_endcheck(swjdp);
 737         command_print(CMD_CTX, "0x%8.8" PRIx32 "", baseaddr);
 738
 739         if (apselsave != apsel)
 740                 dap_ap_select(swjdp, apselsave);
 741
 742         return retval;
 743 }
 744
 745 /*
 746  * Return the debug ap id in hexadecimal;
 747  * no extra output to simplify script processing
 748  */
 749 COMMAND_HANDLER(handle_dap_apid_command)
 750 {
 751         struct target *target = get_current_target(CMD_CTX);
 752         struct armv7m_common *armv7m = target_to_armv7m(target);
 753         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 754
 755         return CALL_COMMAND_HANDLER(dap_apid_command, swjdp);
 756 }
 757
 758 COMMAND_HANDLER(handle_dap_apsel_command)
 759 {
 760         struct target *target = get_current_target(CMD_CTX);
 761         struct armv7m_common *armv7m = target_to_armv7m(target);
 762         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 763
 764         return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp);
 765 }
 766
 767 COMMAND_HANDLER(handle_dap_memaccess_command)
 768 {
 769         struct target *target = get_current_target(CMD_CTX);
 770         struct armv7m_common *armv7m = target_to_armv7m(target);
 771         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 772
 773         return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp);
 774 }
 775
 776
 777 COMMAND_HANDLER(handle_dap_info_command)
 778 {
 779         struct target *target = get_current_target(CMD_CTX);
 780         struct armv7m_common *armv7m = target_to_armv7m(target);
 781         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 782         uint32_t apsel;
 783
 784         switch (CMD_ARGC) {
 785         case 0:
 786                 apsel = swjdp->apsel;
 787                 break;
 788         case 1:
 789                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
 790                 break;
 791         default:
 792                 return ERROR_COMMAND_SYNTAX_ERROR;
 793         }
 794
 795         return dap_info_command(CMD_CTX, swjdp, apsel);
 796 }
 797
 798 static const struct command_registration armv7m_exec_command_handlers[] = {
 799         {
 800                 .name = "info",
 801                 .handler = &handle_dap_info_command,
 802                 .mode = COMMAND_EXEC,
 803                 .help = "dap info for ap [num], "
 804                         "default currently selected AP",
 805         },
 806         {
 807                 .name = "apsel",
 808                 .handler = &handle_dap_apsel_command,
 809                 .mode = COMMAND_EXEC,
 810                 .help = "select a different AP [num] (default 0)",
 811         },
 812         {
 813                 .name = "apid",
 814                 .handler = &handle_dap_apid_command,
 815                 .mode = COMMAND_EXEC,
 816                 .help = "return id reg from AP [num], "
 817                         "default currently selected AP",
 818         },
 819         {
 820                 .name = "baseaddr",
 821                 .handler = &handle_dap_baseaddr_command,
 822                 .mode = COMMAND_EXEC,
 823                 .help = "return debug base address from AP [num], "
 824                         "default currently selected AP",
 825         },
 826         {
 827                 .name = "memaccess",
 828                 .handler = &handle_dap_memaccess_command,
 829                 .mode = COMMAND_EXEC,
 830                 .help = "set/get number of extra tck for mem-ap memory "
 831                         "bus access [0-255]",
 832         },
 833         COMMAND_REGISTRATION_DONE
 834 };
 835 const struct command_registration armv7m_command_handlers[] = {
 836         {
 837                 .name = "dap",
 838                 .mode = COMMAND_ANY,
 839                 .help = "Cortex DAP command group",
 840                 .chain = armv7m_exec_command_handlers,
 841         },
 842         COMMAND_REGISTRATION_DONE
 843 };