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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  12  *   oyvind.harboe@zylin.com                                               *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  *                                                                         *
  29  *      ARMv7-M Architecture, Application Level Reference Manual               *
  30  *              ARM DDI 0405C (September 2008)                             *
  31  *                                                                         *
  32  ***************************************************************************/
  33 #ifdef HAVE_CONFIG_H
  34 #include "config.h"
  35 #endif
  36
  37 #include "breakpoints.h"
  38 #include "armv7m.h"
  39
  40 #define ARRAY_SIZE(x)   ((int)(sizeof(x)/sizeof((x)[0])))
  41
  42
  43 #if 0
  44 #define _DEBUG_INSTRUCTION_EXECUTION_
  45 #endif
  46
  47 /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
  48 char *armv7m_mode_strings[] =
  49 {
  50         "Thread", "Thread (User)", "Handler",
  51 };
  52
  53 static char *armv7m_exception_strings[] =
  54 {
  55         "", "Reset", "NMI", "HardFault",
  56         "MemManage", "BusFault", "UsageFault", "RESERVED",
  57         "RESERVED", "RESERVED", "RESERVED", "SVCall",
  58         "DebugMonitor", "RESERVED", "PendSV", "SysTick"
  59 };
  60
  61 /* FIXME these dummies are IDENTICAL to the armv4_5, arm11, and armv7a
  62  * ones... except for naming/scoping
  63  */
  64 static uint8_t armv7m_gdb_dummy_fp_value[12];
  65
  66 static struct reg armv7m_gdb_dummy_fp_reg =
  67 {
  68         .name = "GDB dummy floating-point register",
  69         .value = armv7m_gdb_dummy_fp_value,
  70         .dirty = 0,
  71         .valid = 1,
  72         .size = 96,
  73         .arch_info = NULL,
  74         .arch_type = 0,
  75 };
  76
  77 static uint8_t armv7m_gdb_dummy_fps_value[4];
  78
  79 static struct reg armv7m_gdb_dummy_fps_reg =
  80 {
  81         .name = "GDB dummy floating-point status register",
  82         .value = armv7m_gdb_dummy_fps_value,
  83         .dirty = 0,
  84         .valid = 1,
  85         .size = 32,
  86         .arch_info = NULL,
  87         .arch_type = 0,
  88 };
  89
  90 #ifdef ARMV7_GDB_HACKS
  91 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
  92
  93 struct reg armv7m_gdb_dummy_cpsr_reg =
  94 {
  95         .name = "GDB dummy cpsr register",
  96         .value = armv7m_gdb_dummy_cpsr_value,
  97         .dirty = 0,
  98         .valid = 1,
  99         .size = 32,
 100         .arch_info = NULL,
 101         .arch_type = 0,
 102 };
 103 #endif
 104
 105 /*
 106  * These registers are not memory-mapped.  The ARMv7-M profile includes
 107  * memory mapped registers too, such as for the NVIC (interrupt controller)
 108  * and SysTick (timer) modules; those can mostly be treated as peripherals.
 109  *
 110  * The ARMv6-M profile is almost identical in this respect, except that it
 111  * doesn't include basepri or faultmask registers.
 112  */
 113 static const struct {
 114         unsigned id;
 115         char *name;
 116         unsigned bits;
 117 } armv7m_regs[] = {
 118         { ARMV7M_R0, "r0", 32 },
 119         { ARMV7M_R1, "r1", 32 },
 120         { ARMV7M_R2, "r2", 32 },
 121         { ARMV7M_R3, "r3", 32 },
 122
 123         { ARMV7M_R4, "r4", 32 },
 124         { ARMV7M_R5, "r5", 32 },
 125         { ARMV7M_R6, "r6", 32 },
 126         { ARMV7M_R7, "r7", 32 },
 127
 128         { ARMV7M_R8, "r8", 32 },
 129         { ARMV7M_R9, "r9", 32 },
 130         { ARMV7M_R10, "r10", 32 },
 131         { ARMV7M_R11, "r11", 32 },
 132
 133         { ARMV7M_R12, "r12", 32 },
 134         { ARMV7M_R13, "sp", 32 },
 135         { ARMV7M_R14, "lr", 32 },
 136         { ARMV7M_PC, "pc", 32 },
 137
 138         { ARMV7M_xPSR, "xPSR", 32 },
 139         { ARMV7M_MSP, "msp", 32 },
 140         { ARMV7M_PSP, "psp", 32 },
 141
 142         { ARMV7M_PRIMASK, "primask", 1 },
 143         { ARMV7M_BASEPRI, "basepri", 8 },
 144         { ARMV7M_FAULTMASK, "faultmask", 1 },
 145         { ARMV7M_CONTROL, "control", 2 },
 146 };
 147
 148 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
 149
 150 static int armv7m_core_reg_arch_type = -1;
 151
 152 /**
 153  * Restores target context using the cache of core registers set up
 154  * by armv7m_build_reg_cache(), calling optional core-specific hooks.
 155  */
 156 int armv7m_restore_context(struct target *target)
 157 {
 158         int i;
 159         struct armv7m_common *armv7m = target_to_armv7m(target);
 160
 161         LOG_DEBUG(" ");
 162
 163         if (armv7m->pre_restore_context)
 164                 armv7m->pre_restore_context(target);
 165
 166         for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
 167         {
 168                 if (armv7m->core_cache->reg_list[i].dirty)
 169                 {
 170                         armv7m->write_core_reg(target, i);
 171                 }
 172         }
 173
 174         if (armv7m->post_restore_context)
 175                 armv7m->post_restore_context(target);
 176
 177         return ERROR_OK;
 178 }
 179
 180 /* Core state functions */
 181
 182 /**
 183  * Maps ISR number (from xPSR) to name.
 184  * Note that while names and meanings for the first sixteen are standardized
 185  * (with zero not a true exception), external interrupts are only numbered.
 186  * They are assigned by vendors, which generally assign different numbers to
 187  * peripherals (such as UART0 or a USB peripheral controller).
 188  */
 189 char *armv7m_exception_string(int number)
 190 {
 191         static char enamebuf[32];
 192
 193         if ((number < 0) | (number > 511))
 194                 return "Invalid exception";
 195         if (number < 16)
 196                 return armv7m_exception_strings[number];
 197         sprintf(enamebuf, "External Interrupt(%i)", number - 16);
 198         return enamebuf;
 199 }
 200
 201 static int armv7m_get_core_reg(struct reg *reg)
 202 {
 203         int retval;
 204         struct armv7m_core_reg *armv7m_reg = reg->arch_info;
 205         struct target *target = armv7m_reg->target;
 206         struct armv7m_common *armv7m = target_to_armv7m(target);
 207
 208         if (target->state != TARGET_HALTED)
 209         {
 210                 return ERROR_TARGET_NOT_HALTED;
 211         }
 212
 213         retval = armv7m->read_core_reg(target, armv7m_reg->num);
 214
 215         return retval;
 216 }
 217
 218 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
 219 {
 220         struct armv7m_core_reg *armv7m_reg = reg->arch_info;
 221         struct target *target = armv7m_reg->target;
 222         uint32_t value = buf_get_u32(buf, 0, 32);
 223
 224         if (target->state != TARGET_HALTED)
 225         {
 226                 return ERROR_TARGET_NOT_HALTED;
 227         }
 228
 229         buf_set_u32(reg->value, 0, 32, value);
 230         reg->dirty = 1;
 231         reg->valid = 1;
 232
 233         return ERROR_OK;
 234 }
 235
 236 static int armv7m_read_core_reg(struct target *target, int num)
 237 {
 238         uint32_t reg_value;
 239         int retval;
 240         struct armv7m_core_reg * armv7m_core_reg;
 241         struct armv7m_common *armv7m = target_to_armv7m(target);
 242
 243         if ((num < 0) || (num >= ARMV7M_NUM_REGS))
 244                 return ERROR_INVALID_ARGUMENTS;
 245
 246         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 247         retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
 248         buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
 249         armv7m->core_cache->reg_list[num].valid = 1;
 250         armv7m->core_cache->reg_list[num].dirty = 0;
 251
 252         return retval;
 253 }
 254
 255 static int armv7m_write_core_reg(struct target *target, int num)
 256 {
 257         int retval;
 258         uint32_t reg_value;
 259         struct armv7m_core_reg *armv7m_core_reg;
 260         struct armv7m_common *armv7m = target_to_armv7m(target);
 261
 262         if ((num < 0) || (num >= ARMV7M_NUM_REGS))
 263                 return ERROR_INVALID_ARGUMENTS;
 264
 265         reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
 266         armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
 267         retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
 268         if (retval != ERROR_OK)
 269         {
 270                 LOG_ERROR("JTAG failure");
 271                 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 272                 return ERROR_JTAG_DEVICE_ERROR;
 273         }
 274         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 275         armv7m->core_cache->reg_list[num].valid = 1;
 276         armv7m->core_cache->reg_list[num].dirty = 0;
 277
 278         return ERROR_OK;
 279 }
 280
 281 /** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */
 282 int armv7m_invalidate_core_regs(struct target *target)
 283 {
 284         struct armv7m_common *armv7m = target_to_armv7m(target);
 285         int i;
 286
 287         for (i = 0; i < armv7m->core_cache->num_regs; i++)
 288         {
 289                 armv7m->core_cache->reg_list[i].valid = 0;
 290                 armv7m->core_cache->reg_list[i].dirty = 0;
 291         }
 292
 293         return ERROR_OK;
 294 }
 295
 296 /**
 297  * Returns generic ARM userspace registers to GDB.
 298  * GDB doesn't quite understand that most ARMs don't have floating point
 299  * hardware, so this also fakes a set of long-obsolete FPA registers that
 300  * are not used in EABI based software stacks.
 301  */
 302 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
 303 {
 304         struct armv7m_common *armv7m = target_to_armv7m(target);
 305         int i;
 306
 307         *reg_list_size = 26;
 308         *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 309
 310         /*
 311          * GDB register packet format for ARM:
 312          *  - the first 16 registers are r0..r15
 313          *  - (obsolete) 8 FPA registers
 314          *  - (obsolete) FPA status
 315          *  - CPSR
 316          */
 317         for (i = 0; i < 16; i++)
 318         {
 319                 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
 320         }
 321
 322         for (i = 16; i < 24; i++)
 323         {
 324                 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
 325         }
 326
 327         (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
 328
 329 #ifdef ARMV7_GDB_HACKS
 330         /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
 331         (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
 332
 333         /* ARMV7M is always in thumb mode, try to make GDB understand this
 334          * if it does not support this arch */
 335         *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
 336 #else
 337         (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
 338 #endif
 339
 340         return ERROR_OK;
 341 }
 342
 343 /* run to exit point. return error if exit point was not reached. */
 344 static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m)
 345 {
 346         uint32_t pc;
 347         int retval;
 348         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 349          * sequence to write register values to the processor and the read them back */
 350         if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
 351         {
 352                 return retval;
 353         }
 354
 355         retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
 356         /* If the target fails to halt due to the breakpoint, force a halt */
 357         if (retval != ERROR_OK || target->state != TARGET_HALTED)
 358         {
 359                 if ((retval = target_halt(target)) != ERROR_OK)
 360                         return retval;
 361                 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
 362                 {
 363                         return retval;
 364                 }
 365                 return ERROR_TARGET_TIMEOUT;
 366         }
 367
 368         armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 369         if (pc != exit_point)
 370         {
 371                 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
 372                 return ERROR_TARGET_TIMEOUT;
 373         }
 374
 375         return ERROR_OK;
 376 }
 377
 378 /** Runs a Thumb algorithm in the target. */
 379 int armv7m_run_algorithm(struct target *target,
 380         int num_mem_params, struct mem_param *mem_params,
 381         int num_reg_params, struct reg_param *reg_params,
 382         uint32_t entry_point, uint32_t exit_point,
 383         int timeout_ms, void *arch_info)
 384 {
 385         struct armv7m_common *armv7m = target_to_armv7m(target);
 386         struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
 387         enum armv7m_mode core_mode = armv7m->core_mode;
 388         int retval = ERROR_OK;
 389         int i;
 390         uint32_t context[ARMV7M_NUM_REGS];
 391
 392         if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
 393         {
 394                 LOG_ERROR("current target isn't an ARMV7M target");
 395                 return ERROR_TARGET_INVALID;
 396         }
 397
 398         if (target->state != TARGET_HALTED)
 399         {
 400                 LOG_WARNING("target not halted");
 401                 return ERROR_TARGET_NOT_HALTED;
 402         }
 403
 404         /* refresh core register cache */
 405         /* Not needed if core register cache is always consistent with target process state */
 406         for (i = 0; i < ARMV7M_NUM_REGS; i++)
 407         {
 408                 if (!armv7m->core_cache->reg_list[i].valid)
 409                         armv7m->read_core_reg(target, i);
 410                 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 411         }
 412
 413         for (i = 0; i < num_mem_params; i++)
 414         {
 415                 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 416                         return retval;
 417         }
 418
 419         for (i = 0; i < num_reg_params; i++)
 420         {
 421                 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 422 //              uint32_t regvalue;
 423
 424                 if (!reg)
 425                 {
 426                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 427                         exit(-1);
 428                 }
 429
 430                 if (reg->size != reg_params[i].size)
 431                 {
 432                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 433                         exit(-1);
 434                 }
 435
 436 //              regvalue = buf_get_u32(reg_params[i].value, 0, 32);
 437                 armv7m_set_core_reg(reg, reg_params[i].value);
 438         }
 439
 440         if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
 441         {
 442                 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 443                 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
 444                                 0, 1, armv7m_algorithm_info->core_mode);
 445                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
 446                 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
 447         }
 448
 449         /* REVISIT speed things up (3% or so in one case) by requiring
 450          * algorithms to include a BKPT instruction at each exit point.
 451          * This eliminates overheads of adding/removing a breakpoint.
 452          */
 453
 454         /* ARMV7M always runs in Thumb state */
 455         if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
 456         {
 457                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
 458                 return ERROR_TARGET_FAILURE;
 459         }
 460
 461         retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
 462
 463         breakpoint_remove(target, exit_point);
 464
 465         if (retval != ERROR_OK)
 466         {
 467                 return retval;
 468         }
 469
 470         /* Read memory values to mem_params[] */
 471         for (i = 0; i < num_mem_params; i++)
 472         {
 473                 if (mem_params[i].direction != PARAM_OUT)
 474                         if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 475                         {
 476                                 return retval;
 477                         }
 478         }
 479
 480         /* Copy core register values to reg_params[] */
 481         for (i = 0; i < num_reg_params; i++)
 482         {
 483                 if (reg_params[i].direction != PARAM_OUT)
 484                 {
 485                         struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 486
 487                         if (!reg)
 488                         {
 489                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 490                                 exit(-1);
 491                         }
 492
 493                         if (reg->size != reg_params[i].size)
 494                         {
 495                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 496                                 exit(-1);
 497                         }
 498
 499                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 500                 }
 501         }
 502
 503         for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
 504         {
 505                 uint32_t regvalue;
 506                 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 507                 if (regvalue != context[i])
 508                 {
 509                         LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
 510                                 armv7m->core_cache->reg_list[i].name, context[i]);
 511                         buf_set_u32(armv7m->core_cache->reg_list[i].value,
 512                                         0, 32, context[i]);
 513                         armv7m->core_cache->reg_list[i].valid = 1;
 514                         armv7m->core_cache->reg_list[i].dirty = 1;
 515                 }
 516         }
 517
 518         armv7m->core_mode = core_mode;
 519
 520         return retval;
 521 }
 522
 523 /** Logs summary of ARMv7-M state for a halted target. */
 524 int armv7m_arch_state(struct target *target)
 525 {
 526         struct armv7m_common *armv7m = target_to_armv7m(target);
 527         uint32_t ctrl, sp;
 528
 529         ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
 530         sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 531
 532         LOG_USER("target halted due to %s, current mode: %s %s\n"
 533                 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
 534                 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
 535                                 target->debug_reason)->name,
 536                 armv7m_mode_strings[armv7m->core_mode],
 537                 armv7m_exception_string(armv7m->exception_number),
 538                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
 539                 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32),
 540                 (ctrl & 0x02) ? 'p' : 'm',
 541                 sp);
 542
 543         return ERROR_OK;
 544 }
 545
 546 /** Builds cache of architecturally defined registers.  */
 547 struct reg_cache *armv7m_build_reg_cache(struct target *target)
 548 {
 549         struct armv7m_common *armv7m = target_to_armv7m(target);
 550         int num_regs = ARMV7M_NUM_REGS;
 551         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 552         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 553         struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
 554         struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
 555         int i;
 556
 557         if (armv7m_core_reg_arch_type == -1)
 558         {
 559                 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
 560         }
 561
 562         register_init_dummy(&armv7m_gdb_dummy_fps_reg);
 563 #ifdef ARMV7_GDB_HACKS
 564         register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
 565 #endif
 566         register_init_dummy(&armv7m_gdb_dummy_fp_reg);
 567
 568         /* Build the process context cache */
 569         cache->name = "arm v7m registers";
 570         cache->next = NULL;
 571         cache->reg_list = reg_list;
 572         cache->num_regs = num_regs;
 573         (*cache_p) = cache;
 574         armv7m->core_cache = cache;
 575
 576         for (i = 0; i < num_regs; i++)
 577         {
 578                 arch_info[i].num = armv7m_regs[i].id;
 579                 arch_info[i].target = target;
 580                 arch_info[i].armv7m_common = armv7m;
 581                 reg_list[i].name = armv7m_regs[i].name;
 582                 reg_list[i].size = armv7m_regs[i].bits;
 583                 reg_list[i].value = calloc(1, 4);
 584                 reg_list[i].dirty = 0;
 585                 reg_list[i].valid = 0;
 586                 reg_list[i].arch_type = armv7m_core_reg_arch_type;
 587                 reg_list[i].arch_info = &arch_info[i];
 588         }
 589
 590         return cache;
 591 }
 592
 593 /** Sets up target as a generic ARMv7-M core */
 594 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
 595 {
 596         /* register arch-specific functions */
 597
 598         target->arch_info = armv7m;
 599         armv7m->read_core_reg = armv7m_read_core_reg;
 600         armv7m->write_core_reg = armv7m_write_core_reg;
 601
 602         return ERROR_OK;
 603 }
 604
 605 /** Generates a CRC32 checksum of a memory region. */
 606 int armv7m_checksum_memory(struct target *target,
 607                 uint32_t address, uint32_t count, uint32_t* checksum)
 608 {
 609         struct working_area *crc_algorithm;
 610         struct armv7m_algorithm armv7m_info;
 611         struct reg_param reg_params[2];
 612         int retval;
 613
 614         static const uint16_t cortex_m3_crc_code[] = {
 615                 0x4602,                                 /* mov  r2, r0 */
 616                 0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
 617                 0x460B,                                 /* mov  r3, r1 */
 618                 0xF04F, 0x0400,                 /* mov  r4, #0 */
 619                 0xE013,                                 /* b    ncomp */
 620                                                                 /* nbyte: */
 621                 0x5D11,                                 /* ldrb r1, [r2, r4] */
 622                 0xF8DF, 0x7028,                 /* ldr          r7, CRC32XOR */
 623                 0xEA80, 0x6001,                 /* eor          r0, r0, r1, asl #24 */
 624
 625                 0xF04F, 0x0500,                 /* mov          r5, #0 */
 626                                                                 /* loop: */
 627                 0x2800,                                 /* cmp          r0, #0 */
 628                 0xEA4F, 0x0640,                 /* mov          r6, r0, asl #1 */
 629                 0xF105, 0x0501,                 /* add          r5, r5, #1 */
 630                 0x4630,                                 /* mov          r0, r6 */
 631                 0xBFB8,                                 /* it           lt */
 632                 0xEA86, 0x0007,                 /* eor          r0, r6, r7 */
 633                 0x2D08,                                 /* cmp          r5, #8 */
 634                 0xD1F4,                                 /* bne          loop */
 635
 636                 0xF104, 0x0401,                 /* add  r4, r4, #1 */
 637                                                                 /* ncomp: */
 638                 0x429C,                                 /* cmp  r4, r3 */
 639                 0xD1E9,                                 /* bne  nbyte */
 640                                                                 /* end: */
 641                 0xE7FE,                                 /* b    end */
 642                 0x1DB7, 0x04C1                  /* CRC32XOR:    .word 0x04C11DB7 */
 643         };
 644
 645         uint32_t i;
 646
 647         if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
 648         {
 649                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 650         }
 651
 652         /* convert flash writing code into a buffer in target endianness */
 653         for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
 654                 if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
 655                 {
 656                         return retval;
 657                 }
 658
 659         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 660         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 661
 662         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 663         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 664
 665         buf_set_u32(reg_params[0].value, 0, 32, address);
 666         buf_set_u32(reg_params[1].value, 0, 32, count);
 667
 668         if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
 669                 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
 670         {
 671                 LOG_ERROR("error executing cortex_m3 crc algorithm");
 672                 destroy_reg_param(&reg_params[0]);
 673                 destroy_reg_param(&reg_params[1]);
 674                 target_free_working_area(target, crc_algorithm);
 675                 return retval;
 676         }
 677
 678         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 679
 680         destroy_reg_param(&reg_params[0]);
 681         destroy_reg_param(&reg_params[1]);
 682
 683         target_free_working_area(target, crc_algorithm);
 684
 685         return ERROR_OK;
 686 }
 687
 688 /** Checks whether a memory region is zeroed. */
 689 int armv7m_blank_check_memory(struct target *target,
 690                 uint32_t address, uint32_t count, uint32_t* blank)
 691 {
 692         struct working_area *erase_check_algorithm;
 693         struct reg_param reg_params[3];
 694         struct armv7m_algorithm armv7m_info;
 695         int retval;
 696         uint32_t i;
 697
 698         static const uint16_t erase_check_code[] =
 699         {
 700                 /* loop: */
 701                 0xF810, 0x3B01,         /* ldrb r3, [r0], #1 */
 702                 0xEA02, 0x0203,         /* and  r2, r2, r3 */
 703                 0x3901,                         /* subs r1, r1, #1 */
 704                 0xD1F9,                         /* bne  loop */
 705                 /* end: */
 706                 0xE7FE,                         /* b    end */
 707         };
 708
 709         /* make sure we have a working area */
 710         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
 711         {
 712                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 713         }
 714
 715         /* convert flash writing code into a buffer in target endianness */
 716         for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
 717                 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
 718
 719         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 720         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 721
 722         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 723         buf_set_u32(reg_params[0].value, 0, 32, address);
 724
 725         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 726         buf_set_u32(reg_params[1].value, 0, 32, count);
 727
 728         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 729         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
 730
 731         if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 732                         erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
 733         {
 734                 destroy_reg_param(&reg_params[0]);
 735                 destroy_reg_param(&reg_params[1]);
 736                 destroy_reg_param(&reg_params[2]);
 737                 target_free_working_area(target, erase_check_algorithm);
 738                 return 0;
 739         }
 740
 741         *blank = buf_get_u32(reg_params[2].value, 0, 32);
 742
 743         destroy_reg_param(&reg_params[0]);
 744         destroy_reg_param(&reg_params[1]);
 745         destroy_reg_param(&reg_params[2]);
 746
 747         target_free_working_area(target, erase_check_algorithm);
 748
 749         return ERROR_OK;
 750 }
 751
 752 /*--------------------------------------------------------------------------*/
 753
 754 /*
 755  * Only stuff below this line should need to verify that its target
 756  * is an ARMv7-M node.
 757  *
 758  * FIXME yet none of it _does_ verify target types yet!
 759  */
 760
 761
 762 /*
 763  * Return the debug ap baseaddress in hexadecimal;
 764  * no extra output to simplify script processing
 765  */
 766 COMMAND_HANDLER(handle_dap_baseaddr_command)
 767 {
 768         struct target *target = get_current_target(cmd_ctx);
 769         struct armv7m_common *armv7m = target_to_armv7m(target);
 770         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 771         uint32_t apsel, apselsave, baseaddr;
 772         int retval;
 773
 774         apselsave = swjdp->apsel;
 775         switch (argc) {
 776         case 0:
 777                 apsel = swjdp->apsel;
 778                 break;
 779         case 1:
 780                 COMMAND_PARSE_NUMBER(u32, args[0], apsel);
 781                 break;
 782         default:
 783                 return ERROR_COMMAND_SYNTAX_ERROR;
 784         }
 785
 786         if (apselsave != apsel)
 787                 dap_ap_select(swjdp, apsel);
 788
 789         dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
 790         retval = swjdp_transaction_endcheck(swjdp);
 791         command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr);
 792
 793         if (apselsave != apsel)
 794                 dap_ap_select(swjdp, apselsave);
 795
 796         return retval;
 797 }
 798
 799 /*
 800  * Return the debug ap id in hexadecimal;
 801  * no extra output to simplify script processing
 802  */
 803 COMMAND_HANDLER(handle_dap_apid_command)
 804 {
 805         struct target *target = get_current_target(cmd_ctx);
 806         struct armv7m_common *armv7m = target_to_armv7m(target);
 807         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 808
 809         return CALL_COMMAND_HANDLER(dap_apid_command, swjdp);
 810 }
 811
 812 COMMAND_HANDLER(handle_dap_apsel_command)
 813 {
 814         struct target *target = get_current_target(cmd_ctx);
 815         struct armv7m_common *armv7m = target_to_armv7m(target);
 816         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 817
 818         return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp);
 819 }
 820
 821 COMMAND_HANDLER(handle_dap_memaccess_command)
 822 {
 823         struct target *target = get_current_target(cmd_ctx);
 824         struct armv7m_common *armv7m = target_to_armv7m(target);
 825         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 826
 827         return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp);
 828 }
 829
 830
 831 COMMAND_HANDLER(handle_dap_info_command)
 832 {
 833         struct target *target = get_current_target(cmd_ctx);
 834         struct armv7m_common *armv7m = target_to_armv7m(target);
 835         struct swjdp_common *swjdp = &armv7m->swjdp_info;
 836         uint32_t apsel;
 837
 838         switch (argc) {
 839         case 0:
 840                 apsel = swjdp->apsel;
 841                 break;
 842         case 1:
 843                 COMMAND_PARSE_NUMBER(u32, args[0], apsel);
 844                 break;
 845         default:
 846                 return ERROR_COMMAND_SYNTAX_ERROR;
 847         }
 848
 849         return dap_info_command(cmd_ctx, swjdp, apsel);
 850 }
 851
 852 /** Registers commands used to access DAP resources. */
 853 int armv7m_register_commands(struct command_context *cmd_ctx)
 854 {
 855         struct command *arm_adi_v5_dap_cmd;
 856
 857         arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
 858                         NULL, COMMAND_ANY,
 859                         "cortex dap specific commands");
 860
 861         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info",
 862                         handle_dap_info_command, COMMAND_EXEC,
 863                         "Displays dap info for ap [num],"
 864                         "default currently selected AP");
 865         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel",
 866                         handle_dap_apsel_command, COMMAND_EXEC,
 867                         "Select a different AP [num] (default 0)");
 868         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid",
 869                         handle_dap_apid_command, COMMAND_EXEC,
 870                         "Displays id reg from AP [num], "
 871                         "default currently selected AP");
 872         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr",
 873                         handle_dap_baseaddr_command, COMMAND_EXEC,
 874                         "Displays debug base address from AP [num],"
 875                         "default currently selected AP");
 876         register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess",
 877                         handle_dap_memaccess_command, COMMAND_EXEC,
 878                         "set/get number of extra tck for mem-ap "
 879                         "memory bus access [0-255]");
 880
 881         return ERROR_OK;
 882 }